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Messages from 8150

Article: 8150
Subject: Re: what is metastability time of a flip_flop
From: Steve Goodwin <steve@p2cl_DSPM.demon.co.uk>
Date: Fri, 21 Nov 1997 10:39:37 +0000
Links: << >>  << T >>  << A >>
In article <652vrc$54c@src-news.pa.dec.com>, Hal Murray
<murray@pa.dec.com> writes
>In article <3474c626.1321210@news.mv.net>, jeff@wa1hco.mv.com (Jeff Millar) 
>writes:
>
>>                                           A few manufacturers make
>> metastable hardened FF that may take longer to settle to high or low
>> but will monotonically transition...thus clocking all down stream
>> devices equally.
>
>Would you trust a design that depended upon that characteristic?
>
>Metastability is a tricky area.  My semiconductor physics is weak
>enough that I can't prove that it is or isn't possible to build
>a FF that makes a clean transition.  [I've seen enough pictures
>in ap-notes to know that it is possible to build a FF that does
>summersaults.]
>
>I've built my share of kludgy logic, but I try real hard to avoid
>clocking things with a FF, especially one that might be metastable.

I would be interested in how you avoid this situation.

My understanding is that as soon as you introduce into a circuit a clock
and an incoming signal thats not synch'd to that clock you involve
metastability. There *will* be times when the incoming signal
transitions at the wrong time.

In my case I use two D Type FF in series (or equivalent) and (as much as
I can <g>) make sure that the time between clock edges allows the first
FF to 'settle' with some kind of very high likelyhood of success. I use
Xilinx stuff and provided the clock is reasonable (can't quote what that
means off hand) the chances of there being a problem are low enough for
me to fly with it (maybe not the case for other bugs of course!)

There is a reasonable Xilinx app note on some of this subject.

Regards
-- 
Steve Goodwin...  De-spamming active, remove any _DSPM from address
Article: 8151
Subject: Re: what is metastability time of a flip_flop
From: Rick Filipkewicz <rick@xxxxz.co.uk>
Date: Fri, 21 Nov 1997 11:35:51 +0000
Links: << >>  << T >>  << A >>
There seems to be a generally accepted statistical formula that relates 
the MTBF to the time taken for the metastable condition to resolve
itself. Quoting from the Xilinx appnote XAPP067:

MTBF = exp(C2 * tMET)/(C1 * Fc * Fd)

Where  tMET = time for metastability to resolve itself.
       Fc = clock frequency.
       Fd = data  (D input) frequency.
       C1 = constant related to the size of the metastability window.
       C1 = constant related to how fast the metastable condtion
is                  resloved.

One way to use this goes like this. Say you are clocking an async input 
at 50MHz which is followed by another register who's Tco = 7,  Tsu = 4
nsec and you want to know the probability that a metastable condition
will not resolve itself before the next clock edge. In this case tMET =
20 - 7 - 4 = 9nsec.

Just plug in the values for C1, C2, Fd (Fc = 50MHz) and 
derive MTBF. Alternatively you can decide what MTBF is acceptable,
invert the equation and derive the relationship between tMET & Fc
allowing you to determine the max acceptable frequency.


_________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 8152
Subject: Re: Dr watson & M1
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 21 Nov 1997 10:12:54 -0500
Links: << >>  << T >>  << A >>
L.Brodbeck KS/EF2C 58/2/15 #7334 wrote:
> 
> Kim Hofmans wrote:
> >
> > Most of the time while using the M1 software for Xilinx (viewdraw, epic,
> > etc..)
> > I get the message : "Dr Watson : application error " followed by "not enough
> > storage to complete this operation".
> >
> > Anyone having similar problems ?
> > The platform I'm using : PentiumII, NT4.0
> >
> > Setting the registry higher didn't seem to solve the problem.
> >
how much RAM do you have in the machine?
Article: 8153
Subject: Gigaops Reconfiguration board
From: Ken Chung <ckchung@cse.cuhk.edu.hk>
Date: 21 Nov 1997 15:27:08 GMT
Links: << >>  << T >>  << A >>
Hello,

	I am new to Gigaops board. My development tool is VHDL from 
synopsys. I got a .bit file and wrote a .lnk file successfully. 
Then, I got the .exe file by visual C++. 

	But, after I executed it, it seems that the communication has 
something wrong. I guess that I can't send the inputs to the FPGA. 
So, anything wrong? Should I need to explicitly define the HBUS protocol?


Ken
Article: 8154
Subject: Re: Q: HDLC packet size in V5.2
From: ugowda@cc.hut.fi (Umesh Chandra Gowda)
Date: 21 Nov 1997 18:14:28 GMT
Links: << >>  << T >>  << A >>
Allan Herriman (allan.herriman@fujitsu.com.au.NOSPAM) wrote:
: Hi,
: 	I'm implementing a HDLC concentrator in VHDL on a XC5215.  It takes
: multiple 16kbit/s D channels from Basic Rate ISDN ports, concentrates them,
: and sends them (via other cards) to a V5.2 switch / phone exchange.
: 
: Question:  If ITU-T Q.921 (LAPD) states that the maximum HDLC packet size
: shall be 260 octets, why does ETS 300 324-1 (V5.2) say that the maximum
: size will be 533 octets?
: This doubles the size of my buffer ram (it's already 1Meg).

Are you sure you have to buffer the whole content? I would advise you to use a FIFO. This way a 64 byte-2 kbyte dual-port RAM should be enough. The exact amount depends on the read and write speed. In a HDLC controller that I have worked on, I needed just 64 bytes for transmission and an other 64 bytes for reception. 

: ETS 300 324-1 also refers to "too long frames" (up to 533 bytes) which must
: be accepted, but it also says that the "longest permissible frame" is 268
: bytes.  Why the difference?

Based on the text I would say that a fully complient frame would have a length shorter than 269. However, frames between 268 and 534 are considered "too long" but are still valid. Frames above 533 are invalid.  

Hope this information proves useful.

Regards,
Umesh Gowda

Article: 8155
Subject: Re: Dr watson & M1
From: tom_curran@7memecdesign.com (tom curran)
Date: Fri, 21 Nov 1997 19:27:40 GMT
Links: << >>  << T >>  << A >>
I have had this same problem  with my Pentium Pro and NT4.0.

The only fix I have found is to reboot the machine -- or -- go into
the task manager and kill the REVENGINE.EXE process.

Killing the process is much more fun.

tom




On Fri, 21 Nov 1997 10:58:54 +0100, "L.Brodbeck KS/EF2C 58/2/15 #7334"
<brod@lts.sel.alcatel.de> wrote:

>Kim Hofmans wrote:
>> 
>> Most of the time while using the M1 software for Xilinx (viewdraw, epic,
>> etc..)
>> I get the message : "Dr Watson : application error " followed by "not enough
>> storage to complete this operation".
>> 
>> Anyone having similar problems ?
>> The platform I'm using : PentiumII, NT4.0
>> 
>> Setting the registry higher didn't seem to solve the problem.
>> 
>> Anyone a solution ?
>> 
>> Tnx in advance !
>> 
>Better use the Vendor with A....
>
>I tried to use the M1 SW, the installation was hard work.
>
>After this i had to install the patches !!!
>
>THeni tried to proceed with the tutorial (count8) ==> failed.
>
>I couldn't fit my VHDL (Synopsys) design ==> failed !!!
>
>Have to wait for the X.... support.
>
>
>Isn't it sad.
>
>Best regards and good luck.
>
>Lothar Brodbeck
>
>
>p.s. sorry that i couldn't support you, but sometimes
>it is maybe helpful that you kbnowe that you are not 
>the only one

Article: 8156
Subject: Re: what is metastability time of a flip_flop
From: daveb@iinet.net.au (David R Brooks)
Date: Fri, 21 Nov 1997 22:57:41 GMT
Links: << >>  << T >>  << A >>
ratranch@svpal.svpal.org (Charles Mosher) wrote:

:lzh@bd748.pku.edu.cn wrote:
:: Hi.  Does anybody explain the meaning of  " metastability time of a
:: flip_flop", and what would happen if data changed in metastability time
:: of a flip_flop?  any help will be appreciated!	thanks advanced!
:
[snip]
:  Remember there are NO digital parts, only analog parts
:specified in a digital way, for digital use.  This requires hiding
:substantial analog behavior from the customer.  Meta-stability is one such
:analog behavior.

 Very, very true.

 For a to-the-max example of this, take a look at
http://www.cogs.susx.ac.uk/users/adrianth/ices96/paper.html


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 8157
Subject: field programmable gater-aid
From: Roger Blincow <"Roger Blincow"@bignet.net>
Date: Sat, 22 Nov 1997 00:30:47 -0800
Links: << >>  << T >>  << A >>
hello, there are some really interestine things at Xilinx and other fpga 
related sites, but is there an FAQ for this newsgroup? It seems there is 
no starting point for people interested in fpga technology and design. I 
would really appreciate if someone could mail me a URL or just a little 
background information. Any responses should be sent to z5c@hotmail.com, 
as i have no yet purchased a POP server on this isp.
Thanx alot,
---Roger
Article: 8158
Subject: ViewSynthesis and LogiBlox
From: Stephan Gick <gck@iis.fhg.de>
Date: Sat, 22 Nov 1997 10:34:09 +0100
Links: << >>  << T >>  << A >>
Hello,
I'm using ViewLogic ViewSynthesis 7.2.3.4 together with XILINX M1.3.7
LogiBlox. 

First Problem: 
The generated WIR File with instantiated LogiBlox components cannot be
converted to EDIF (with ViewLogic Edif Netlist Writer) because the line
LEVEL=XILINX is missing for all LogiBlox components and so the netlist
writer doesn't find the LogiBlox WIR files. (There are only EDIF
LogiBlox files)
Workaround: Check the WIR files and insert this line to all LogiBlox
components -> works, but this cannot be the solution.

Second Problem:
How can I instantiate special purpose XILINX PADs like TDO in my VHDL
description?

Any tips??

Thanx alot
Stephan  

-- 
Dipl. Ing. Stephan Gick  +  FhG IIS
Tel. +49 (0)9131-776521  +  Abteilung ESY-B
Fax: +49 (0)9131-776599  +  Am Weichselgarten 3
EMail: gck@iis.fhg.de    +  D-91058 Erlangen
http://www.iis.fhg.de/departs/esy/index.html
Article: 8159
Subject: New programmable logic article
From: edndipert@NOSPAM.postoffice.worldnet.att.net (Brian Dipert)
Date: Sat, 22 Nov 1997 14:39:09 GMT
Links: << >>  << T >>  << A >>
There's been a fair amount of discussion lately on this newsgroup
about the strengths and shortcomings of various programmable logic
cost reduction paths; 'vanilla' ASICs, using ASIC conversion service
vendors, 'Hardwires' and equivalents....plus debate on whether or not
a conversion even make sense. So....I thought I'd point out that my
article on this topic is in the new issue of EDN.

Go to <http://www.ednmag.com> and click on the 11/20/97 issue
hyperlink, then search through the table of contents. In that same
issue, I also did a short writeup on new Altera and Xilinx chips in
the Leading Edge section.

Beginning on 12/4/97 you'll have to first register, then find the
article through the website archive. As always, feedback is
appreciated!

Regards,
Brian Dipert
Technical Editor
EDN Magazine: The Design Magazine Of The Electronics Industry
1864 52nd Street
Sacramento, CA   95819
(916) 454-5242
(916) 454-5101 (fax)
***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY***
Visit me at <http://members.aol.com/bdipert>
Article: 8160
Subject: Re: Need info on runtime configurable FPGAs
From: "Brad Smallridge" <manbike@smallridge.xo.com>
Date: Sat, 22 Nov 1997 10:29:36 -0800
Links: << >>  << T >>  << A >>

Jonas Thor wrote in message <346A0CA0.E1A1778D@sm.luth.se>...
>Hi!
>
>For a seminar I have chosen the topic "Runtime Configurable
>FPGAs". I've found some articels on the web but there's still
>some information that some of you might be able to answer or
>provide me with a pointer to where I can find some documents.
>
>1) Are there any commersial available FPGAs, except Atmel and
>   Xilinx, which are runtime configurable?
>
>2) Are there any design tools that support simulation, synthesis,
>   map, place and route of runtime configurable FPGAs?


I am only familiar with the Atmel 6k series and Atmel does not have
any software that supports runtime reconfigurations of their products.
You can, however, request the download file structure by signing a
nondisclosure agreement. With this information you can make modest
changes to your design and do runtime configurations either by sending
down a complete modified design or by sending down smaller design
windows. I have used this technique only somewhat. For example,
you can send down a window of constants and they magically appear within
your design. This can save you the expense of having IO pins and shift
registers
for the purpose of communicating constants. It assumes you already have a
micro downloading your design code rather than a bootup serial Eprom.
A considerable amount of planning is necessary. First, some cells may share
resources with bus routing corners. These routing paths must remain intact
when downloading the new design. One method is to keep the corners away
from the download area.  It is only the turns that are a problem. Another
problem
is that the cells are turned on one at a time, so consideration on how this
will
affect the overall performance of your design is important.

I am just beginning to look into this technique again because I can save
considerable
amount of cells by downloading sequences of AN2 (and gate) and AN2L ( and
gate
with one inverted input) to replace EQUALITY Comparators. The mission is to
generate a pulse when a counter in the gate array matches a counter in an
external
micro. The classic way to do this is to send the micro constant down through
a shift
register, then use a Equality Comparator to match the two constants. This
requires,
for eight bit constants, 16 cells for the serial in parallel out shift
register and 24 bits for
a comparator. ( 8 cells can be saved if one of the constant is preinverted
and a special
Equality Macro is constucted).

On the other hand, if you use the window download of the Atmel parts. You
can download
the micro constant as a series of AN2 and AN2L gates that can be directly
connected to
the counter within the Atmel 6k. The AN2 and AN2L are daisy chained using an
AN2 when
the corresponding bit is 1 and an AN2L when the corresponding bit is a 0.
The AN2L gates
invert the 0s from the counter and all the daisy-chain fills with 1s
creating a pulse.
This accomplishes the same pulse effect with only 8 cells, no IO pins, and
no routing hassles.

This generally sumarizes my present ability with runtime reconfiguration of
Atmel parts. It
is more of a space saving technique rather than a runtime design
reconfiguration. I am not a
particullary sophisticated Atmel user. I don't use the simulation tools and
I haven't looked
a the Partitioning tools. Perhaps these can be helpful.

Brad Smallridge
manbike@smallridge.xo.com

>
>3) Is it possible to use VHDL or Verilog to describe a runtime
>   configurable design for both simulation and synthesis?
>
>Thanks!
>
>Jonas Thor
>i93-jtr@sm.luth.se
>


Article: 8161
Subject: Re: XACT 5.0 problem under DOS
From: z80@ds.com (Peter)
Date: Sat, 22 Nov 1997 19:34:55 GMT
Links: << >>  << T >>  << A >>
You probably need the following dir structure

      bytes  files  path
 10,386,712     35  d:\xact92
  7,818,150    185  d:\xact92\data
    167,448     36  d:\xact92\data\hmlib
     68,313      1  d:\xact92\designs
    180,348     38  d:\xact92\msg

(ignore file numbers & sizes)

taken from my 1991 software. XACT6 does not use a msg subdir.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8162
Subject: FPAA Motorola's new tech.
From: jamil.khatib@pemail.net (J. Khatib)
Date: Sat, 22 Nov 1997 20:38:05 GMT
Links: << >>  << T >>  << A >>
Please I want your help.
I can not understand what is the Idea behind the new FPAA " Field
Prgrammable Analog Arrays" technology announced by MOTOROLA.

These ICs are like teh FPGAs they can be programmed to produce not
digital functions but analog functions

Do you have any Idea how these ICs work or how they are fabricated

If you want any information about this technology check 
http://techweb.cmp.com/eet/823/

Thanks for your time
                  \\\|///
                \\  ~ ~  //
                 ( =@=@= )
+------------oOOo---(_)---oOOo-------------+
|                                          |
|e-mail: jik@planet.edu     		   |
|www.planet.edu/~jik/JamilHomepage.html    |
|www.geocities.com/SiliconValley/Pines/6639|
|					   |
|              .oooO   Oooo.               |
|              (   )   (   )               |
+---------------\ (-----) /----------------+
                 \_)   (_/
Article: 8163
Subject: Re: Need info on runtime configurable FPGAs
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sun, 23 Nov 1997 12:31:52 -0500
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> 
> Jonas Thor wrote in message <346A0CA0.E1A1778D@sm.luth.se>...
> >Hi!
> >
> >For a seminar I have chosen the topic "Runtime Configurable
> >FPGAs". I've found some articels on the web but there's still
> >some information that some of you might be able to answer or
> >provide me with a pointer to where I can find some documents.
> >
> >1) Are there any commersial available FPGAs, except Atmel and
> >   Xilinx, which are runtime configurable?
> >
> >2) Are there any design tools that support simulation, synthesis,
> >   map, place and route of runtime configurable FPGAs?
> 
I believe the motorola part also supports runt time reconfiguration, but
I have not played with their part yet.  The ATmel device requires a
considerable amount of planning of the design and layout to make sure
critical routes in the existing design are not corrupted during the
reconfiguration.  I've done this using hand place and route, at least in
the vicinity of the boundaries of the overlay you are putting in place. 
If you do a hand place and route of each overlay, you can use the
existing tools to generate windowed bitstreams to do the replacement.  I
found that it is much much easier and less headache to do a complete
design with the overlay in place over the base for each combination of
overlay and base, then do a complete reconfiguration.  This effectively
replaces just the overlay, while making sure the connections to the base
are made properly.  While the cells that are the same from
reconfiguration to reconfiguration technically are reconfigured, the new
settings are identical to the old so the effect is the same as not
changing them (register state is not changed as a result of
configuration) and they continue to operate.  

I presented a paper last year on a dynamically configured video
processor based in a MCM containing four tiled NSC Clay31 devices last
year (the CLAy 31 is essentially the same as the Atmel 6005 with a few
very minor differences in the routing resources).  That paper is
available for download on my website.  You may wish to look at it for
more details on working dynamic configuration in this part.  As of the
time I wrote that paper, there were several papers on partial
reconfiguration by the good folks at BYU.  As far as I know, none kept
the clock running during the actual configuration (this avoids a huge
set of problems involving order of configuration and what happens to a
cell if it is clocked while it is being configured).

One more thing, For the extensive handcrafting, I've found that the old
interact tool (atmel version 2) is much better than the newer tools (the
array editor in it is very fast and easy to use).  If you are doing
extensive hand place and route, try to get your hands on this tool.  The
array editor in the newer Atmel tools is painfully slow and very
clunky...I wouldn't want to do more than a couple of cells with it.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 8164
Subject: Re: what is metastability time of a flip_flop
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sun, 23 Nov 1997 13:22:54 -0500
Links: << >>  << T >>  << A >>
> 
> I would be interested in how you avoid this situation.
> 
> My understanding is that as soon as you introduce into a circuit a clock
> and an incoming signal thats not synch'd to that clock you involve
> metastability. There *will* be times when the incoming signal
> transitions at the wrong time.
> 
> In my case I use two D Type FF in series (or equivalent) and (as much as
> I can <g>) make sure that the time between clock edges allows the first
> FF to 'settle' with some kind of very high likelyhood of success. I use
> Xilinx stuff and provided the clock is reasonable (can't quote what that
> means off hand) the chances of there being a problem are low enough for
> me to fly with it (maybe not the case for other bugs of course!)
> 
> There is a reasonable Xilinx app note on some of this subject.
> 

Metastability is fairly easy to deal with.  There are two issues.  First
is to reduce the probability of a metastable event (you can never really
eliminate it totally). Second, you should design the circuit to be
tolerant of the uncertainty introduced due to a metastable event.  The
first invariably is dealt with by passing the signal through one (or a
serial chain of several) synchronizing flip-flops. If the first
flip-flop goes metastable, it may take a while to settle to a known
state.  (that flop is clocked by the destination logic's clock).  The
destination logic, doesn't look at the output from the synchronizing
flop until the next clock, so there is always one clock period to allow
the signal to settle. This eliminates ill effects caused by metastable
events lasting less than a clock period of the receiving logic. 
Obviously, the lower the clock rate of the receiving logic, the lower
the probability of a metastable event lasting longer than a clock
period.  Adding additional synchronizing flip-flops reduces the
likelyhood even more, since a long metastable event on the first one
would also have to trigger a long metastable event on the second (not
very likely with reasonable clock rates) to cause an upset in the
destination circuit.

The kicker, is that there are times when a long pipeline delay to
synchronize the signal is unacceptable in the system context.  In these
cases, the destination logic can usually be designed so that only one
flip-flop's state is determined by the incoming signal (especially in a
state machine).  If the clock rate is low and the metastability recover
time is sufficiently fast that a single level of synchronization yields
an acceptable probability of failure, the synchronization can be done by
the single flop affected in a state machine so designed.

The receiving logic should be designed to tolerate uncertainties due to
the crossing of clock domain boundaries.  This means, that it should be
designed so that only one async signal is used to control the transfer
(parallel signals cannot be depended upon to cross the boundary on the
same clock cycle), and so that the async signal affects the next state
of only one flip-flop.

Often times, an entire data bus comes crosses a clock domain boundary. 
In these cases, you cannot depend on all bits to be accepted by the
receiving clock domain on the same clock cycle.  The solution is to
write the data into a register using the sending clock domain's clock. 
SImultaneoulsy, set a flag to indicate data is available in the
register.  Then you synchronize the valid flag and use that to read the
data from the mailbox register.  I typically use a flop clocked by the
sending domain clock which toggles each time valid data is sent.  A
simple state machine generates a data valid signal when it detects a
change in the state of the toggle flop.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 8165
Subject: Which size of Xilinx Fits the DLX
From: "Yasser Y. Hanafy" <yhanafy@dataxprs.com.eg>
Date: Sun, 23 Nov 1997 11:51:07 -0800
Links: << >>  << T >>  << A >>
I am pretty sure somebody mentioned this before, but i have not been a 
regulare news reader as i used to be. I am interested in fitting the DLX 
RISC processor described in Patterson & Henessey on a Xilinx chip, but i 
am not sure which size can fit it ( if it can at all?!). My wild guess is 
that the 4085 may be able to do the job. Any comments?

-- 
===================================================================
Yasser Y. Hanafy
Assistant Professor
Electronics & Computer Eng. Dept.
Arab Academy for Science and Technology
Alexandria, Agypt
===================================================================
Article: 8166
Subject: Re: Q: HDLC packet size in V5.2
From: "Allan Herriman" <allan.herriman@fujitsu.com.au.NOSPAM>
Date: 24 Nov 1997 00:01:27 GMT
Links: << >>  << T >>  << A >>
Umesh Chandra Gowda <ugowda@cc.hut.fi> wrote in article
<654j24$fer@nntp.hut.fi>...
> Allan Herriman (allan.herriman@fujitsu.com.au.NOSPAM) wrote:
> : Hi,
> : 	I'm implementing a HDLC concentrator in VHDL on a XC5215.  It takes
> : multiple 16kbit/s D channels from Basic Rate ISDN ports, concentrates
them,
> : and sends them (via other cards) to a V5.2 switch / phone exchange.
> : 
> : Question:  If ITU-T Q.921 (LAPD) states that the maximum HDLC packet
size
> : shall be 260 octets, why does ETS 300 324-1 (V5.2) say that the maximum
> : size will be 533 octets?
> : This doubles the size of my buffer ram (it's already 1Meg).
> 
> Are you sure you have to buffer the whole content? I would advise you to
use
> a FIFO. This way a 64 byte-2 kbyte dual-port RAM should be enough. The
exact
> amount depends on the read and write speed. In a HDLC controller that I
have
> worked on, I needed just 64 bytes for transmission and an other 64 bytes
for
> reception. 

Yes, I need to buffer the whole content.  In fact, I need to buffer a
number of whole packets on each port.  This is because the concentration
factor is rather high, and I will lose packets if my buffer isn't big
enough.
By "concentration" I mean rate-adaption.

(Think about the queue size required when you have one server which is fed
by multiple input queues.)

Also, I have to receive the whole packet before I can send it because I
want to know whether the incoming packet has a correct CRC before I start
to send it out again.

Higher layer protocols allow (I think) up to seven outstanding messages per
TE.  I can have more than one TE per port.  I have several ports.  And so
on...

BTW, all the concentration happens in hardware.  I'm _not_ buffering the
packets so that they can be read by a microprocessor.  If that was the
case, I could use a very small (possibly on-chip) buffer.  The large ram
would then be connected to the micro, and not the fpga, but the total size
remains the same.

Thanks,
Allan.
Article: 8167
Subject: barrel shifter
From: Robert Olson <Robert.Olson@CAS.Honeywell.Com>
Date: Sun, 23 Nov 1997 19:28:40 -0800
Links: << >>  << T >>  << A >>
Does anyone have an example of a barrel shifter implemented in VHDL?  I
need to shift from 1 to 14 bits.  Thanks
Article: 8168
Subject: ABEL6 and Xilinx Foundation
From: Rick Filipkewicz <rick@xxxxz.co.uk>
Date: Mon, 24 Nov 1997 17:43:44 +0000
Links: << >>  << T >>  << A >>
Anyone know where I can find a - downloadable, printable - manual for 
ABEL6. This is now part of the Xilinx M1 release of Foundation but
there seems to be no syntax description available beyond the online
help. e.g. the only Xilinx ABEL manual I have doesn't mention 
hierarchy.

_________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 8169
Subject: Re: what is metastability time of a flip_flop
From: Tom Bowns <bowns@data-io.com>
Date: Mon, 24 Nov 1997 17:49:55 GMT
Links: << >>  << T >>  << A >>
lzh@bd748.pku.edu.cn wrote:
> 
> Hi.  Does anybody explain the meaning of  " metastability time of a
> flip_flop", and what would happen if data changed in metastability > > time of a flip_flop?  


Metastability is, in a flip-flop, the state of being "undecided"
followed by the state of being "resolved".

For example, if the D input of a D flip-flop went high well before
the clock edge, the Q output will go high after the time Tco.

But if the D input of a flip-flop went high around the same time as the
clock edge (within Tsetup or Thold), the flip-flop will have trouble
"deciding" whether the D input was first or the clock was first, and may
very well enter the "metastable" state.

Whether the flip-flop will enter the metastable state in the first
place, and how long it takes to resolve out of the metastable state into
a solid HIGH or LOW depends primarily upon the process technology of the
device. The old TTL parts (74LS74, for example) would go metastable a
lot more easily, and could potentially stay in that state for a much
longer time than the newer CMOS technologies, for example.

I had this grand notion that in the future, metastability data would be
included in every registered device data sheet as a standard thing, like
Tco and Tsetup and such. Guess not.

I'm not sure if he's still doing it, but Thomas Chaney has been, to me,
the Metastability-Meister. There's a paper he wrote in IEEE
transactions: "Measured Flip Flop Responses To Marginal Trigerring,"
IEEE transactions on computers, volume C-32, No 12, December 1983. He
told me that at the university (I forget which one - it's been a few
years) they'll do metastability analysis of your system or device for a
nominal fee.

For what it's worth.

-Tom Bowns
Synario Design Automation
Article: 8170
Subject: AT17C256 problems
From: Tobias Hilpert <thilpert@osc.de>
Date: Mon, 24 Nov 1997 23:25:18 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm a student working on a FPGA-based module for image preprocessing on
a framegrabber (module: two XC4013E-2 both serial master configured + 4
synchronous SRAM's 128kx8).

For FPGA configuration I wanted to use ATMEL AT17C256 EEPROMS (for
in-system-programmability the AT17C256 data output and some other pin's
run through a multiplexer 74AC157; I used the circuitry described in the
ATMEL data sheet p.3-29). Unfortunately, the configuration process
doesn't finish correctly !!! I tried to change some pull-up/down
resistors without solving the problem :( . I also substituted the ATMEL
by the original Xilinx PROM and wonder: no config problems occurred (->
there are no circuitry errors).
Some other students are using ATMEL AT17C128 devices for smaller XILINX
FPGA's without any problems.

It would be very helpful, if somebody could give me some advices how to
fix the problem with the ATMEL devices, because I don't want to waste
those XILINX PROM's trying to implement new things into my FPGAs (I
already killed some :)  ).

Thank you in advance,

   Tobias Hilpert
Article: 8171
Subject: Re: What is the difference between CPLD and FPGA ?
From: htimsg@passport.ca (Greg Smith)
Date: Mon, 24 Nov 1997 23:57:03 GMT
Links: << >>  << T >>  << A >>
In article <64vocg$eqg$1@nntp2.ba.best.com>, "John Birkner" <birkner@quicklogic.com> wrote:
>Jean-Paul Ricaud wrote:
>>What is the difference between CPLD and FPGA ?
>
>The simplest definition that I have heard is that,
>  CPLDs are product term based and
>  FPGAs are not product term based.
>
Wow, this is like RISC vs CISC.
Here's another one: FPGAs allow logic basically in proportion to the
area of the die, with CPLD's it's in proportion to the perimeter (with
an exponent maybe a little bigger than 1 for some parts). But the
distinction between 'routing' and 'logic' blurs a little, from wired-and.
Article: 8172
Subject: Re: what is metastability time of a flip_flop
From: htimsg@passport.ca (Greg Smith)
Date: Tue, 25 Nov 1997 00:07:22 GMT
Links: << >>  << T >>  << A >>
In article <652vrc$54c@src-news.pa.dec.com>, murray@pa.dec.com (Hal Murray) wrote:
>In article <3474c626.1321210@news.mv.net>, jeff@wa1hco.mv.com (Jeff Millar)
> writes:
>
>>                                           A few manufacturers make
>> metastable hardened FF that may take longer to settle to high or low
>> but will monotonically transition...thus clocking all down stream
>> devices equally.
>
>Would you trust a design that depended upon that characteristic?
>
Well, if I couldn't avoid it, yes. I remember seeing a '74something9074' or
something which was a metastability-reduced 7474 device. The thing
is, there is a statistical phenomenon happening. Each time an edge
falls in the 'bad' window, you have a possibility of it going metastable
for some length of time; this is a random variable which is related to
the position in the window of the edge.
In practical terms, you want to reduce the probability of it still being
unsettled when you sample it. If the clock is very fast, then these
events may happen very frequently, and the time allowed for settling
may be very short. So, using a part which promises to bring your
probability of screwup down may make a lot of sense. If you simply
*need* to synchronize things at that rate, you can mess around all you
like with extra delays and so forth; at the end of the day, you will need
a device whose analog performance is up to scratch. Alternately, you
can find a way to reduce your syncing rate (widen the data path first,
etc), which is usually preferable; but in some cases you may just need
the speed.

Greg
Article: 8173
Subject: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
From: htimsg@passport.ca (Greg Smith)
Date: Tue, 25 Nov 1997 00:14:46 GMT
Links: << >>  << T >>  << A >>
In article <3470B1C5.2781E494@NOSPAMnortel.ca>, Tim Warland <twarland@NOSPAMnortel.ca> wrote:
>Markus Leberecht wrote:
>> 
>> Hi all!
>> 
>> We are currently planning to do an FPGA design that is loaded with
>> registers to all of which a processer would need read and possibly
>> write access. We therefore came up with the idea of using a
>> reconfigurable device with a memory-like CPU interface (like the
>> XC6200) since it would provide us for free with all the datapaths to
>> access the registers. Using a regular FPGA, it seems that we would
>> just waste too much space for the "little functionality" of accessing
>> the registers. Is this reasoning correct or are there regular (non-
>> reconfigurable, that is) FPGA families that are better suited to this
>> kind of design with maybe a higher density?
>> 
>
This may help - the CX4000 series allows you to put 2x16 bits of RAM in a CLB
This means, for instance, if you want 16 regs of 32 bits each, you can put
them in 16 CLBs - and that includes the multiplexer required to read them. You
can also put them in 32 'dual port' CLBs, which gives you two independent
read ports; a write operation is always done to the address supplied by one
of the read ports. This eliminates the need for a lot of wiring and logic
just to allow reading of regs. Of course, it means you can't load all the
regs in parallel.

Greg
Article: 8174
Subject: Re: barrel shifter
From: Brian Philofsky <brianp@xilinx.com>
Date: Mon, 24 Nov 1997 18:42:34 -0800
Links: << >>  << T >>  << A >>
Robert,

      Here is a 0 to 15 bit barrel shifter from a Xilinx App note.  It was
compiled on Synopsys FPGA Compiler but seems generic enough that it should
work on most any compiler.  Hope it helps you out :



-- BARREL.VHD
-- Based on XAPP 26 (see http://www.xilinx.com)
-- 16-bit barrel shifter (shift right)
-- May 1997

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity barrel is
port (  S:   in STD_LOGIC_VECTOR(3 downto 0);
        A_P: in STD_LOGIC_VECTOR(15 downto 0);
        B_P: out STD_LOGIC_VECTOR(15 downto 0));
end barrel;

architecture RTL of barrel is

signal SEL1,SEL2: STD_LOGIC_VECTOR(1 downto 0);
signal C:         STD_LOGIC_VECTOR(15 downto 0);

begin
    FIRST_LVL: process (A_P, SEL1)
    begin
        case SEL1 is
            when "00" => -- Shift by 0
               C               <= A_P;

            when "01" => -- Shift by 1
               C(15)           <= A_P(0);
               C(14 downto 0)  <= A_P(15 downto 1);

            when "10" => -- Shift by 2
               C(15 downto 14) <= A_P(1 downto 0);
               C(13 downto 0)  <= A_P(15 downto 2);

            when "11" => -- Shift by 3
               C(15 downto 13) <= A_P(2 downto 0);
               C(12 downto 0)  <= A_P(15 downto 3);

            when others =>
               C               <= A_P;
        end case;
    end process; --End FIRST_LVL

SECND_LVL: process (C, SEL2)
    begin
        case SEL2 is
           when "00" => --Shift by 0
               B_P               <=  C;

           when "01" => --Shift by 4
               B_P(15 downto 12) <= C(3 downto 0);
               B_P(11 downto 0)  <= C(15 downto 4);

           when "10" => --Shift by 8
               B_P(7 downto 0)   <= C(15 downto 8);
               B_P(15 downto 8)  <= C(7 downto 0);

           when "11" => --Shift by 12
               B_P(3 downto 0)   <= C(15 downto 12);
               B_P(15 downto 4)  <= C(11 downto 0);

           when others =>
               B_P               <= C;
        end case;
    end process; -- End SECOND_LVL

    SEL1 <= S(1 downto 0);
    SEL2 <= S(3 downto 2);

end RTL;



Robert Olson wrote:

> Does anyone have an example of a barrel shifter implemented in VHDL?  I
> need to shift from 1 to 14 bits.  Thanks



--
-------------------------------------------------------------------
 / 7\'7 Brian Philofsky   (brian.philofsky@xilinx.com)
 \ \ `  Xilinx Applications Engineer             hotline@xilinx.com
 / /    2100 Logic Drive                         1-800-255-7778
 \_\/.\ San Jose, California 95124-3450          1-408-879-5199
-------------------------------------------------------------------





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