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Messages from 6650

Article: 6650
Subject: Re: XC6200 Gate Count
From: Tim Warland <twarland@nortel.ca>
Date: Mon, 09 Jun 1997 15:41:00 -0400
Links: << >>  << T >>  << A >>
Pedro Merino Gonzalez wrote:
> 
> I'm studying Xilinx information about one of their new parts: the
> XC6200. When I saw the architecture, I thought that it was possible to map
> only one gate for each cell (they have only one functional unit and each
> FU is capable of implementing only one gate). If you look at the table
> of characteristics of these FPGAs they say that the XC6216 has 4096
> cells (64x64) but the maximum number of logic gates is 24,000
<snip> 
No one can explain it, the gate counting methodology was developed by
marketing types so you have to realize that they don't understand it
either.

Pedro, you are comparing apples to oranges. When you say "map only one
gate
for each cell" you are thinking about functional gates like nand gates
or
xor gates etc. You are thinking of gates from a user perspective
(certainly
not a marketing perspective). These gates then feed a FF to form a cell.
Cells are the best metric to evaluate FPGAs.  The information of 24000
doesn't even represent the number of physical gates (read transistor
gate
elements), it is a magic number to compare relative sizes by one vendor.

BTW are you aware that the XC6200 family is recommended for co-processor
interface applications?

Cheers
Tim.
-- 
You better be doing something so that in the future
you can look back on "the good old days"

My opinions != Nortel's opinion;  Nortel's Hardware :-)
Article: 6651
Subject: Re: readback on xc40xx ?
From: d.ingram@elec.canterbury.ac.nz (Dave Ingram)
Date: Mon, 09 Jun 97 20:27:01 GMT
Links: << >>  << T >>  << A >>
In article <339B9E48.1FC6@e-technik.uni-rostock.de>,
   Andreas Wassatsch <wa11@e-technik.uni-rostock.de> wrote:
>Hello,
>
>i have a problem with the readback on the xc40xx.
>
>has anyone some information to or expierences with this feature ?

I have used the readback feature on the XC4003A and XC4005E. I have yet to try 
it on my brand-spanking new XC4010E. I used the Xchecker pod (it is probably 
the only option) and did asynchronous debugging. Async was used because I 
didn't want to hack and slash the target board. 

I was still able to extract the information I needed out of my registers 
inside the Xilinx -- it saved at least a week of head scratching by being able 
to do this. If you have the board space for a full Xchecker connection I 
recommend it - at least for developing. Other people here just plug the pod 
into the 8 pin PROM socket, but they have no debugging facilities then.


Dave.
Article: 6652
Subject: Re: XC6200 Gate Count
From: Steve Casselman <sc@vcc.com>
Date: Mon, 9 Jun 1997 20:31:21 GMT
Links: << >>  << T >>  << A >>
Pedro Merino Gonzalez wrote:
> 
> I'm studying Xilinx information about one of their new parts: the
> XC6200. When I saw the architecture, I thought that it was possible to map
> only one gate for each cell (they have only one functional unit and each
> FU is capable of implementing only one gate). If you look at the table
> of characteristics of these FPGAs they say that the XC6216 has 4096
> cells (64x64) but the maximum number of logic gates is 24,000
> 
> Is there anybody able to explain this to me?
Every cell in the XC6200 line can be a two input gate (1 gate)
or a mux (3 gates) - and a register (4 gates). So there are 4K
cells in the XC6216 the highest gate count would be 7 * 4K = 28K.
The lowest gate count would be 4K. Of course there is a utilization
factor depending on your design.

The best figure of how big a part is (IMHO) how many full 
adders feeding registers can you have in a part. If I count
a full adder as 5 gates and a register as 4 gates then a
adder feeding a register is 9 gates. In the 6216 there 4K
cells it takes 3 cells to make a full adder and there are
registers all over so 4K/3 * 9 = 12288 gates. The 4013 has
24x24 cells each of which can have 2 full adders and 2 registers
(18 gates).  24*24*18 gates = 10368 gates. If you look at
the ratios the 6216 is right in there are far as marketing
gates go.
-- 
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


-- 
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com
Article: 6653
Subject: Job-Upstate NY; Senior Engineer; FPGA; Altera
From: richard_steinman@cmagroup.com
Date: 9 Jun 1997 21:14:01 GMT
Links: << >>  << T >>  << A >>

Upstate NY; Senior Engineer; FPGA; Altera;High Speed Digital. 5+ Years 
Exp. Must have: signal processing, algorithms, high speed digital design 
(40-50 MegaHertz), FPGAs, and exposure to imaging &/or sensor systems 
applications. Client using ViewLogic and Spice CAE/CAD tools. 60-70% design/
detailed design; 30-40% systems level work. TO $48-75K

Please refer to JO# 582RJS in your response.



Richard Steinman
Team Leader
rjs@cmagroup.com
IT & Software Solutions Team
Career Marketing Associates
http://www.cmagroup.com/IT.html
Article: 6654
Subject: FS: CADKEY '97 (8.0) -100+ Available- Save $HUNDRED's EACH!!!
From: Karl Kristianson <KarlKristian@ntr.net>
Date: Mon, 09 Jun 1997 15:43:05 -0600
Links: << >>  << T >>  << A >>
FS: CADKEY '97 -100+ Available- Save $HUNDRED's 
EACH!!!

Hello!

A new copy of Cadkey 97 is selling on the street for 
$1,195. To guarantee updates for the next year costs 
$350 more, bringing it up to $1,545 total!

We have available over 100 NEW unopened, 
shrinkwrapped copies of Cadkey 6.0 on CD for DOS 
which can be upgraded to Cadkey 97, INCLUDING the 
year's worth of free updates, for the street price 
of $595; that's $950 LESS than the normal street 
price!

Or, maybe Cadkey 6.0 has enough power for you with 
no upgrade at all! (Cadkey '97 is basically Cadkey 
8.0)

I'm selling these for best offer, one or all.

If you would like more info on Cadkey 97, here's 
Cadkey 97's Web page: 
http://www.cadkey.com/cadkey/index.htm

Thanks!

Karl Kristianson
Article: 6655
Subject: Re: Fine Pitch PQFP : anyone any hassles?
From: Patrick Drolet <pdrolet@galea.com>
Date: Mon, 09 Jun 1997 21:07:52 -0400
Links: << >>  << T >>  << A >>
rhodes@gigaops.com wrote:
> 
> In <3389f515.2357106@news.on.net>, stuart.summerville@practel.com.au (Stuart Summerville) writes:
> >Hi all,
> >
> >I have a 208pin PQFP fpga  (0.5mm pitch) on a board. I am having
> >problems with pin connections to the board. Attempting to re-heat the
> >solder to make a clean connection seems to create problems with
> >surrounding pins - it doesn't take much to get a minute solder bridge
> >between two pins.
> >
> To engineers and technicians concerned with QFP208 soldering problems/techniques
>  -
> 
> QFP208s and QFP240s are soldered by hand by technicians in the South Bay
> (SF bay) by a drag technique which some in this thread have described.

PACE has a great solder tip to solder by hand 0.5mm pitch (20 mils). 
It's called MicroWave.  We've been using it for 208 PQFP packages and 48
pins ssop flash-roms.  Works great.  I'm an enginner (aka: bad
technician) and it takes me about 5 minutes to solder a 208 pqfp.

Patrick
Article: 6656
Subject: Re: What is M1?
From: "John W. Curtis" <jcurtis@metasystematic.com>
Date: 10 Jun 1997 04:16:23 GMT
Links: << >>  << T >>  << A >>
As has been said earlier, M1 is the first fruit of the NeoCad merger with
Xilinx

XNF is still in this first version, but will be dropped from future
versions.

Homegrown tools will have to be converted to EDIF 2.0.0 to work with future
tools.

Simon Bacon <SimonBacon@tile.demon.co.uk> wrote in article
<864483367snz@tile.demon.co.uk>...
> For those of us who are not on the M1 pre-release program - possibly
> because we don't have paid-up software support - what is M1?
> 
> From other posts, it sounds as if XNF is being dropped.  Is that
> correct?
> 
> Will we have to abandon our home-grown tools which manipulate
> and/or generate XNF?
> 
> ---
> Regards
> Simon
> 
> 
Article: 6657
Subject: Re: readback on xc40xx ?
From: Andreas Wassatsch <wa11@e-technik.uni-rostock.de>
Date: Tue, 10 Jun 1997 06:58:14 +0200
Links: << >>  << T >>  << A >>
okay

in a the sample design i have include the macro "rdbk".

=2E..
  CCLK : in std_logic;
  TM0 : in std_logic;
  TM1 : out std_logic;
=2E..
 component RDBK
  port(
   TRIG : in std_logic;
   DATA : out std_logic;
   RIP : out std_logic
   ); end component;
=2E..
  I_RDBACK : RDBK port map ( TRIG =3D> TM0, DATA =3D> TM1 );
=2E..

then i try to connect the the io's to the pins as follow ( synopsys )

set_attribute "CCLK" "pad_location" -type string "P73"
set_attribute "TM0" "pad_location" -type string "P32"
set_attribute "TM1" "pad_location" -type string "P30"

but xnfprep reports :

    XNFPREP Errors
    --------------
    XNFPREP: ERROR 4546: =

      The pad `TM0' has an invalid LOC parameter value `P32'.
      =

      The location `P32' is not a valid I/O pin on the part `4003APC84'.
      =

    XNFPREP: ERROR 4546: =

      The pad `TM1' has an invalid LOC parameter value `P30'.
      =

      The location `P30' is not a valid I/O pin on the part `4003APC84'.
      =


and no connections a build between the readbk-component and the io-pins

i use xact 5.2.1, a 4003A(PLC84) on the xilinx fpga-demoboard
-- =

#  Andreas Wassatsch                           Tel: +49 (0)381 498 3533
#  University Rostock                          Fax: +49 (0)381 498 1126
#  Department of Electrical Engineering
#  Institute of Applied Microelectronics and Computer Science
#  Richard-Wagner-Str. 31
#  18119 Rostock-Warnem=FCnde        email: wa11@e-technik.uni-rostock.de=

#  Germany            WWW: http://www-md.e-technik.uni-rostock.de/~wa11
Article: 6658
Subject: ATMEL 17Cxxx ISP function
From: Stephan Gick <gck@iis.fhg.de>
Date: Tue, 10 Jun 1997 09:34:06 +0200
Links: << >>  << T >>  << A >>
Hi,
has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
17C256 to change the Prom contents on the fly by a microcontroller or
Host CPU?
Any hints or possible problems? Is there a source code available for
downloading a bitstream via PC?
Stephan 

-- 
Dipl. Ing. Stephan Gick  +  FhG IIS
Tel. +49 (0)9131-776521  +  Abteilung ESY-B
Fax: +49 (0)9131-776599  +  Am Weichselgarten 3
EMail: gck@iis.fhg.de    +  D-91058 Erlangen
http://www.iis.fhg.de/departs/esy/index.html
Article: 6659
Subject: Re: ATMEL 17Cxxx ISP function
From: koen Gadeyne <koen.gadeyne@barco.com>
Date: Tue, 10 Jun 1997 13:25:25 +0200
Links: << >>  << T >>  << A >>
Stephan Gick wrote:
> 
> Hi,
> has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
> 17C256 to change the Prom contents on the fly by a microcontroller or
> Host CPU?

I did that a long while ago (when they first came out). It's not too
difficult to do, since it's an IIC protocol. The only thing I had
trouble with, and which wasn't mentionned in the early datasheets, was
that these things are FLASH-based, and hence they need to be programmed
in blocks of 64 (?) bytes. That's where the datasheets stopped. What
they didn't tell was that after writing a block, you have to wait for a
while for the FLASH architecture to "update" the block.

I suspect they use the same architecture as in their generic FLASH
PROMS, which use a RAM "buffer" for an entire sector, which is used as a
sort of cache. Once the cache buffer is full, it is transferred into the
FLASH memory bank in one blast.

But that blast takes a while, and the ATMEL EEPROMs don't respond to any
IIC command until that's done. So you can't even probe some register to
see if they're "ready". You can only tell be the irresponsive IIC
interface.

Oh yeah, if you program them for XILINX, don't reverse the bits as the
datasheet suggests. For Altera, you need to do that. In this case, I
suspect they wanted to avoid paying any license fees to Philips for
using the IIC protocol, so they didn't name it IIC, and they made sure
to make it non-compliant (on paper) by specifying the inverse bit-order
as used by the IIC spec.

Koen.
Article: 6660
Subject: Re: ATMEL 17Cxxx ISP function
From: fink@post.tau.ac.il (Udi Finkelstein)
Date: Tue, 10 Jun 1997 12:13:35 GMT
Links: << >>  << T >>  << A >>
On Tue, 10 Jun 1997 13:25:25 +0200, koen Gadeyne <koen.gadeyne@barco.com>
wrote:

>Stephan Gick wrote:
>> 
>> Hi,
>> has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
>> 17C256 to change the Prom contents on the fly by a microcontroller or
>> Host CPU?
>

I have a board with an AT17C65 booting an Atmel AT6005 FPGA. The onboard
AT17C65 (I use the SOIC version, which is soldered) can be programmed either
through a cable using Atmel's CF.EXE download software, or through my own
software which drives the I2C lines from my PCI interface (the chips are
located on a PCI board).

Udi
Article: 6661
Subject: Re: ATMEL 17Cxxx ISP function
From: glenr@netcom.com (Glen Rosendale)
Date: Tue, 10 Jun 1997 17:33:40 GMT
Links: << >>  << T >>  << A >>
koen Gadeyne (koen.gadeyne@barco.com) wrote:
: Stephan Gick wrote:
: > 
: > Hi,
: > has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
: > 17C256 to change the Prom contents on the fly by a microcontroller or
: > Host CPU?

: I did that a long while ago (when they first came out). It's not too
: difficult to do, since it's an IIC protocol. The only thing I had
: trouble with, and which wasn't mentionned in the early datasheets, was
: that these things are FLASH-based, and hence they need to be programmed
: in blocks of 64 (?) bytes. That's where the datasheets stopped. What
: they didn't tell was that after writing a block, you have to wait for a
: while for the FLASH architecture to "update" the block.

The data sheet specifies that when the "STOP" bit is sent (at the end
of the WRITE instruction/data stream) the device will enter an 
internally timed write cycle, during which it will not ACK any data
requests. It also specifies that this time is 10 ms (worst case).

The data sheet ALSO states that the device can be "polled" during
the write cycle; as soon as it ACK's a device address it can be 
accessed again (typical page write time is about 2 to 3 ms).

: I suspect they use the same architecture as in their generic FLASH
: PROMS, which use a RAM "buffer" for an entire sector, which is used as a
: sort of cache. Once the cache buffer is full, it is transferred into the
: FLASH memory bank in one blast.

Sort of, but not quite.

: But that blast takes a while, and the ATMEL EEPROMs don't respond to any
: IIC command until that's done. So you can't even probe some register to
: see if they're "ready". You can only tell be the irresponsive IIC
: interface.

Not at all; see above. You can easily find out *exactly* when the
device is done. 

: Oh yeah, if you program them for XILINX, don't reverse the bits as the
: datasheet suggests. For Altera, you need to do that. In this case, I
: suspect they wanted to avoid paying any license fees to Philips for
: using the IIC protocol, so they didn't name it IIC, and they made sure
: to make it non-compliant (on paper) by specifying the inverse bit-order
: as used by the IIC spec.

Hmm ... I don't know where this comes from; the data byte ordering is
identical to the Xilinx device requirements.

: Koen.

The Atmel FPGA Configuration memories make it very straightforward to
implement an in-system reprogrammable FPGA data storage solution. The
Atmel WWW page has detailed instructions and examples, and app notes
are available.

Disclaimer:

I designed the chip family and work at the company that sells them.
Obviously that affects my perceptions :)

glen rosendale (glen@atmel.com)
Article: 6662
Subject: Re: ATMEL 17Cxxx ISP function
From: Werner Dreher <dreher@informatik.uni-tuebingen.de>
Date: Tue, 10 Jun 1997 22:07:05 +0200
Links: << >>  << T >>  << A >>
Glen Rosendale wrote:
 
> The data sheet specifies that when the "STOP" bit is sent (at the end
> of the WRITE instruction/data stream) the device will enter an
> internally timed write cycle, during which it will not ACK any data
> requests. It also specifies that this time is 10 ms (worst case).
> 
> The data sheet ALSO states that the device can be "polled" during
> the write cycle; as soon as it ACK's a device address it can be
> accessed again (typical page write time is about 2 to 3 ms).
[...]

During this write cycle, the device dosn't recognize the START bit,
so I have to send a START bit before each device adress byte in this
polling loop, right? When I send only one START bit and then loop
sending the device adress byte and listening for the ACK, I never
get an ACK.

I tried to change the polarity of the RESET/_OE pin to _RESET/OE
("_" indicates active low) of the AT17C128 in the following manner
(as described in the programming specification):

 1. set all pins to 5V (at power up)
   (except pin A2 which has a resistor of 4.7k to ground)
 2. set CLOCK = 0V
 3. set RESET/_OE = 0V
    (if already _RESET/OE then the device is reset now, otherwise
     in state 1)
 4. set _SER_EN = 0V and RESET/_OE = 5V (_CE remains high)
 5. write a START bit
 6. write a device adress byte
 7. write a byte of 3F (MSB first)      \
 8. write a byte of FF (MSB first :-) ) / this gives EEPROM Adress 3FFF
 9. write a byte of FF (one data byte)
10. write a STOP bit
11. wait 1 second (enough?)
12. set _SER_EN = 5V
13. set CLK = 5V
(all pins are driven by a Xilinx FPGA so they are at 5V until
 end of configuration of the FPGA)

but the polarity of pin RESET/_OE doesn't change.
What's wrong?

(I tried both RESET/_OE = 5V and =0V during steps 4 to 12).
The routines generating the START and STOP bit and the adress/data
bytes seem to work right; I have looked at the pins with a
logic analyzer, and I can program the memory array.

Sorry for my english
  Werner

----------------------------------------------------------------
Werner Dreher                 dreher@informatik.uni-tuebingen.de
University of Tuebingen
Technische Informatik / Computer Engineering
Sand 13
D-72076 Tuebingen, Germany
Article: 6663
Subject: SUN AND SGI FOR SALE
From: Brandon Unger <brandon@recurrent.com>
Date: Tue, 10 Jun 1997 15:47:04 -0700
Links: << >>  << T >>  << A >>
For Sale
(2000) Sun Sparc 5/20 disk drive brackets.....	$7
				(qty 100).....	$5ea
Sun Sparc 5 w/ 32Mb,GX,19" color,2gb disk,CD..	$2,950
Sun S10 w/64Mb,GX,19"color,1Gb disk,mod 61....	$2,900
Sun Sparc 2 32Mb,GXplus,19"color,424mb disk ..	$1,100
				(qty 10)......	900ea
Sun IPX w/32Mb,GX,19" color,424Mb disk........	$750	
				(qty 10)......	$600
Sun Sparc 2 base .............................	$300
Sun IPX base .................................	$250
Sun X1016A FDDI/S DAS 3.0 dual attach FDDI....	$1,500
Sun X6254A 4-8Gb 4mm unipack .................	$950
Sun 501-2353 TX4 frame buffer ................	$800
Sun 501-2039 GX plus frame buffer ............	$300
				(qty 10)......	$250
Sun 365-1330 20" color monitor (refurb) ......	$900
Sun 365-1160 19" color monitor ...............	$425
Sun type 5 keyboards .........................	$75
Seagate ST19171N 3.5" 9Gb disk................	$1,400
SGI 20" granite color monitors ...............	$1,200
Sgi Indigo 2 w/96mb,200mhz,XZ+,2Gb, 20" color.	$6,400

6 MONTH WARRANTY

VISA MASTERCARD AMX
--

Brandon Unger	
Recurrent Technologies, Inc.
3270 Keller Street  #114
Santa Clara, CA  95054	
Phone:  408-727-1122			Fax:  408-727-8002
http://www.recurrent.com/		brandon@recurrent.com
Article: 6664
Subject: Re: PCI how to
From: "Austin Franklin" <darkroo4m@ix.netcom.com>
Date: 11 Jun 1997 00:17:19 GMT
Links: << >>  << T >>  << A >>
> |>    I would like to make a simple PCI interface card that would allow
> |> me to do some basic I/O with 'outside world'. I found quite some
> |> information about the ISA interfaces,  but basically nothing usefull
> |> about PCI. I would be very thankfull if someone could tell me how I
> |> should approach this problem (point me to some resources on net, or
> |> literature).
> 
> If you don't want to spend more than half a year in designing/testing
your own
> PCI implementation, try some of-the-shelf chips (maybe there are
more...):

If it takes you 'half a year' to do a target implementation (which is what
they guy mentioned he wanted to do) in an FPGA, you might want to consider
getting outside help.

This should take someone about 3 months if they don't know anything about
the PCI bus, or the FPGA tools etc.  Most of the work isn't in the PCI
target interface, it is in the back end interface.

A master is a different story...that's a bit tougher...

Austin Franklin
darkroom@ix.netcom.com

Article: 6665
Subject: Re: Fine Pitch PQFP : anyone any hassles?
From: "John Solo" <johnsolo@worldnet.att.net>
Date: 11 Jun 1997 03:26:38 GMT
Links: << >>  << T >>  << A >>
Please explain this to me.
For years cameras and military electronics, my print head,
have used flexible epoxy circuits.
Perhaps there is something in this question I don't get,
I haven't USED these products.
One other product I haven't used is a pen for making repairs,
leaves a silver epoxy. Also I have USED special ball point pens 
that are usually used for making on photo's, floppies.
They work like a Paint spray can/ball point pen.
Why isn't there a product like a pen or epoxy that can be
used to repair fine pitched ic's or MAKE them is small QTY.
I am thinking that this can't be too hard to pull off.
Mask Develop Etch Board, Mount Components, Using Superglue.:)
Make final connections with a pen or epoxy or Photocoating, SEE YA BYE.

Stuart Summerville <stuart.summerville@practel.com.au> wrote in article
<3389f515.2357106@news.on.net>...
> Hi all,
> 
> I have a 208pin PQFP fpga  (0.5mm pitch) on a board. I am having
> problems with pin connections to the board. Attempting to re-heat the
> solder to make a clean connection seems to create problems with
> surrounding pins - it doesn't take much to get a minute solder bridge
> between two pins.
> 
> Two questions:
> 
> 1) Do any of you find such packages tend to come in with such
> connection problems?
> 
> 2) What is the feeling about attempting to re-solder such pins if a
> connection seems to be flakey? Am I wasting my time trying to fix it?
> Maybe if some pins have flakey connections then others on the same
> chip are likely to (eg. if some are bent down too much, then obviously
> the others are at a different level...).
> 
> Regards, Stu.
> ---------------------------------------------
> Stuart Summerville      
> Project Engineer         
> Practel International
> 442 Torrens Road, Kilkenny, SA 5009
> Tel: (61.8) 8268 2196  Fax: (61.8) 8268 2882
> Email: stuart.summerville@practel.com.au  
> ---------------------------------------------
> 
Article: 6666
Subject: Re: ATMEL 17Cxxx ISP function
From: Martin Mason <nospam_mtmason@ix.netcom.com>
Date: Tue, 10 Jun 1997 22:30:00 -0700
Links: << >>  << T >>  << A >>
> : Stephan Gick wrote:
> : >
> : > Hi,
> : > has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
> : > 17C256 to change the Prom contents on the fly by a microcontroller or
> : > Host CPU?

For more information check-out....

http://www.atmel.com/atmel/products/fpga/fpga1.html

or e-mail configurator@atmel.com

Martin Mason
Configurator Apps.
Atmel Corp.
Article: 6667
Subject: Re: Fine Pitch PQFP : anyone any hassles?
From: z80@dserve.com (Peter)
Date: Wed, 11 Jun 1997 07:01:48 GMT
Links: << >>  << T >>  << A >>

>Or just slice the pins off very close to the package with a sharp knife,
>then nip round and desolder many pins at a time using a biggish tip and
>a blob of solder. IME, far less likely to kill pads / tracks that way. 

I generally agree, although lately I have come round to the view that
this is dodgy on reall fine pitch packages such as TSOP, because the
PCB pads are so small that if the knife gets pushed in a bit too far,
causing the lead to be displaced away from the package, it tends to
rip the pad off the board.

The best way to remove TSOPs is with a desoldering bit which melts the
whole lot in one go.

But with SOP etc this is the best way. 


Peter.

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Article: 6668
Subject: XC1700 programming algorithm
From: Paul Hatcher <hephat@dial.pipx.com>
Date: Wed, 11 Jun 1997 18:10:50 +1000
Links: << >>  << T >>  << A >>

Does anyone know where I can obtain the programming details (algorithms
hardware etc) for the Xilinx XC1700D SPROM series?

Thanks,

Paul Hatcher
hephat@dial.pipex.com

Article: 6669
Subject: Re: PCI how to
From: "Carlos Stahr" <kramer@ostis.com>
Date: 11 Jun 1997 20:19:53 GMT
Links: << >>  << T >>  << A >>

Try this web site:

          http://www.vchips.com/products.htm

                    
Ivan Hamer <ivan@caseware.com> wrote in article
<3395d321.22329448@news.caseware.com>...
> 
>    I would like to make a simple PCI interface card that would allow
> me to do some basic I/O with 'outside world'. I found quite some
> information about the ISA interfaces,  but basically nothing usefull
> about PCI. I would be very thankfull if someone could tell me how I
> should approach this problem (point me to some resources on net, or
> literature).
> 
>   Ivan Hamer (ivan.hamer@toronto.edu).
> 
Article: 6670
Subject: Re: ATMEL 17Cxxx ISP function
From: "Erwin Oertli" <oertli@inf.ethz.ch>
Date: 12 Jun 1997 07:03:56 GMT
Links: << >>  << T >>  << A >>
I have successfully used the ISP function. I am using three daisy-chained
AT17C256 to program four daisy-chained XC52xx FPGAs. One of the FPGAs
contains a simple state machine to controll the ISP functionallity and to
reboot the system.

The Atmel documentation is complete but not very clear. You can it find at
theirs web cite.

The thing I did not realize at first was: one has to program pages of 64
byte and then wait until programming is done. After realizing that, I found
all the information in the documentation.

Good luck.

-- 
Erwin Oertli                                      Tel:  +41-1-63 27333
Institut für Computersysteme                      Fax:  +41-1-63 21307
ETH Zentrum                                  mailto:oertli@inf.ethz.ch
CH-8092 Zürich, Switzerland         http://www.cs.inf.ethz.ch/~oertli/


Stephan Gick <gck@iis.fhg.de> wrote in article
<339D036E.78BE@iis.fhg.de>...
> Hi,
> has anyone used the ISP function of the serial ATMEL Boot Proms 17C65,
> 17C256 to change the Prom contents on the fly by a microcontroller or
> Host CPU?
> Any hints or possible problems? Is there a source code available for
> downloading a bitstream via PC?
> Stephan 
> 
> -- 
> Dipl. Ing. Stephan Gick  +  FhG IIS
> Tel. +49 (0)9131-776521  +  Abteilung ESY-B
> Fax: +49 (0)9131-776599  +  Am Weichselgarten 3
> EMail: gck@iis.fhg.de    +  D-91058 Erlangen
> http://www.iis.fhg.de/departs/esy/index.html
> 
Article: 6671
Subject: Re: XC1700 programming algorithm
From: "Steven K. Knapp" <sknapp @ optimagic.com>
Date: 12 Jun 1997 19:49:07 GMT
Links: << >>  << T >>  << A >>
I believe that you can only get it from Xilinx.  I'd try sending a message
to 'hotline@xilinx.com' with your request.
-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  sknapp @ optimagic.com
Programmable Logic Jump Station:  http://www.optimagic.com

Paul Hatcher <hephat@dial.pipx.com> wrote in article
<339E5D8A.4893816A@dial.pipx.com>...
| 
| Does anyone know where I can obtain the programming details (algorithms
| hardware etc) for the Xilinx XC1700D SPROM series?
| 
| Thanks,
| 
| Paul Hatcher
| hephat@dial.pipex.com
| 
| 
Article: 6672
Subject: FPGA Opportunities
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Thu, 12 Jun 1997 14:25:49 -0700
Links: << >>  << T >>  << A >>
Title: Digital Hardware Designer
Location: Redmond, WA or Austin, TX

Duties:  Member of a high performance team designing state-of-the-art
emulation hardware to support X86 architecture.

Requirements: 3 years experience doing embedded microprocessor-based
digital design.  Knowledge of the X86, 16, and 32 bit architectures is a
real plus.  Knowledge of Assembly and C.  Experience in designing with
various forms of programmable logic PAL's, GAL's, FPGA, etc.
Understanding of microprocessor emulation and the operation of emulators.
--

-- 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.
Article: 6673
Subject: FPGA Opportunities
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Thu, 12 Jun 1997 14:27:40 -0700
Links: << >>  << T >>  << A >>
Title: Digital Hardware Designer
Location: Redmond, WA or Austin, TX

Duties:  Member of a high performance team designing state-of-the-art
emulation hardware to support X86 architecture.

Requirements: 3 years experience doing embedded microprocessor-based
digital design.  Knowledge of the X86, 16, and 32 bit architectures is a
real plus.  Knowledge of Assembly and C.  Experience in designing with
various forms of programmable logic PAL's, GAL's, FPGA, etc.
Understanding of microprocessor emulation and the operation of emulators.
--

-- 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.
Article: 6674
Subject: Test/Development Engineer, FPGA
From: "Robin M. Morneault" <rmorno@eden.com>
Date: Thu, 12 Jun 1997 14:31:15 -0700
Links: << >>  << T >>  << A >>
Title: Test/Development Engineer
Location: Redmond, WA 

Duties:  Design and develop manufacturing tests for new variants of a 
high
-profile product line of software analysis tools.  Development of the 
tests
will require the individual to gain detailed knowledge of the latest
microprocessors on the market and write applications which run on them.
Participate in the development of the hardware for new product variants
by assessing testability.

Requirements: Must have a BSEE/CS and 3+ years experience in hardware
test/design, including expertise in embedded C/C++ programming.  
Experience in developing manufacturing tests, and a familiarity with
FPGA's, hardware simulation packages, and embedded real-time operation
systems is desirable.  
 
Robin Morneault
Professional Recruiter 
Career Consultants Staffing Services
512-346-6660 voice
512-346-6714 fax
headhunter@eden.com
Career Consultants Staffing Services, Inc. has been professionally 
staffing for 25 years as a full service staffing firm that provides 
executive search, direct hire, contract, technical and temporary 
services.


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