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Messages from 8200

Article: 8200
Subject: Re: I need Help
From: "Ahmed H. Hussien" <sega@ritsec1.com.eg>
Date: Thu, 27 Nov 1997 00:02:41 +0200
Links: << >>  << T >>  << A >>
Yes me too please.


Reda Roushdy El-Masry wrote in message <346F601B.CF18C1E3@usa.net>...
>I have to write a paper about FPGA and I know nothing about it
>Please help
>send sites
>papers
>anything
>
>
>



Article: 8201
Subject: Re: what is metastability time of a flip_flop
From: marc@aargh.mayn.de (Marc Heuler)
Date: Wed, 26 Nov 1997 17:21:04 CET
Links: << >>  << T >>  << A >>
In article <3479BE43.5D67@data-io.com>, Tom Bowns writes:

> Whether the flip-flop will enter the metastable state in the first
> place, and how long it takes to resolve out of the metastable state into
> a solid HIGH or LOW depends primarily upon the process technology of the
> device.

Hm, when the flipflop is metastable, can it be recovered by another clock
pulse with valid setup/hold?  Or is it on its bad trip for an uncertain
amount of time not accepting any new input?
Article: 8202
Subject: AHDL vs. VHDL
From: konschak@fb.sony.de (T. Konschak)
Date: Thu, 27 Nov 1997 11:40:05 GMT
Links: << >>  << T >>  << A >>
Hi all,

where is the main difference between AHDL and VHDL?

Is there any difference between these two concerning implementation effort and 
speed of the design. As I understand it VHDL is the more general, versatile of 
the two, but are there any other advantages/disadvantages?


Thanks 

Tino

Article: 8203
Subject: Re: FPGAs for hobbyist, HELP
From: Tony Clark <tony@gw.ballist.net.au>
Date: Thu, 27 Nov 1997 20:34:33 +0800
Links: << >>  << T >>  << A >>

--------------D15BDD76FA6A5EDF8AA2A3E9
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Content-Transfer-Encoding: 7bit

Xlinix have a cheap starter pack on offer at present.  A$150.  Cypress
also use to offer their Warp2
package for just over a $100.  Its VHDL entry so you can play with that
also.  Motorola where offering a cut down version which supported a
couple of devices for free at one stage, don't know about now though.

If your a good talker you can quite often get evaluation software for a
months trial  :)

tony

>  Which manufacture of PGAs would make it possible for the hobbyist to
> use this technology. Obviously the manufactures are mainly interested
> in the big customers and so charge big bucks for their development
> products. So far I've investigated  Lattice, Altera & Xilinx and they
> all have unrealistic prices for their design software. The cost of the
> chips are relativly small ($10-$20 each). The cheapest design package
> was around ($850 Australian). Maybe I haven't looked around enough,
> but if anyone has managed to use re-programable PGAs for a home
> project, then please direct me to a source.
>
> I am interested in  devices capable of In System Programable and In
> System Configerable. This has led me to the following products
>
>                                             erase/program cycles
>   Lattice:     ispLSI1000  series                1000
>    Altera:     FLEX6000  series                infinite
>    Altera:     MAX7000  series                   100
>    Xilinx:     XC3000 series                   infinite
>   Philips:     PZ5000  series                    1000
>
>
>
> Adam



--------------D15BDD76FA6A5EDF8AA2A3E9
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<HTML>
Xlinix have a cheap starter pack on offer at present.&nbsp; A$150.&nbsp;
Cypress also use to offer their Warp2
<BR>package for just over a $100.&nbsp; Its VHDL entry so you can play
with that also.&nbsp; Motorola where offering a cut down version which
supported a couple of devices for free at one stage, don't know about now
though.

<P>If your a good talker you can quite often get evaluation software for
a months trial&nbsp; :)

<P>tony
<BLOCKQUOTE TYPE=CITE>&nbsp;<TT>Which manufacture of PGAs would make it
possible for the hobbyist to use this technology. Obviously the manufactures
are mainly interested in the big customers and so charge big bucks for
their development products. So far I've investigated&nbsp; Lattice, Altera
&amp; Xilinx and they all have unrealistic prices for their design software.
The cost of the chips are relativly small ($10-$20 each). The cheapest
design package was around ($850 Australian). Maybe I haven't looked around
enough, but if anyone has managed to use re-programable PGAs for a home
project, then please direct me to a source.</TT>

<P><TT>I am interested in&nbsp; devices capable of In System Programable
and In System Configerable. This has led me to the following products</TT>

<P><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
erase/program cycles</TT>
<BR><TT>&nbsp; Lattice:&nbsp;&nbsp;&nbsp;&nbsp; ispLSI1000&nbsp; series&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
1000</TT>
<BR><TT>&nbsp;&nbsp; Altera:&nbsp;&nbsp;&nbsp;&nbsp; FLEX6000&nbsp; series&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
infinite</TT>
<BR><TT>&nbsp;&nbsp; Altera:&nbsp;&nbsp;&nbsp;&nbsp; MAX7000&nbsp; series&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
100</TT>
<BR><TT>&nbsp;&nbsp; Xilinx:&nbsp;&nbsp;&nbsp;&nbsp; XC3000 series&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
infinite</TT>
<BR><TT>&nbsp; Philips:&nbsp;&nbsp;&nbsp;&nbsp; PZ5000&nbsp; series&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
1000</TT>
<BR>&nbsp;
<BR>&nbsp;

<P><TT>Adam</TT></BLOCKQUOTE>
&nbsp;</HTML>

--------------D15BDD76FA6A5EDF8AA2A3E9--

Article: 8204
Subject: VHDL/Verilog Trainers Required by Esperan in US and/or UK
From: Simon Moreton <simon@esperan.com>
Date: Thu, 27 Nov 1997 15:39:14 +0000
Links: << >>  << T >>  << A >>
VHDL/Verilog Trainers Required by Esperan in US and/or UK
=========================================================


Esperan specialize in supplying independent, application orientated VHDL 
and Verilog based training and have very close relationships with most 
of the main EDA and FPGA vendors such as Synopsys, Mentor, Viewlogic and 
Xilinx, our courses are recommended or re-sold by many of them.

Due to our rapid expansion in the provision of VHDL and Verilog training 
services in the US and Europe.  We are actively seeking to recruit 
consultants as trainers to out source the delivery of the training 
courses to, on a week by week basis.

In addition to the obvious financial benefits our experience with other 
consultants has shown that delivering the training courses provides an 
excellent opportunity for the consultant to market their own, and their 
organizations expertise to potential customers. 

Primarily we are looking for Designers/Consultants who have:

* Real world experience of VHDL and/or Verilog based design using 
synthesis.
Use of FPGAs would be a distinct advantage.

* Good communication skills and the ability to explain complex topics in 
a
clear, concise manner.

* Availability for periods of up to one week for between four and ten 
weeks
per year.

* A willingness to travel.

We own and develop all the training material, but subcontract the 
delivery to third party consultants.

All the logistics of the courses, such as marketing, software licenses, 
training materials, presentation materials etc. are taken care of by 
Esperan.

If you are interested in this opportunity then please contact me by 
phone,
email or fax.

==============================
Simon Moreton
Esperan
Phone: (800) 947 6116
Fax:   (800) 766 3895
Email: simon@esperan.com
WWW:   http://www.esperan.com
==============================

=======================================================
EUROPE:                        US:
Esperan Ltd                    Esperan
Unit 1, Hilldrop Lane          Permit No. 2105
Ramsbury, Wilts SN8 2RB        Dept. AA25, PO Box 618001
England.                       Dallas  TX 75261-8001
Phone:  +44 1672 520101        (800) 947-6116
Fax:    +44 1672 521039        (800) 766-3895
WWW: http://www.esperan.com/
Article: 8205
Subject: Re: barrel shifter
From: drgtec@aol.com (Drgtec)
Date: 27 Nov 1997 17:34:47 GMT
Links: << >>  << T >>  << A >>
 I hope this will help.
The Sel signal tell how often A  is shifted.
!!! Not all synthesis tool support the exit statement !!!
Gregor


=== SOURCE ==================
library IEEE;
use     IEEE.std_logic_1164.all;
use     IEEE.std_logic_unsigned.all;
--use     IEEE.std_logic_arith.all;

entity BARREL_SHIFTER_N_1 is
    port (
	   Sel : in  Std_logic_vector (3  downto 0);
	   A   : in  Std_logic_vector (15 downto 0);
	   B   : out Std_logic_vector (15 downto 0)
	  );
end BARREL_SHIFTER_N_1;

architecture RTL of BARREL_SHIFTER_N_1 is
begin
process (Sel, A)
    variable Tmp : Std_logic_vector (A'RANGE);
begin

    Tmp := A;
    L1: for J in A'REVERSE_RANGE loop
	if conv_integer(SEL) = 0 then  -- synopysy
	--if to_integer(SEL) = 0 then      -- cds
	    B(J) <= Tmp(J); 
	else
	    Tmp := Tmp(Tmp'RIGHT) & Tmp(Tmp'LEFT downto Tmp'RIGHT+1);
	    B <= Tmp;
	    if conv_integer(Sel) = J+1 then
	    --if to_integer(Sel) = J+1 then
		exit L1;
	    end if;
	end if;
    end loop;

end process;
end RTL;

Article: 8206
Subject: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Thu, 27 Nov 1997 11:16:22 -0800
Links: << >>  << T >>  << A >>
John Cooley wrote:
> 
> I knew I wasn't going to make friends by doing this competition; but, then
> again, I wasn't looking for friends -- I was looking for hard data......
.....
> What I tried very hard to do was to suppress my personal
> views and let the contest and subsequent user response settle this issue.

John,
at the risk of being accused of filibustering, I have to say that you 
haven't addressed my real point.  I completely agree that gathering
objective data is *always* a good thing to do, and I certainly did not
mean to suggest any kind of unfairness in your competition. I wish I had 
the courage and inventiveness to stick my neck on the block like that.

The "friends" I mentioned are not the existing EDA tool suppliers.  
The folk whose support we need are the software scientists who have for
decades been grappling with the problem of how to build large pieces
of software reliably; we hardware people are only just starting on
that road.

I think you proved beyond reasonable doubt something that many of us 
already suspected: Verilog beats VHDL by a couple of lengths if you are
measuring designer productivity on small, timing-critical designs.  The
open
question (much harder to answer, I fear) is this:  on a big project
where
design re-use, integration of many designers' work, and ease of
maintenance
are the important criteria, does VHDL deliver the advantages it was
designed
to provide?

I promise I won't whinge on about this any more!
============================================================================
Jonathan Bromley
Article: 8207
Subject: Free C hardware synthesizer (still available ???)
From: Erik de Castro Lopo <erikd@zip.com.au>
Date: Fri, 28 Nov 1997 20:08:52 +1100
Links: << >>  << T >>  << A >>
Hi all,

I found the following on Deja News. Does anybody know if this 
this still exists? I couldn't find it on the listed server; 
has anybody got a copy?

> 
> Subject:      Free C hardware synthesizer available
> From:         Christian.Iseli@di.epfl.ch (Christian Iseli)
> Date:         1995/12/02
> Message-ID:   <xrpzqdbpm0x.fsf@lslsun7>
> Newsgroups:   comp.arch.fpga,comp.arch,comp.lsi.cad
> [More Headers]
> 
> 
> Hi folks,
> 
> As a part of a larger project, I have developed a C++ to netlist
> compiler. The main goal is to be able to emulate the generated
> hardware by compiling the source code with a regular C++ compiler.
> The targeted hardware is mainly FPGA chips.
> 
> I actually compiled code all the way into Xilinx chips. And they
> run. I think this compiler might be of some interest to other
> researchers, so I decided to make it freely available under a GPL type
> of licensing.
> 
> At the current time, the compiler:
>   - is written in C++. Can be compiled by g++ 2.7.2
>   - needs the LEDA 3.3 library (available by anonymous ftp).
>   - will directly generate ViewLogic WIR files and the associated
>     symbols. It should be easy to add some code to have it generate
>     netlists of different format.
> 
> The target (FPGA) architecture is described directly in the source
> code, preferably in an included file. Thus it should be extremely easy
> to generate netlists for different FPGA architectures. A partial
> description of the XC4000 and XC6200 families is provided in the sources.
> 
> This is still beta quality code. The documentation is very sparse.
> 
> How to get it:
>   ftp://lslsun5.epfl.ch/pub/nlc-0.9.tar.gz
> then look at the README file for terse explanations on how to build...
> 
> I'll also put a compiled binary version for sparc, Solaris 2.4 (sorry,
> this is all I have access to...), file nlc-0.9.bin.gz
> 
> There is a Majordomo mailing list for discussion about nlc. To be
> added to the list, send a message containing the line
> subscribe nlc
> to majordomo@lslsun.epfl.ch. The subject is irrelevant.
> 
> If some folk manage to compile nlc for some other platform, they can upload
> the binary on lslsun5 and tell the list...
> 
> I'm in the process of writing my PhD thesis at the moment... There is a
> chapter on this compiler. I'll make it available as well in the file
> nlc-chapter.ps.gz on the same server.
> 
> Take care,
>                                         Christian Iseli
> -- 
> 
>                                         Christian Iseli
>                                         LSL-DI-EPFL
>                                         Lausanne, Switzerland

-- 
+--------------------------------------------------------------+
	Erik de Castro Lopo   
	home : erikd @ zip.com.au
	work : e.de.castro @ fairlightesp.com.au
+--------------------------------------------------------------+
	
Unsolicited Broadcast Email is Forced Pay-per-view Advertising.
Article: 8208
Subject: Re: Xilinx tech support
From: "Willy" <willy@asic.co.za>
Date: 28 Nov 1997 12:43:14 GMT
Links: << >>  << T >>  << A >>
Yeah, Xilinx need allot of support....

Willem

E.M. Shattock <ems@see.sig> wrote in article <347B59ED.C63@see.sig>...
> I posted a message here last week about a router crash
> I was having when running Xilinx's M1. Within a couple of days
> two people from Xilinx got in touch, and asked for my sources.
> After another couple of days I was told that they'd found the
> bug, and were going to do a patch for M1.3 so that I could route
> the design. I got the patch on Monday morning (I think they
> must have worked through the weekend), and it fixed my problem.
> 
> Amazed? I was...
> 
> Evan
>  
> ----------------------------------------------------------------
> -- E.M. Shattock                                              --
> -- Riverside Machines Ltd.                                    --
> -- 19 De Freville Ave.     tel:   (+44) 1223 566083           --
> -- Cambridge CB4 1HW       fax:   (+44) 1223 566983           --
> -- UK                      mailto:ems@riverside-machines.com  -- 
> ----------------------------------------------------------------
> 
> 
Article: 8209
Subject: Re: Free C hardware synthesizer (still available ???)
From: Charles Sweeney <CharlesSweeney@compuserve.com>
Date: Fri, 28 Nov 1997 16:08:50 +0000
Links: << >>  << T >>  << A >>
I don't have any info on this compiler but if you're generally interested in high
level programming of FPGAs take a look at Handel-C at
<http://www.embedded-solutions.ltd.uk/>. There will be a free demo version
available soon downloadable from this site.

Regards,
Charles

Erik de Castro Lopo wrote:

> Hi all,
>
> I found the following on Deja News. Does anybody know if this
> this still exists? I couldn't find it on the listed server;
> has anybody got a copy?
>
> >
> > Subject:      Free C hardware synthesizer available
> > From:         Christian.Iseli@di.epfl.ch (Christian Iseli)
> > Date:         1995/12/02
> > Message-ID:   <xrpzqdbpm0x.fsf@lslsun7>
> > Newsgroups:   comp.arch.fpga,comp.arch,comp.lsi.cad
> > [More Headers]
> >
> >
> > Hi folks,
> >
> > As a part of a larger project, I have developed a C++ to netlist
> > compiler. The main goal is to be able to emulate the generated
> > hardware by compiling the source code with a regular C++ compiler.
> > The targeted hardware is mainly FPGA chips.
> >
> > I actually compiled code all the way into Xilinx chips. And they
> > run. I think this compiler might be of some interest to other
> > researchers, so I decided to make it freely available under a GPL type
> > of licensing.
> >
> > At the current time, the compiler:
> >   - is written in C++. Can be compiled by g++ 2.7.2
> >   - needs the LEDA 3.3 library (available by anonymous ftp).
> >   - will directly generate ViewLogic WIR files and the associated
> >     symbols. It should be easy to add some code to have it generate
> >     netlists of different format.
> >
> > The target (FPGA) architecture is described directly in the source
> > code, preferably in an included file. Thus it should be extremely easy
> > to generate netlists for different FPGA architectures. A partial
> > description of the XC4000 and XC6200 families is provided in the sources.
> >
> > This is still beta quality code. The documentation is very sparse.
> >
> > How to get it:
> >   ftp://lslsun5.epfl.ch/pub/nlc-0.9.tar.gz
> > then look at the README file for terse explanations on how to build...
> >
> > I'll also put a compiled binary version for sparc, Solaris 2.4 (sorry,
> > this is all I have access to...), file nlc-0.9.bin.gz
> >
> > There is a Majordomo mailing list for discussion about nlc. To be
> > added to the list, send a message containing the line
> > subscribe nlc
> > to majordomo@lslsun.epfl.ch. The subject is irrelevant.
> >
> > If some folk manage to compile nlc for some other platform, they can upload
> > the binary on lslsun5 and tell the list...
> >
> > I'm in the process of writing my PhD thesis at the moment... There is a
> > chapter on this compiler. I'll make it available as well in the file
> > nlc-chapter.ps.gz on the same server.
> >
> > Take care,
> >                                         Christian Iseli
> > --
> >
> >                                         Christian Iseli
> >                                         LSL-DI-EPFL
> >                                         Lausanne, Switzerland
>
> --
> +--------------------------------------------------------------+
>         Erik de Castro Lopo
>         home : erikd @ zip.com.au
>         work : e.de.castro @ fairlightesp.com.au
> +--------------------------------------------------------------+
>
> Unsolicited Broadcast Email is Forced Pay-per-view Advertising.



--


Charles Sweeney, Engineering Director, Embedded Solutions Ltd
Tel/fax +44 1235 510456   <http://www.embedded-solutions.ltd.uk/>
Email CharlesSweeney@compuserve.com or csweeney@embedded-solutions.ltd.uk
6 Main Road, East Hagbourne, Didcot, Oxfordshire. OX11 9LJ. UK.


Article: 8210
Subject: Re: Gigaops Reconfiguration board
From: Terry Graessle <graessle@vlsiDOTgsfc.nasa.gov>
Date: Fri, 28 Nov 1997 12:49:35 -0500
Links: << >>  << T >>  << A >>
Ken,
  You need to specify the HBUS interface in your FPGA design.  You can
either write your own HBUS interface in VHDL or you can use the HLIB
stuff provided by Giga Ops.  
  If you use the Giga Ops provided files you need to instaniate the HBUS
interface .xnf files as black box components in your VHDL code. One
drawback of using the Giga Ops files is that you will be unable to
simulate the HBUS interface portion of your design.  

Ken Chung wrote:
> <snip>
>         But, after I executed it, it seems that the communication has
> something wrong. I guess that I can't send the inputs to the FPGA.
> So, anything wrong? Should I need to explicitly define the HBUS protocol?
> 
> Ken

-- 
Terry L. Graessle         
Lockheed Martin - Space Mission Systems
NASA Code 521/ Microelectronics Systems Branch
graessle@vlsiDOTgsfc.nasa.gov                 (301) 286-9698
Article: 8211
Subject: Xilinx P&R - how does M1 compare to XACT6?
From: z80@ds.com (Peter)
Date: Fri, 28 Nov 1997 19:04:20 GMT
Links: << >>  << T >>  << A >>
Hello,

I have the hugely expensive and dongled XACT6, but I have received the
M1 update a few weeks ago, plus another one just now.

M1 is not dongled, and can be moved to another machine by editing the
volume serial number. This is a major step forward in preserving one's
tools for future maintenance of old projects.

But I wonder how good, and how bug-free, M1 is compared to XACT6. I
use only 3k and 4k devices as these are the cheapest for 100+ volumes.

I have to say I had no problems with the old APR, until I tried to fit
a dense design into a 3090, and APR could not manage anything better
than about 60% utilisation. That was why I got XACT6 - $3500!

I use an old DOS Viewlogic 4 front end for circuit drawing and
simulation (XNF output), and CUPL -> PDS2XNF -> XNF for state
machines.

Any feedback much appreciated.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8212
Subject: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
From: ram <rmcbain@dynavision.com>
Date: Sat, 29 Nov 1997 04:57:35 GMT
Links: << >>  << T >>  << A >>
< snip> 

> The "friends" I mentioned are not the existing EDA tool suppliers.
> The folk whose support we need are the software scientists who have for
> decades been grappling with the problem of how to build large pieces
> of software reliably; we hardware people are only just starting on
> that road.

<snip>

Your looking for guidance from software engineers makes me nervous :)

Certainly, there's some merging of methodologies that makes sense, but
let's make sure it's driven by hardware people who understand "big"
software. In my experience, few software (computing science) people can
learn or understand hardware (enough to be really useful to a hardware
type, anyways).  I've had too many bad experiences...

On the software side, I see them still not having a concept on how to
use pictures to describe a design.  It's only in the last year or so
that state machines became popular there; and they still haven't figured
out how to link a high level data flow or object model diagram to the
actual compilable software (at least not in any widely successful
way).... which is something we've been doing in hardware for years.

My vote (of course) is for more pictures to describe the high level
design. Pictures that are actualy COMPILABLE. People work best with
pictures; we have a huge portion of our brain allocated for them. And I
guess that's why they're way more understandable - just compare the VHDL
code for a complicated state machine vs. a state diagram (which you can
compile into VHDL or Verilog or ABEL). With the VHDL, you end up trying
to create the picture in your head.

What I see in the software world is yet another language (Java). Such
tunnel vision in linguistics doesn't help anybody. Yes, we want reusable
objects (and if they'd started out emulating hardware "parts" a long
time ago, this wouldn't be such an innovative concept). But what we're
talking about is complexity. And listening to somebody telling you about
some complicated object (in words) is nowhere near as good as giving you
a combination of pictures AND words, where the pictures are forced
(through compilation) to be accurate (seen any accurate software
pictures lately?).

Regards,
Rick McBain
Senior (Hardware and Software) Engineer
Dynamic Control Systems

Excuse my ranting and raving. It's genetic.
Article: 8213
Subject: Re: AHDL vs. VHDL
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Sat, 29 Nov 1997 10:24:41 GMT
Links: << >>  << T >>  << A >>
On Thu, 27 Nov 1997 11:40:05 GMT, konschak@fb.sony.de (T. Konschak)
wrote:

>where is the main difference between AHDL and VHDL?

VHDL will not tie you in to a proprietary vendor. It will give you
portability for when your locked in vendor can't provide the features
that a particular project requires.

With sensible, modular use, VHDL will enable you to write re-usable
modules that do not rely on any particular architecture. Of course
there are caveats, but on the whole, code using instantiated
hardware-specific blocks is limited to RAM implementations and
possibly some occasions where you try to extract the maximum possible
from an architecture.

Stuart
--
For Email remove "die.spammer." from the address
Article: 8214
Subject: Re: AHDL vs. VHDL
From: Geir Frode Raanes <geirfrs@VOID.ed.ntnu.no>
Date: 29 Nov 1997 11:05:30 GMT
Links: << >>  << T >>  << A >>
T. Konschak <konschak@fb.sony.de> wrote:
: Hi all,

: where is the main difference between AHDL and VHDL?

It is my impression that AHDL has a higher degree of abstraction
over VHDL.  I do programm in AHDL and has as yet not taken the time
to fully learn VHDL.  But I have learned the hard way that if you 
actually _use_ any of the high level features in AHDL, you will see
LCs start flying past you in an ever increasing rate...

: Tino


GeirFRS@invalid.and.so.forth...



Article: 8215
Subject: Re: FPGAs for hobbyist, HELP
From: z80@ds.com (Peter)
Date: Sat, 29 Nov 1997 12:06:58 GMT
Links: << >>  << T >>  << A >>
Actually it is amazing how much one can get inside a 22V10 :)

I have just spent 2 days doing a really slick state machine. I was
going to use a XC3020 (or similar), to avoid a 22V10 with (what looked
like) a few external chips. Eventually I was able to integrate the
whole lot inside the 22V10, using CUPL's state machine processor.

The saving? About 3x on parts cost. Speed? Can't even compare. Horses
for courses, I suppose.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8216
Subject: VIUF Fall 1998 Call for Topics - Last Chance
From: Peter Ashenden <petera@ececs.uc.edu>
Date: Sat, 29 Nov 1997 12:37:55 -0500
Links: << >>  << T >>  << A >>
LAST CHANCE!  Deadline is Monday, 1 December.

                                ----

                VIUF International Users' Forum (VIUF)
                              Fall 1998

                           CALL FOR TOPICS

                 "Idea Factory: VHDL for Power Users"


Over the past ten years, the EDA Industry has seen VHDL and some of
its satellite standards evolve from infancy to maturity.  The VHDL
International Users' Forum (VIUF) has contributed significantly toward
the introduction of VHDL and its companion standards to the user
community.  However, feedback from users has indicated that VIUF must
do more to address the needs of the "experienced" user.  In light of
this, the Steering Committee for VIUF Fall 1998 has chosen to devote
the majority of its focus to the needs of experienced users and the
practical, real-world applications of VHDL.  (Of course, we promise
not to forget the novice user in our plans, so don't worry if you're
just getting started using VHDL.)

The format of the Fall Forum is also changing, i.e., in addition to
providing a forum for instruction and presentation of the latest
information available concerning the practical application of VHDL,
the Steering Committee is working on a format for VIUF Fall 1998 that
will promote information interchange among the attendees.  We also
hope to offer you more, in a tangible sense, than just a copy fo the
"Proceedings" to take home with you.  However, in order to better meet
your needs, we need your help.  In short, we need to know which topics
related to VHDL and its companion standards are of the greatest
interest to you.

The VIUF Fall 1998 Steering Committee invites you to submit one or
more topics that are of interest to you and/or your colleagues.
Please send your suggestions to the Program Chair, Peter Ashenden, via
electronic mail to:

        petera@ececs.uc.edu

or by regular mail to:

        Peter Ashenden
        Dept ECECS, PO Box 210030
        University of Cincinnati
        Cincinnati, OH 45221-0030
        USA

        Phone: (513) 556 4756
        Fax:   (513) 556 7326

Submit your suggestions by no later than December 1, 1997.

Subsequent to receiving your suggestions, the official "Call for
Participation" will be distributed later this year.  This is your
forum, so please assist us in serving you better by offering your
suggestions.  Thanks in advance for your help.
Article: 8217
Subject: Altera vs Xilinx
From: Umesh Nair <nair@ee.tamu.edu>
Date: Sat, 29 Nov 1997 14:39:09 -0600
Links: << >>  << T >>  << A >>

I would like to have your opinions on whether Altera's MaxplusII or the
Xilinx product -which is superior in what way? 
I have used Altera's tool but not the one from Xilinx- one flaw I find is
that to use the Synopsis compiler for Verilog files; I need to have an
UNIX environment. I would like to have a comparison of these tools with
reference to following features:

1. Programming PLD chips
2. Usability w.r.t Windows environment.
3. Usage of VHDL, Verilog,AHDL(Altera HDL)etc.
4. Timing analysis, Pin layouts, etc.

thanks
Umesh


Article: 8218
Subject: Re: FPGAs for hobbyist, HELP
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 29 Nov 1997 13:22:19 -0800
Links: << >>  << T >>  << A >>
The cost of various FPGA packages has always been a limiter for the
hobbyist.  Luckily, a number of vendors now provide either free or low-cost
(i.e. < US500) versions of their development software via the web.  We
maintain a fairly up-to-date listing at
http://www.optimagic.com/lowcost.html.  All the vendors that you mentioned
are listed.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Adam Seychell wrote in message <347AFD03.2EE5D57@cybec.com.au>...
    Which manufacture of PGAs would make it possible for the hobbyist to use
this technology. Obviously the manufactures are mainly interested in the big
customers and so charge big bucks for their development products. So far
I've investigated  Lattice, Altera & Xilinx and they all have unrealistic
prices for their design software. The cost of the chips are relativly small
($10-$20 each). The cheapest design package was around ($850 Australian).
Maybe I haven't looked around enough, but if anyone has managed to use
re-programable PGAs for a home project, then please direct me to a source.
    I am interested in  devices capable of In System Programable and In
System Configerable. This has led me to the following products

                                                erase/program cycles
      Lattice:     ispLSI1000  series                1000
       Altera:     FLEX6000  series                infinite
       Altera:     MAX7000  series                   100
       Xilinx:     XC3000 series                   infinite
      Philips:     PZ5000  series                    1000



    Adam



Article: 8219
Subject: Re: need help on FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 29 Nov 1997 13:26:46 -0800
Links: << >>  << T >>  << A >>
You may find some useful information on The Programmable Logic Jump
Station at http://www.optimagic.com .  It's a fairly comprehensive set of
links to other relative sites.  Some of the more basic information is under
development on the Frequently-Asked Questions page
(http://www.optimagic.com/faq.html).

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Ahmed H. Hussien wrote in message ...
>I am doing a research on FPGAs but I don't know anything about them. Can
>anyone help me please.
>Please reply to my mailing address directly.
>Regards,
>    Ahmed Hassan
>    a.h.hussien@ieee.org
>
>
>
>


Article: 8220
Subject: Re: FPGAs for hobbyist, HELP
From: Richard Schwarz <aps@associatedpro.com>
Date: Sat, 29 Nov 1997 19:56:45 -0500
Links: << >>  << T >>  << A >>
Adam,

APS currently is selling a complete XILINX kit for $350.00 which allows
you to program FPGAs up to 8000 gates. Plus.. the kit comes with the
APS-X84 FPGA
test board which has an FPGA installed, and allows you to program the
FPGA in
circuit and write C test code on the PC to write and read test vectors
through it.
This is a very low VERY COMPLETE system. The kit also comes with full
capabilities
to program all of XILINXs CPLD in circuit programmable family. At
$350.00 this has to the best value going !

see: http://www.associatedpro.com/aps

Adam Seychell wrote:

>  Which manufacture of PGAs would make it possible for the hobbyist to
> use this technology. Obviously the manufactures are mainly interested
> in the big customers and so charge big bucks for their development
> products. So far I've investigated  Lattice, Altera & Xilinx and they
> all have unrealistic prices for their design software. The cost of the
> chips are relativly small ($10-$20 each). The cheapest design package
> was around ($850 Australian). Maybe I haven't looked around enough,
> but if anyone has managed to use re-programable PGAs for a home
> project, then please direct me to a source.
>
> I am interested in  devices capable of In System Programable and In
> System Configerable. This has led me to the following products
>
>                                             erase/program cycles
>   Lattice:     ispLSI1000  series                1000
>    Altera:     FLEX6000  series                infinite
>    Altera:     MAX7000  series                   100
>    Xilinx:     XC3000 series                   infinite
>   Philips:     PZ5000  series                    1000
>
>
>
> Adam



Article: 8221
Subject: ROUTER/TEST BOARD/CPLD/FPGA all for $350.00
From: Richard Schwarz <aps@associatedpro.com>
Date: Sat, 29 Nov 1997 20:00:26 -0500
Links: << >>  << T >>  << A >>
APS currently is selling a complete XILINX kit for $350.00 which allows
you to program FPGAs up to 8000 gates. Plus.. the kit comes with the
APS-X84 FPGA
test board which has an FPGA installed, and allows you to program the
FPGA in
circuit and write C test code on the PC to write and read test vectors
through it.
This is a very low VERY COMPLETE system. The kit also comes with full
capabilities
to program all of XILINXs CPLD in circuit programmable family. At
$350.00 this has to the best value going !

see: http://www.associatedpro.com/aps

Article: 8222
Subject: Re: what is metastability time of a flip_flop
From: ScottF@emu.com (J. Scott Fuller)
Date: Sun, 30 Nov 1997 04:15:50 GMT
Links: << >>  << T >>  << A >>
On Wed, 26 Nov 1997 17:21:04 CET, marc@aargh.mayn.de (Marc Heuler)
wrote:

>In article <3479BE43.5D67@data-io.com>, Tom Bowns writes:
>
>> Whether the flip-flop will enter the metastable state in the first
>> place, and how long it takes to resolve out of the metastable state into
>> a solid HIGH or LOW depends primarily upon the process technology of the
>> device.
>
>Hm, when the flipflop is metastable, can it be recovered by another clock
>pulse with valid setup/hold?  Or is it on its bad trip for an uncertain
>amount of time not accepting any new input?

A subsequent clock pulse with a valid setup and hold will resolve
the metastable state.  This subsequent clock replaces the metastable
state with a stable value.
Article: 8223
Subject: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
From: spp@bob.eecs.berkeley.edu
Date: 30 Nov 1997 13:28:37 GMT
Links: << >>  << T >>  << A >>
John Cooley <jcooley@world.std.com> wrote:

> Yea, I do have personal opinions about Verilog & VHDL.  Most
> engineers do.  What I tried very hard to do was to suppress my
> personal views and let the contest and subsequent user response
> settle this issue.

Now, just how do you expect us to believe you have
suppressed your personal views when your write up
makes continuous use of phrases such as 'VHDL bigots' ??

Anyway.  I like verilog too, just wish it had types, operator
overloading, consistent treatment of reg's vs. nets, multidimensional
arrays, a for-generate construct, and a better preprocessor.
I think our best shot at a truly good HDL is to upgrade
Verilog, rather than forcing unwilling users to use VHDL 
because it is has these features.

Cheers,

Steve
Article: 8224
Subject: Xilinx .bit file format.
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 1 Dec 1997 03:51:26 GMT
Links: << >>  << T >>  << A >>
Hello...

   Does anyone have the Xilinx .bit file format?  It appears to be
the binary bitstream and some 67-byte header in front which includes
the part number, source (.ngd) file name, and date of creation.
Anyone have a technical description of this header?

    Cheers,
    Jake


--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html


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