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Ray Andraka wrote: > sachink321@gmail.com wrote: > > > Environment in which system works: > > > > Microblaze softcore processor on spartan 3 fpga board > > compact flash, acting as a mass storage. > > > > How to access the compact flash in embedded applications > > write to and read from the compact flash? how to access the FAT table? > > to which sector i need to write, which address? > > > > which mode of addressing is easy way out > > CHS or LBA?? > > > > I got no clue how to access, it would be great help if i could > > understand in and out of doing tht becoz i need to write a code in C > > > > Thanks in advance > > > > http://www.compactflash.org/faqs/faq.htm You can register for free and > download the CF3 spec from there. > If you are just using the CF for mass storage that does not have to be > read by a PC, then you needn't format it with a PC file structure. In > that case it is simply a matter of converting your address to a sector > and offset into the sector. There is a bit less bookkeeping if you use > LBA, but either one is relatively easy. Hi Ray im using CF for only Mass storage it does not have to be read by PC the problem is to address a particular sector will LBA make it easier to address? how do i do this addressing? how does this thing work?Article: 100401
Hi, I have a IP block which is responsible of receiving all different kinds of external inputs and condition them. Once received siganls are validated than i need to pass them to different IPs and also to the centralized memory place (like BRAM) so they can be shared with the processor. Here is my problem: 1. If the received signal needs to be consumed by two or three different IPs how can i do that. I cannot use the BRAM for that as prefered way is to have them connect directly to signal processing IP. So Signal Processing Block ---> User IP(s) 2. What are the methods to hardcode the connections between the two user IP. I mean without using bus. Just Point to Point connection. I think it has to do with the net names but need some more explanation on that how to do. Thanks FizzyArticle: 100402
The -11X speed grade is dead as of this week. Do this some other way.Article: 100403
I don't really understand what's being asked but... It sounds like you want to create IP blocks that both "talk" to software via a bus (probably OPB) and also connect directly to other IP modules. And I assume you are working in the EDK. The import peripheral wizard tool will create the proper Verilog/VHDL wrappers for your IP. Within the user logic module, you will specify all the I/O that you want for a particular IP block. If you want to connect it entirely to the OPB, meaning only software controlled, then you would not specify any I/O signals. You would instantiate your module inside the user logic and just pass signals back and forth via slave register writes/reads. However, it sounds like you want both software and hardware signals. The I/O that you specify in the user logic wrappers will eventually become the I/O signals that the IP module has available. Inside the EDK these signlas will show up and you can connect them directly to any other IP that you wish. There is some good documentation in the EDK install directory. I hope this helps. If I totally missed the question, let me know.Article: 100404
I didn't see this info on Xilinx's site! Is it official? On the last Virtex-4 datasheet (ds302) the speed grade -12x disapeared but not the -11x! mike_la_jolla wrote: > The -11X speed grade is dead as of this week. Do this some other way.Article: 100405
Having seen way too much spam on this newsgroup lately, I have come with a possible solution that just might work. Add a section to FPGA FAQ where the known names on the newsgroup will list the companies they recommend (plus some explanation). Next time someone spams the list about "high quality PCB", or what the hell it is, we post a polite response saying that no one should support spammer companies and we suggest you choose another manufacture from the list below (link to FPGA-FAQ follows).Given that spammers only care about money, seeing they are loosing customers might stop them from spamming the list. This way, you will also support the local companies that you think are doing a good job ;) We could also add another section about newsgroup netiquette, 3leet English and what we think about doing other peoples homework. This is of course not as big problem as spammer, but it is still a little bit annoying sometimes. Furthermore, someone should contact Google, notifying them about the existence of a group FAQ. I think the biggest problem with the FAQ is that the ones that dont know about it are the ones that really need to read it :) regards - BrunsArticle: 100406
Salil Raje wrote: > Hi - > > Hmm.. Speaking for PlanAhead, this is a setup that we definitely do not test > on. > Not sure if I can help you, but answers to a couple of our questions may > give us a clue: > > 1. Are you running on a notebook? No it's a workstation. Intel CPU dual core, 2Go of RAM. > 2. Does it hang consistently or semi-repeatably? If so, how? CPU remains > idle or is it pegged? It's not fully repeatable. I mean it always crash but not always at the same point but it happens quite fast. I think it's always related to a GUI action. I mean, if I don't do anything with it it will stay fine (i.e still refresh the window when another window passes over), but possibly at the next button click or action on a text field, it will just stop responding. AFAIK, cpu is idle when it's freezed but I'll need to confirm that on monday. > BTW, can you download 8.1.5 at www.xilinx.com/planahead and see if you still > get this problem? I'll try that on monday. SylvainArticle: 100407
I have an Actel design with a 3 clocks. I need to define two of them in
Synplify (v8.5):
define_clock -name {n:clk2} -freq 20
define_clock -name {n:clk1} -freq 100
This will make Synplify to insert clock buffers in the design:
clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);
The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
these buffers as it will assign the clocks to global clock networks
anyway:
Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
a clock net which is not needed. Before compiling this design, this
macro must be removed from the design.
How do i get rid of them? I tried to fix this by setting the max fanout
to a very high value:
define_attribute {n:clk1} syn_maxfan {200000}
define_attribute {n:clk2} syn_maxfan {200000}
but it didnt work :(
Designer has an option for removing unsued buffers, but I never get to
the optimization stage. Any suggestions how i can stop Synplify from
inserting clock buffers or get Designer to ignore the buffer?
regards,
- Burns
PS. here are the rest of the constraints
forward annotated from Synplify to Designer (as SDC constraints):
create_clock -period 50 -waveform {0.000000 25.00000} clk2
create_clock -period 10 -waveform {0.000000 5.00000} clk1
additional PDC constraints imported to Designer:
assign_global_clock -net {clk2}
assign_global_clock -net {clk1}
Article: 100408Hi everyone, I'm considering making a compiler for Atmels FPSLIC (combined microcontroller with FPGA). The idea is to mark expensive funktions, so they can be implemented in the FPGA instead of normal machine code. I have experience with microcontrollers and construction of compilers, but I have only made very small test-projects with a very old FPGA and really buggy software. Is this possible to make such a compiler? Does it make sense at all to compile high-level language to a FPGA in this way? Has someone else made it/is this normal procedure today ? Regards, Niels SandmannArticle: 100409
I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was going to put the resistor at the DDR but use the FPGAs DCI to terminate at the FPGA using a series resistance. Can I do this or have I missed a trick somewhere along. Cheers JonArticle: 100410
sachink321@gmail.com wrote: > Hi Ray > im using CF for only Mass storage > it does not have to be read by PC > the problem is to address a particular sector > will LBA make it easier to address? > how do i do this addressing? > how does this thing work? > LBA makes it easier. Basically you give it a sector number, which is an address to one of the sectors. It will access one sector at at time, each sector is 512 bytes, presented two bytes at a time. In order to be successful accessing it you really have to pick up the Compact Flash specification and study that. I can't adequately describe the interface in a post. You'll need either a state machine or a small microcontroller to sequence the commands to it. For basic access, you'll need at least the identify, read sector and write sector commands.Article: 100411
burn.sir@gmail.com wrote:
> I have an Actel design with a 3 clocks. I need to define two of them in
> Synplify (v8.5):
>
> define_clock -name {n:clk2} -freq 20
> define_clock -name {n:clk1} -freq 100
>
>
> This will make Synplify to insert clock buffers in the design:
>
> clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);
>
>
>
> The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
> these buffers as it will assign the clocks to global clock networks
> anyway:
>
> Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
> a clock net which is not needed. Before compiling this design, this
> macro must be removed from the design.
>
>
> How do i get rid of them? I tried to fix this by setting the max fanout
> to a very high value:
> define_attribute {n:clk1} syn_maxfan {200000}
> define_attribute {n:clk2} syn_maxfan {200000}
>
> but it didnt work :(
>
I don't have version 8.5 of Synplify, but the rather old version I have
has the attribute syn_noclockbuf for this purpose.
Article: 100412"maxascent" <maxascent@yahoo.co.uk> wrote in message news:j5ednbW2A7vePqrZRVn_vA@giganews.com... > > I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I > downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put > resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was > going to put the resistor at the DDR but use the FPGAs DCI to terminate at > the FPGA using a series resistance. Can I do this or have I missed a trick > somewhere along. > > Cheers > > Jon Jon, You have to carefully look at what the DCI options are for a particular type of line. The V2-Pro user guide is the best source of this information. As I recall, the 25 (22?) ohm series output is only available by itself when the IOB is an output (only). If the IOB is bidir (as is the case for the DQ and DQS lines) then you also get the two parallel (supply-to-ground) 100 ohm terminations. These get the FPGA really hot if you're using a lot of IOBs, in this configuration. Also, I believe that there are different DCI options depending on whether you're using Class I or Class II SSTL. The best thing to do is to simulate the entire ram circuit and see what type of termination you really need. As long as you meet your setup and hold times, and don't violate the undershoot/overshoot specs of the ram and FPGA, you may be able to simplify the termination scheme. BobArticle: 100413
That was actually the first thing that I tired. Needless to say, it did not workArticle: 100414
Niels Sandmann wrote: > I'm considering making a compiler for Atmels FPSLIC (combined > microcontroller with FPGA). The idea is to mark expensive funktions, so > they can be implemented in the FPGA instead of normal machine code. Remember, that transferring operators to special purpose computing blocks takes some time. The gain of speed with the function block must be big enough to make it worth. > I > have experience with microcontrollers and construction of compilers, but > I have only made very small test-projects with a very old FPGA and > really buggy software. > > Is this possible to make such a compiler? > Does it make sense at all to compile high-level language to a FPGA in > this way? It is possible - if also usable, I don't know. There is some research about Field Programmable Function Arrays. There compiler are used to analyze C code and map this to configurable function blocks in the FPFA. Why FPFAs and not normal FPGAs? Its easier to map a software algorithm to a known block of hardware, where only "little" configuration is possible (add or sub or none, multiply or not, intermediate register storage or not...). Mapping a software algorithm to FPGAs is possible with languages like SystemC. I am not an expert in this area. I just want to give you some words, where your search may start. RalfArticle: 100415
burn.sir@gmail.com wrote:
> That was actually the first thing that I tired.
>
> Needless to say, it did not work
>
It works fine for me on Xilinx parts, so that would appear to be a
regression in Synplify if it doesn't work in the version you have. Or
perhaps it is a problem in the Actel synthesis. It shows up in the
project.sdf file like this:
define_attribute {CLK} syn_noclockbuf {1}
With the attribute set to '1', the edf file contains:
(instance CLK_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
)
With the attribute set to '0':
(instance CLK_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
)
Article: 100416I'm curious: why have you chosen Atmel's FPSLIC? - a Niels Sandmann <usenet.s@ndmann.dk> writes: > Hi everyone, > > I'm considering making a compiler for Atmels FPSLIC (combined > microcontroller with FPGA). The idea is to mark expensive funktions, so > they can be implemented in the FPGA instead of normal machine code. I > have experience with microcontrollers and construction of compilers, > but I have only made very small test-projects with a very old FPGA and > really buggy software. > > Is this possible to make such a compiler? > Does it make sense at all to compile high-level language to a FPGA in > this way? > Has someone else made it/is this normal procedure today ? > > Regards, > Niels SandmannArticle: 100417
Niels Sandmann wrote:
> Is this possible to make such a compiler?
There's one for nios:
http://www.altera.com/literature/wp/C2H_Compiler_FAQ.pdf
-- Mike Treseler
Article: 100418You will probably need to add a plb bus to your system. On that bus I would guess you'd need a plb BRAM if cntlr and your own IP. The if_cntlr would be hooked to that second port on the shared BRAM and your IP would need to be a PLB master. So somehow your "FPGA design" needs to become the PLB master, probably using the IP wizard. Good luck... JoeyArticle: 100419
Thanks for replying... Can you guide me to some examples or literature which can tell me how to connect to IP directly.Article: 100420
Amal wrote:
> Google is not broken, but it's not quite what I need. A dual-clock,
> dual-port block memory mapped to RAMB16 using VHDL!
A dual write port RAM template would
have to include a description of the
arbitration of simultaneous
writes to the same address. Lacking
this, there is no guarantee that
simulation and synthesis would match.
Your choices are
1. Use a vendor-specific instance or
2. Use a supported RAM template and add separate
logic to cover all the required cases.
-- Mike Treseler
Article: 100421Niels Sandmann wrote: > Hi everyone, > > I'm considering making a compiler for Atmels FPSLIC (combined > microcontroller with FPGA). The idea is to mark expensive funktions, so > they can be implemented in the FPGA instead of normal machine code. I > have experience with microcontrollers and construction of compilers, but > I have only made very small test-projects with a very old FPGA and > really buggy software. > > Is this possible to make such a compiler? > Does it make sense at all to compile high-level language to a FPGA in > this way? > Has someone else made it/is this normal procedure today ? > > Regards, > Niels Sandmann Boy, that would be interesting. There may be part of a doctorate in there if you work it right. I think this is possible. I think the shortest road to success in the confines of one file would be to make a preprocessor that would extract the FPGA stuff to a C language design file which would then go to one of those nifty new C language synthesis tools. I suspect, though, that this would cause problems with concurrency. Either you would have concurrency problems in the function call, or in making the processor wait on the FPGA and visa versa. If you _really_ wanted to do this in one language you could investigate the possibility of reviving Occam*. All in all, however, I think the best thing to do is find a good way that you can treat what the FPGA does as a concurrent process within C or C++. This would mean finding a way, within C, of 'telling' the compiler to write something to the FPGA and kick off a computation, then 'telling' the compiler to retrieve it, but leaving it to the software and FPGA designers to actually synchronize the FPGA with the processor. * Search for 'transputer'. The best quote I heard about Occam was "Oakum (Occam) is something you use to keep boats from leaking -- not a computer language". -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/Article: 100422
Finally I could map to RAMB16 on Xilinx Virtex and Synplify using the
followig:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
entity DualPortMemory is
generic (
DEPTH : positive;
WIDTH : positive
);
port (
-- port a (read/write)
clka : in std_logic;
ena : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(integer(ceil(
log2(real(DEPTH))))-1 downto 0);
dia : in std_logic_vector(WIDTH-1 downto 0);
doa : out std_logic_vector(WIDTH-1 downto 0);
-- port b (read/write)
clkb : in std_logic;
enb : in std_logic;
web : in std_logic;
addrb : in std_logic_vector(integer(ceil(
log2(real(DEPTH))))-1 downto 0);
dib : in std_logic_vector(WIDTH-1 downto 0);
dob : out std_logic_vector(WIDTH-1 downto 0)
);
end entity DualPortMemory;
architecture rtl of DualPortMemory is
type MEM_TYPE is array(0 to DEPTH-1) of
std_logic_vector(WIDTH-1 downto 0);
signal memory : MEM_TYPE;
attribute syn_ramstyle : string;
attribute syn_ramstyle of memory : signal is "block_ram";
attribute syn_ramstyle of memory : signal is "no_rw_check";
begin
--------------------------------------
-- Port A (read/write)
--------------------------------------
p_Port_A: process( clka )
begin
if ( rising_edge(clka) ) then
if ( ena = '1' ) then
if ( wea = '1' ) then
memory( conv_integer(unsigned(addra)) ) <= dia;
end if;
doa <= memory( conv_integer(unsigned(addra)) );
end if;
end if;
end process p_Port_A;
--------------------------------------
-- Port B (read/write)
--------------------------------------
p_Port_B: process( clkb )
begin
if ( rising_edge(clkb) ) then
if ( enb = '1' ) then
if ( web = '1' ) then
memory( conv_integer(unsigned(addrb)) ) <= dib;
end if;
dob <= memory( conv_integer(unsigned(addrb)) );
end if;
end if;
end process p_Port_B;
end architecture rtl;
No collision check is done here.
-- Amal
Article: 100423
Amal wrote:
> Finally I could map to RAMB16 on Xilinx Virtex and Synplify
I don't have Synplify, so I can't verify this.
I like your idea of using math_real
functions for synthesis constants,
however, I am unconvinced that this a useful
simulation model since the signal _memory_
is driven by both processes.
And you may have a typo one one of these
duplicated attribute specifications:
> attribute syn_ramstyle of memory : signal is "block_ram";
> attribute syn_ramstyle of memory : signal is "no_rw_check";
> No collision check is done here.
True, but a vhdl simulator knows nothing
about Synplify attributes declarations.
-- Mike Treseler
Article: 100424Niels Sandmann wrote: > Hi everyone, > > I'm considering making a compiler for Atmels FPSLIC (combined > microcontroller with FPGA). The idea is to mark expensive funktions, so > they can be implemented in the FPGA instead of normal machine code. Sometimes an 'expensive' item might be an operator. ie Maths libraries, and their support is one productive area that does not need armloads of new software. > I have experience with microcontrollers and construction of compilers, but > I have only made very small test-projects with a very old FPGA and > really buggy software. > > Is this possible to make such a compiler? almost anything is possible ... > Does it make sense at all to compile high-level language to a FPGA in > this way? depends a lot on the FPGA, and the project, ( and the designer..) [ It is also a dangerous tool in the wrong hands....] > Has someone else made it/is this normal procedure today ? Someone has mentioned Altera's new C flow ( not cheap ) For good examples of FPGA centric work on other languages, look at http://www.jopdesign.com/ http://myhdl.jandecaluwe.com/doku.php/cookbook:intro and for an example of a smaller FPGA-Core, and what can be done in core-extension, look at this carefully before commiting to the FpSLIC ( which is rather a dead-end pathway ). http://bleyer.org/pacoblaze/ A google on Python AVR ( if you MUST use the FpSLIC ) finds quite a lot, including http://savannah.nongnu.org/patch/?func=detailitem&item_id=3763 http://www.ecs.soton.ac.uk/~jb1403/projects/avrpy/ -jg
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