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In article <bihpt1t46dm7afskbo72gqe1qb9fi5j3c2@4ax.com>, Brian Drummond <brian@shapes.demon.co.uk> wrote: >On 29 Jan 2006 03:37:49 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: > >> >>I've set up a wiki space for discussion of ideas for an open source XDL tool >>suite. For those not familiar with wikis, they are collaborative web spaces >>that can be edited by anyone (for now it is editable by anyone; if there are >>problems we can restrict edit access to approved authors) or by a >>select set of individuals. They're used quite commonly for software projects >>now as they are great for discussion of features, todo lists, idea boards, etc. >> >>If you had tools that could parse and programatically generate XDL how would >>you use them? Some suggestions have been made in other recent threads here on >>comp.arch.fpga, now let's collect those ideas in the wikispace that I've setup >>here: >>http://thoughtfiz.stikipad.com/XDL_Tools/ > >Thanks Phil... > >ummm... > >is there any way to access it? > >it keeps asking me to login (which I don't mind, except that I don't >have an account, and there's no "register" button :-) It appears to be a bug at stikipad (it's a fairly new service). I keep tryinng to edit the configuration so that the wiki is viewable by anyone, but it keeps reverting back to 'viewable by authors only' mode. I sent an email to support. In the meantime, you could become an author by getting an account at stikipad: http://stikipad.com Then you'd be able to log in. (BTW: it's a pretty cool service, if you sign up you get one free wiki) > >>There is a Feature Request page you'll see on the home page. You can go to >>that page and edit it or you can add comments to any page by clicking on the >>'Discuss' link at the right hand side of the page. > >well that's one "feature request" but you'll forgive me for not posting >it in the right place :-) > >- Brian >(who is almost sorry for "pushing" XDL having seen what the discussion >degenerated into) No problem. Definitely looking forward to your input. PhilArticle: 96076
In article <drihtm$qg9$01$1@news.t-online.com>, Antti Lukats <antti@openchip.org> wrote: >"Brian Drummond" <brian_drummond@btconnect.com> schrieb im Newsbeitrag >news:bihpt1t46dm7afskbo72gqe1qb9fi5j3c2@4ax.com... >> On 29 Jan 2006 03:37:49 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >> >>> >>>I've set up a wiki space for discussion of ideas for an open source XDL >>>tool >>>suite. For those not familiar with wikis, they are collaborative web >>>spaces >>>that can be edited by anyone (for now it is editable by anyone; if there >>>are >>>problems we can restrict edit access to approved authors) or by a >>>select set of individuals. They're used quite commonly for software >>>projects >>>now as they are great for discussion of features, todo lists, idea boards, >>>etc. >>> >>>If you had tools that could parse and programatically generate XDL how >>>would >>>you use them? Some suggestions have been made in other recent threads >>>here on >>>comp.arch.fpga, now let's collect those ideas in the wikispace that I've >>>setup >>>here: >>>http://thoughtfiz.stikipad.com/XDL_Tools/ >> >> Thanks Phil... >> >> ummm... >> >> is there any way to access it? >> >> it keeps asking me to login (which I don't mind, except that I don't >> have an account, and there's no "register" button :-) >> >>>There is a Feature Request page you'll see on the home page. You can go >>>to >>>that page and edit it or you can add comments to any page by clicking on >>>the >>>'Discuss' link at the right hand side of the page. >> >> well that's one "feature request" but you'll forgive me for not posting >> it in the right place :-) >> >> - Brian >> (who is almost sorry for "pushing" XDL having seen what the discussion >> degenerated into) > >Hi Brian, > >agree 'degenerated' is a mild word for whats happened - XDL has been around >for pretty long time and if those interested in the use of XDL have not done >so far, well that is not the fault of Xilinx (and its license policy). > >hum, as of the Phil's setup thing, it looked weird that someone is password >login authorization protecting websites about some Open-Source discussion. >At first I did not want to register at all, then did come back determined to >register, but failed to register completly as there seems to be no way to >access the pages at all :( > > >Antti Lukats >http://help.xilant.com/XDL:Tools > Antti, As I mentioned in the post in reply to Brian, the wiki is hosted by http://stikipad.com - they let you host one wiki for free. I think there is a bug in their system that does not allow me to make the wiki viewable to everyone. If you go to http://stikipad.com you can sign up for an account and then you can view the wiki. Hopefully this problem will be addressed soon so that you won't have to sign up. PhilArticle: 96077
In article <drihtm$qg9$01$1@news.t-online.com>, Antti Lukats <antti@openchip.org> wrote: >"Brian Drummond" <brian_drummond@btconnect.com> schrieb im Newsbeitrag >news:bihpt1t46dm7afskbo72gqe1qb9fi5j3c2@4ax.com... >> On 29 Jan 2006 03:37:49 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >> >>> >>>I've set up a wiki space for discussion of ideas for an open source XDL >>>tool >>>suite. For those not familiar with wikis, they are collaborative web >>>spaces >>>that can be edited by anyone (for now it is editable by anyone; if there >>>are >>>problems we can restrict edit access to approved authors) or by a >>>select set of individuals. They're used quite commonly for software >>>projects >>>now as they are great for discussion of features, todo lists, idea boards, >>>etc. >>> >>>If you had tools that could parse and programatically generate XDL how >>>would >>>you use them? Some suggestions have been made in other recent threads >>>here on >>>comp.arch.fpga, now let's collect those ideas in the wikispace that I've >>>setup >>>here: >>>http://thoughtfiz.stikipad.com/XDL_Tools/ >> >> Thanks Phil... >> >> ummm... >> >> is there any way to access it? >> >> it keeps asking me to login (which I don't mind, except that I don't >> have an account, and there's no "register" button :-) >> >>>There is a Feature Request page you'll see on the home page. You can go >>>to >>>that page and edit it or you can add comments to any page by clicking on >>>the >>>'Discuss' link at the right hand side of the page. >> >> well that's one "feature request" but you'll forgive me for not posting >> it in the right place :-) >> >> - Brian >> (who is almost sorry for "pushing" XDL having seen what the discussion >> degenerated into) > >Hi Brian, > >agree 'degenerated' is a mild word for whats happened - XDL has been around >for pretty long time and if those interested in the use of XDL have not done >so far, well that is not the fault of Xilinx (and its license policy). > >hum, as of the Phil's setup thing, it looked weird that someone is password >login authorization protecting websites about some Open-Source discussion. >At first I did not want to register at all, then did come back determined to >register, but failed to register completly as there seems to be no way to >access the pages at all :( > > >Antti Lukats >http://help.xilant.com/XDL:Tools ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Antti, It seems you already have a wiki with an entry for XDL tools, can we use it if we can't get the stikipad wiki to be publicly viewable? PhilArticle: 96078
In article <drk7173uhr@enews3.newsguy.com>, Phil Tomson <ptkwt@aracnet.com> wrote: >In article <drihtm$qg9$01$1@news.t-online.com>, >Antti Lukats <antti@openchip.org> wrote: >>"Brian Drummond" <brian_drummond@btconnect.com> schrieb im Newsbeitrag >>news:bihpt1t46dm7afskbo72gqe1qb9fi5j3c2@4ax.com... >>> On 29 Jan 2006 03:37:49 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >>> >>>> >>>>I've set up a wiki space for discussion of ideas for an open source XDL >>>>tool >>>>suite. For those not familiar with wikis, they are collaborative web >>>>spaces >>>>that can be edited by anyone (for now it is editable by anyone; if there >>>>are >>>>problems we can restrict edit access to approved authors) or by a >>>>select set of individuals. They're used quite commonly for software >>>>projects >>>>now as they are great for discussion of features, todo lists, idea boards, >>>>etc. >>>> >>>>If you had tools that could parse and programatically generate XDL how >>>>would >>>>you use them? Some suggestions have been made in other recent threads >>>>here on >>>>comp.arch.fpga, now let's collect those ideas in the wikispace that I've >>>>setup >>>>here: >>>>http://thoughtfiz.stikipad.com/XDL_Tools/ >>> >>> Thanks Phil... >>> >>> ummm... >>> >>> is there any way to access it? >>> >>> it keeps asking me to login (which I don't mind, except that I don't >>> have an account, and there's no "register" button :-) >>> >>>>There is a Feature Request page you'll see on the home page. You can go >>>>to >>>>that page and edit it or you can add comments to any page by clicking on >>>>the >>>>'Discuss' link at the right hand side of the page. >>> >>> well that's one "feature request" but you'll forgive me for not posting >>> it in the right place :-) >>> >>> - Brian >>> (who is almost sorry for "pushing" XDL having seen what the discussion >>> degenerated into) >> >>Hi Brian, >> >>agree 'degenerated' is a mild word for whats happened - XDL has been around >>for pretty long time and if those interested in the use of XDL have not done >>so far, well that is not the fault of Xilinx (and its license policy). >> >>hum, as of the Phil's setup thing, it looked weird that someone is password >>login authorization protecting websites about some Open-Source discussion. >>At first I did not want to register at all, then did come back determined to >>register, but failed to register completly as there seems to be no way to >>access the pages at all :( >> >> >>Antti Lukats >>http://help.xilant.com/XDL:Tools >> > >Antti, > >As I mentioned in the post in reply to Brian, the wiki is hosted by >http://stikipad.com - they let you host one wiki for free. I think there is a >bug in their system that does not allow me to make the wiki viewable to >everyone. If you go to http://stikipad.com you can sign up for an account and >then you can view the wiki. Hopefully this problem will be addressed soon so >that you won't have to sign up. > OK, I just got the word from stikipad: it turns out that they weren't very clear in the setup that you can only have a publicly available wiki if you pay $4.95/month. Otherwise you can have other people sign up as authors at stickipad.com. So, now I'm not sure if the stikipad wiki is going to be all that useful... $4.95 isn't all that much, but I'd rather look into some alternatives where I could host all my web projects (not just a wiki) for about the same price. PhilArticle: 96079
wtxwtx@gmail.com wrote:
> Tristate gates are used everywhere in an ASIC chip with no exception of
> FPGA. BLOCK RAM in Xilinx chip has to use tristate to get the selected
> data to output.
I can't think of a FPGA device new enough to have block RAM
yet old enough to have a real internal tri-state bus.
-- Mike Treseler
Article: 96080"Phil Tomson" <ptkwt@aracnet.com> schrieb im Newsbeitrag news:drk77r4uhr@enews3.newsguy.com... > In article <drihtm$qg9$01$1@news.t-online.com>, > Antti Lukats <antti@openchip.org> wrote: >>"Brian Drummond" <brian_drummond@btconnect.com> schrieb im Newsbeitrag >>news:bihpt1t46dm7afskbo72gqe1qb9fi5j3c2@4ax.com... >>> On 29 Jan 2006 03:37:49 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >>> >>>> >>>>I've set up a wiki space for discussion of ideas for an open source XDL >>>>tool >>>>suite. For those not familiar with wikis, they are collaborative web >>>>spaces >>>>that can be edited by anyone (for now it is editable by anyone; if there >>>>are >>>>problems we can restrict edit access to approved authors) or by a >>>>select set of individuals. They're used quite commonly for software >>>>projects >>>>now as they are great for discussion of features, todo lists, idea >>>>boards, >>>>etc. >>>> >>>>If you had tools that could parse and programatically generate XDL how >>>>would >>>>you use them? Some suggestions have been made in other recent threads >>>>here on >>>>comp.arch.fpga, now let's collect those ideas in the wikispace that I've >>>>setup >>>>here: >>>>http://thoughtfiz.stikipad.com/XDL_Tools/ >>> >>> Thanks Phil... >>> >>> ummm... >>> >>> is there any way to access it? >>> >>> it keeps asking me to login (which I don't mind, except that I don't >>> have an account, and there's no "register" button :-) >>> >>>>There is a Feature Request page you'll see on the home page. You can go >>>>to >>>>that page and edit it or you can add comments to any page by clicking on >>>>the >>>>'Discuss' link at the right hand side of the page. >>> >>> well that's one "feature request" but you'll forgive me for not posting >>> it in the right place :-) >>> >>> - Brian >>> (who is almost sorry for "pushing" XDL having seen what the discussion >>> degenerated into) >> >>Hi Brian, >> >>agree 'degenerated' is a mild word for whats happened - XDL has been >>around >>for pretty long time and if those interested in the use of XDL have not >>done >>so far, well that is not the fault of Xilinx (and its license policy). >> >>hum, as of the Phil's setup thing, it looked weird that someone is >>password >>login authorization protecting websites about some Open-Source discussion. >>At first I did not want to register at all, then did come back determined >>to >>register, but failed to register completly as there seems to be no way to >>access the pages at all :( >> >> >>Antti Lukats >>http://help.xilant.com/XDL:Tools > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > > Antti, > It seems you already have a wiki with an entry for XDL tools, can we use > it if > we can't get the stikipad wiki to be publicly viewable? > > Phil yes, of course. -- Antti Lukats http://www.xilant.comArticle: 96081
Bob wrote: > Simply dividing the sample clock by 12 (using a DCM) doesn't give you the > boundary of the 12bit sample. You only have a one-in-twelve chance of > getting it right. There is no way to deduce the sample boundary by > inspecting the serial data stream. I think we're getting confused here (I know I am) with the naming of our clocks. ;) Now, assuming the ADC sends out, together with the data, a fast clock of 420MHz, and a slow clock of 70MHz. Now what Eric calls the "sample clock" is the latter, which gives you the boundary of your 12bit sample. Now as I understand it, what Eric is suggesting is to feed the FPGA with this slow "sample clock", to have ADC and FPGA running synchonously. We don't use the fast clock from the ADC as bit clock, but instead use a DCM to multiply the sample clock, and use this perfectly edge-aligned (the DCM takes care of that) clock to run the ISERDES. Now assuming that you feed all ADCs with the same clock source and the thermal conditions etc. are the same, all sample clocks returned from the ADCs should be identical (maybe with a little skew because of different trace lengths on the PCB, but the frequencies should match), so you only need to do this once for all ADCs. As Eric said, one DCM and two clock nets, regardless of how many channels you have. cu, SeanArticle: 96082
Kolja Sulimma schrieb am 29.01.2006 15:32: > Sean Durkin schrieb: >> And since the clocks you get >> from the ADCs are perfectly edge-aligned, > They are not. > They are out of phase between 330ps and 860ps at the ADC (according to > the datasheet). They will be more out of phase once they arrive inside > your FPGA. > You will not get away without delay buffers at these data rates. Yes, but as you stated earlier, THOSE are not the problem, since I have possibilities to delay in every IOB. The calibration has to be done anyway. What I'm trying to avoid is to introduce additional DCMs and clock nets. Up to now, every suggestion I've heard uses at least the same amount of DCMs and clock nets as the current solution (xapp774), which is something I can't afford once I have 8 or even more of those ADCs hooked up to one FPGA. cu, SeanArticle: 96083
Brian Davis wrote: > I was trying to point out that that capability already exists in the > V2 derived parts, and most likely in V4 as well (esp. with the V4 > differential clock tree, I'd expect one to get inverted clocks for free > with no local inversion skew penalty, but I haven't checked this yet). Yes, you're right, inverted clocks should be easy to get. I'll check that out sometime this week, once I find the time. But, you were right about the IBUFDS_DIFF_OUT: Those still exist in V4, and *tadaaa* I just found out you can actually feed the two ISERDES in one IOB tile with those 2 inverted outputs. So all I need now is to provide the ISERDES with 0/180 clocks. Not sure when I'll find the time to check that out. Getting the clocks shouldn't be a problem, but maybe driving the ISERDES in one IOB tile with different clocks is. > Clocking high speed A/D's with an FPGA generated clock is a very > bad idea, as the inherent DCM & SSO jitter will quickly render the > sub-ps RMS A/D aperture jitter specs useless, giving you maybe > a handful of effective bits worth of data at the rated A/D input > bandwidth. You're absolutely right, which is why I'm looking for programmable external clock sources at the moment. BTW, any recommendations? Up to now the fastest I had these ADCs running was 40MHz (the fastest speedgrades aren't available yet), and there it did still work reliably. But in the future this has to work for 70MHz as well, so I'll be transitioning to "proper" clock sources. cu, SeanArticle: 96084
Hi All, We are developing a product which uses a Cyclone2 device from Altera. The unit is a completely sealed unit with only a RS232 link to the outside. We want to be able to update the Cyclone2 configuration files stored in a EPC device using the available RS232 link. Has anyone done something similar out there? I have thought of writing a PC application which would serially send the configuration files from the PC to a AVR and then the AVR would program the EPC. There are a few unknows for me here. 1. Which output file format could I use and interpret seeing that it seems as if the .pof files generated by the Quartus software must be interpreted and can only be used by Quartus? 2. Are EPC devices the best things to use as there are numerous other flash based configuration devices out there?Article: 96085
hi, Im hoping to start developement using MacroBlaze softcore. currently i got some experiance in using FPGA with vhdl implementations but never tried soft core development. i need to know the requrements (from hardware and software side) i should have to start this. thanksArticle: 96086
Hans wrote: > If you have to choose a C language I would recommend you check out SystemC > which might be better on your CV than Handel-C :-) What's so good about SystemC? :)Article: 96087
Try taking a look at how Parallax does this with their SmartPack development boards. They do the same thing as you're suggesting only with a PIC instead of an AVR. Keith "Amigo" <rmichau@grintek.com> wrote in message news:1138612161.902990.245260@g49g2000cwa.googlegroups.com... > Hi All, > > We are developing a product which uses a Cyclone2 device from Altera. > The unit is a completely sealed unit with only a RS232 link to the > outside. We want to be able to update the Cyclone2 configuration files > stored in a EPC device using the available RS232 link. Has anyone done > something similar out there? > > I have thought of writing a PC application which would serially send > the configuration files from the PC to a AVR and then the AVR would > program the EPC. There are a few unknows for me here. > 1. Which output file format could I use and interpret seeing that it > seems as if the .pof files generated by the Quartus software must be > interpreted and can only be used by Quartus? > 2. Are EPC devices the best things to use as there are numerous other > flash based configuration devices out there? >Article: 96088
Hi. I'm working with the Virtex 4 on a ML403 and want to use the audio codec AC97. At first i want to connect a mp3-player to line in and then i want to manipulate the audiostream and send it to line out. But i don't find a detailled description (e.g not in ml403 userguide) of the audio codec. So i don't know which pin i should use. Does anybody know a paper/tutorial/user guide or something else, how to use the audio codec on ml403(virtex 4)? Thanks for your help. best regards, lori.Article: 96089
"CMOS" <manusha@millenniumit.com> wrote in message news:1138614381.749921.137590@g44g2000cwa.googlegroups.com... > hi, > Im hoping to start developement using MacroBlaze softcore. currently i > got some experiance in using FPGA with vhdl implementations but never > tried soft core development. i need to know the requrements (from > hardware and software side) i should have to start this. > > thanks > I did a quick Google, and Macroblaze appears to be a product which gets rid of waste gas from sewage sludge. I hate to think what a 'softcore' was in this context. :-) As luck would have it, Google suggested I might've meant Microblaze, which gave me 188000 hits! I chose this one, which has a wealth of documentation on said softcore! http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=micro_blaze HTH, Syms.Article: 96090
"Amigo" <rmichau@grintek.com> wrote in message news:1138612161.902990.245260@g49g2000cwa.googlegroups.com... > Hi All, > > We are developing a product which uses a Cyclone2 device from Altera. > The unit is a completely sealed unit with only a RS232 link to the > outside. We want to be able to update the Cyclone2 configuration files > stored in a EPC device using the available RS232 link. Has anyone done > something similar out there? Yes, with a Cyclone but I presume the same can be done with a Cyclone2. I have a core that allows an EPCS1/4 to be accessed from the FPGA over the FPGA programming lines, ie you don't need to waste any FPGA pins to use this functionality. It's currently driven by a SBC over a PCI interface, the SBC controls the download/verification of the config data. You would need to design in some extra control if you want to do this completely within the FPGA. This is being used in a shipping product and so far has proved very reliable. Nial Stewart ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 96091
nitul.das@gmail.com wrote: > Dear Friends. > > Well i am quite new to this FPGA thing...My project is on Video > Compression and i want it to implement in Xilinx platform. > > I am finding really difficult in acquiring the video frames and is it > possible to do it in simulator mode( AND NOT REAL TIME......!)??. It > would be really helpful if anybody could guide me. > > I have the latest Xilinx ISE 8.1i..is this platform sufficient or do i > need something else?? please guide someone..it is really important. For simulation I would suggest using a test image stored as a raw video file. Simulation and video acquisition won't play together, the time scales are off by many orders of magnitude. Photoshop can store picture files in a raw format (just the R, G, B values in binary, with or without a header). There are other ways to get raw images into a file, but this is perhaps easiest. Simulation can get the data directly from the file. Having a constant test image is also useful for debugging errors. Trying to debug with ever-changing video input data is not fun. Because simulation is slow, I would also suggest using a small (low resolution) image at first. You can test on larger images after compression is working on the small ones. Perhaps even do the larger image debug when you go to the hardware. This is probably an ambitious project for someone "new to this FPGA thing." While ISE is probably sufficient to get the job done, you may want to look into the Embedded development software to simplify your job somewhat... Good Luck, GaborArticle: 96092
Robin Bruce (robin.bruce@gmail.com) wrote: : Hans wrote: : > If you have to choose a C language I would recommend you check out SystemC : > which might be better on your CV than Handel-C :-) : What's so good about SystemC? :) What's so good about AnythingC? I have quite strong feelings that whilst a high level language than Verilog/VHDL could be a real boon to FPGA development, C is far from a good prototype form for such a language.... cdsArticle: 96093
"Amigo" <rmichau@grintek.com> writes: > We are developing a product which uses a Cyclone2 device from Altera. > The unit is a completely sealed unit with only a RS232 link to the > outside. We want to be able to update the Cyclone2 configuration files > stored in a EPC device using the available RS232 link. Has anyone done > something similar out there? You can have the Cyclone2 do ISP by controlling the JTAG port of the EPC. > I have thought of writing a PC application which would serially send > the configuration files from the PC to a AVR and then the AVR would > program the EPC. There are a few unknows for me here. Does your design include an AVR? If the RS232 is connected to the Cyclone2 and you have enough pins and some extra LEs you should be able to do this from the Cyclone. > 1. Which output file format could I use and interpret seeing that it > seems as if the .pof files generated by the Quartus software must be > interpreted and can only be used by Quartus? I've done similar things using SVF files. > 2. Are EPC devices the best things to use as there are numerous other > flash based configuration devices out there? There are cheaper FLASH devices out there, but you will need a small PLD to load data into the FPGA. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 96094
c d saunter wrote: > I have quite strong feelings that whilst a high level language than > Verilog/VHDL could be a real boon to FPGA development, C is far from a > good prototype form for such a language.... Depends greatly on what the application is that is targeted for FPGA's, and how much freedom is necessary to divide the application between LUT's, on chip microproccesors, and specialized statemachines such as p-code or jave VM's. For instance writing a pipelined wire speed network stack and application targeted for execution on FPGA's as a combination of logic and a VM is probably SIGNIFICANTLY easier to do in a C based language. Especially since you can use the same source compiled to LUT's, processors and VM's to partition the design in various ways as a late project optimization or to freely move between specific FPGA chips. Trying to instantate specific forms of logic for a complicated hardware design MIGHT be a bit easier in Verilog/VHDL, while being unable to easily move the same source code to a VM or processor as you optimize the system design or move between target chips. As with most highly specialized tools, you tradeoff generality and the degrees of freedom in design choices gained using more general tools with a larger implementation space.Article: 96095
Jidan Al-Eryani, one of my students, has implemented an FPU [1] which is now available for JOP. The FPU is connected via the SimpCon [2] bus and can be accessed as an IO device. That's not the most efficient solution, but ok for the first tests. Compared to the Verilog FPU at opencores, this one is written in VHDL, smaller and fully registerd. It can be clocked with 100MHz on a Cyclone C6 (instead of about 6MHz the fully asynchronous Verilog FPU). As the FPU is not enough tested the floating point bytecodes (from JOP) do not access the FPU at the moment. If you are interested in using the FPU with JOP see .../test/fpu/Basic.java how to access the FPU. Perhaps you can help to test it. The Quartus project the contains the FPU is 'cycfpu'. All sources are available from CVS [3]. Check them out with: cvs -d :pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous -z9 co -P jop change the project in the Makefile to 'cycfpu' (instead of 'cycmin') and build the project with make -e P1=test P2=fpu P3=basic Martin [1] http://www.opencores.org/projects.cgi/web/fpu100/overview [2] http://www.opencores.org/projects.cgi/web/simpcon/overview [3] http://www.opencores.org/projects.cgi/web/jop/overviewArticle: 96096
"Sean Durkin" <smd@despammed.com> wrote in message news:43ddc622$1@news.fhg.de... > Bob wrote: >> Simply dividing the sample clock by 12 (using a DCM) doesn't give you the >> boundary of the 12bit sample. You only have a one-in-twelve chance of >> getting it right. There is no way to deduce the sample boundary by >> inspecting the serial data stream. > I think we're getting confused here (I know I am) with the naming of our > clocks. ;) > > Now, assuming the ADC sends out, together with the data, a fast clock of > 420MHz, and a slow clock of 70MHz. Now what Eric calls the "sample > clock" is the latter, which gives you the boundary of your 12bit sample. > > Now as I understand it, what Eric is suggesting is to feed the FPGA with > this slow "sample clock", to have ADC and FPGA running synchonously. We > don't use the fast clock from the ADC as bit clock, but instead use a > DCM to multiply the sample clock, and use this perfectly edge-aligned > (the DCM takes care of that) clock to run the ISERDES. > > Now assuming that you feed all ADCs with the same clock source and the > thermal conditions etc. are the same, all sample clocks returned from > the ADCs should be identical (maybe with a little skew because of > different trace lengths on the PCB, but the frequencies should match), > so you only need to do this once for all ADCs. As Eric said, one DCM and > two clock nets, regardless of how many channels you have. > > cu, > Sean Ahhhh. Ok. TI call the faster clock "SCLK", but it actually stands for Serial Data Clock. The slower clock is "ADCLK". I think we're on the same page, now. Anywho, I think he's going to have a problem using the DCM to multiply by twelve. This would require use of the FX output which can have terrible jitter (depending on the m/n ratio used). I would be surprised if it could capture data reliably at 480Mbps, doing it this way. BobArticle: 96097
Are you going to design in VHDL or Verilog?Article: 96098
nitul.das@gmail.com wrote: > I am finding really difficult in acquiring the video frames and is it > possible to do it in simulator mode( AND NOT REAL TIME......!)??. It > would be really helpful if anybody could guide me. Yes, but you will have to create a testbench including something that simulates a video signal. This would probably be a simple video generator that reads an image file or a series of image files. If you don't meant to test the aquisition in simulation but only the processing, then use the other poster's suggestion and simply read image files into your processing buffers.Article: 96099
Hi Mike, I disagree with your opinion. BLOCK RAM data output is driven by its address, no matter it is old or brand new. How does it work for a 4K bytes block? Each RAM bit internally drives a 1-bit tristate data bus selected by its address decode logic. From outside, it is only one data output bus. For any CPUs, its SRAM in cache are also driven by its addresses. So tristate buses are as ubiquitous as a register. No any exception is for general FPGA design. Only passive tristate bus is rarely used and shouldn't be used for an active data bus. Weng Mike Treseler wrote: > wtxwtx@gmail.com wrote: > > > Tristate gates are used everywhere in an ASIC chip with no exception of > > FPGA. BLOCK RAM in Xilinx chip has to use tristate to get the selected > > data to output. > > I can't think of a FPGA device new enough to have block RAM > yet old enough to have a real internal tri-state bus. > > -- Mike Treseler
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