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Messages from 10125

Article: 10125
Subject: Re: FPGA input data rate limitations?
From: "Lev Razamat" <lrazamat@netvision.net.il>
Date: Tue, 28 Apr 1998 22:29:26 +0300
Links: << >>  << T >>  << A >>

I check 10k ALTERA 5v on the speed of 140 MHz. Works!!
But I did all design in AHDL and in some critical places need to define CLB
placement
manualy. CLIQUE some times does not help.
Good luck
Lev Razamat  -  PHASECOM Inc.



Article: 10126
Subject: Re: Enforcing Clock Enable Connection in Synthesis
From: allard jean-marc <jm.allard@hol.fr>
Date: Tue, 28 Apr 1998 19:33:49 +0000
Links: << >>  << T >>  << A >>
Tom Meagher wrote:
> 
> allard jean-marc wrote in message <3544D8ED.25D66CD1@hol.fr>...
> >Tom Meagher wrote:
> >>
> ...
> ...
> >>
> >
> >Synthesis tools I used (Synopsys, Compass RIP) have a command to specify
> >multicycle paths.
> >With synopsys, the command is 'set_multicycle_path'. Are you sure that
> >your tool doesn't have such a common feature ?
> >This command answer your 2 questions since clk_ena is out of the
> >multicycle
> >path.
> >
> >jean-Marc
> 
> Yes, this is true, there is a multi-cycle path command for Galileo and
> Synplify(see the excerpts
> below), but I interpret this to be on a signal by signal, or register by
> register basis,
> not for an entire instantiated sub-component, several levels down in the
> hierarchy, which
> might have hundreds of signals and registers.
> 
> And, even if one specified all the signals in the sub-component as
> multi-cycle,
> which seems rather tedious, I don't see how this forces the clock enables to
> be connected
> to the synthesized DFFE's.  Am I missing something here?


Maybe you can do this:

Synthesize alone the block for which all internal paths are double cycle
paths. 
Specifies for this block a clock of 12.5 Mhz and put a constraint on the
arrival time of clk_ena so that clk_ena is tied close to your DFF. For
example, says that clk_ena changes 5 ns before the rising clock edge.
The synthesys
tool will not necessary connect the clk_ena to the enable of yours FF
but close
to it and this is what you want.
Then synthesize the upper hierarchy blocks with a clock of 25 Mhz with a 
"set_dont_touch" on the 12.5 Mhz block.
If you find a better solution, could you please send it to me.

Jean-Marc
Article: 10127
Subject: Re: FPGA input data rate limitations?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Tue, 28 Apr 1998 12:39:48 -0700
Links: << >>  << T >>  << A >>
Dave Hawkins wrote:

> I have an application where I want to operate on either
> a 62.5MHz or 125MHz clock rate sample stream.
>
> Could anyone that has used FPGAs with high I/O data rates
> comment on what they would consider would be the highest
> data rate that, say, a 3.3V Altera Flex 10k130 could handle
> on its I/O pins?
>
> I am considering having a 62.5MHz clock and a 125MHz clock.
> Then having a 62.5MHz clock rate data stream multiplexed by
> 2 on-board where operations on the data are performed at 125MHz.
> Doubling the clock rate on-board reduces the required logic by
> a factor of four for my application.
>  

   I will not comment on Altera, but you definitely can do this in
Xilinx XC4000XL.

I recently designed, built, and demonstrated a working copy of a
complete frequency counter in an XC4002XL-09 that counts up to 420 MHz,
admittedly without using any global clocks.

Icc for the whole counter, including time-base and 6-digit LCD display,
at 100 MHz input frequency is less than 10 mA.
We have looked at ( but not completed yet ) the design of a 155-MHz
multi-channel demultiplexer,  say eight independent clock and data
inputs, each to be reduced to a more manageable 39 MHz . There is no
doubt that it will meet worst-case speed requirements.
The beauty of segmented-routing FPGAs is that you can run small sections
extremely fast without causing problems and power consumption all over
the chip.

Peter Alfke, Xilinx Applications

Article: 10128
Subject: Re: Xilinx Serial Proms
From: "Michael W. Ellis" <in@the.text>
Date: Tue, 28 Apr 1998 16:31:43 -0500
Links: << >>  << T >>  << A >>
Hal Murray wrote in message <6i2ldd$gou@src-news.pa.dec.com>...
>
>Yes, but...  Is there a location that corresponds
>to the flip-reset-ploarity bit and is it documented?
>[if so, where]
>
>

There are specific locations for each size PROM.  For the 17128, the
locations are 0x4000 - 0x4003.  You either fill these locations with 0x00 or
0xff to specify polarity.  From the top of my head, 0x00 corresponds to
RESET (low active) / OE (high active).  The following line may be added to
the MCS file to force these locations low:

:0440000000000000BC

But you still have to manually do this, one way or the other.  Xilinx
ignores this problem unless you are using their programmer.  If they have
addressed it, I have completely missed their solution.

--
"PITCHERS.BAT found: delete DH.SYS? (Y/y)"
Michael Ellis
first initial last name at pesa dot you know what



Article: 10129
Subject: Re: FPGA input data rate limitations?
From: Douglas Clayton <dclayton@fore.com>
Date: Tue, 28 Apr 1998 17:41:02 -0400
Links: << >>  << T >>  << A >>
staylor@dspsystems.com wrote:

<snip>

> You may also find that having two cloks like that causes a problem. If the
> data is ever to be passed between them you would be better off to just use the
> faster clock and disable the slower registers every other clock cycle. The
> logic required to pass data between to clocks of unknown phase, and your will
> be regardless of what precautions you take, is fairly complex compared to
> using a single flip flop set to toggle as a clock enable to registers running
> fast.
> 

I am curious why you say two clocks will necessarily be out of phase. To
interface to the asynchronous SRAMs I will use, I intended to use a
doubled clock to generate a latched WE signal to avoid the delay
problems discussed on another thread. Since some standard clock drivers
create a doubled clock automatically, I had planned on using that. Will
those clocks drift with respect to each other over time?

Douglas Clayton

-- 
Douglas_Clayton@fore.com                   FORE Systems
hardware-engineer-in-training              I don't speak for FORE.
Article: 10130
Subject: [Q] Cheap Xilinx Proto Boards
From: zblazek@kasami.UVic.CA (Zeljko Blazek)
Date: 28 Apr 1998 21:53:10 GMT
Links: << >>  << T >>  << A >>

Hi everybody,

I am interested in getting some information/opinions on prototyping
boards for Xilinx chips.

I was looking at getting a cheap prototyping board for a Xilinx XC4010PC84 
FPGA.  From the Xilinx web page, I have found two companies that produce 
what appear to be suitable boards:

 1) APS-X84 FPGA Test Board from Associated Professional Systems (APS)

 2) XS40 Prototyping Board from X Engineering Software Systems (XESS)


My minimum requirements are a standalone board with a socket for the Xilinx 
chip, a socket for a serial PROM (although I would also be happy with a 
parallel EPROM) and access to some of the I/O pins on the Xilinx chip.  Both 
products offer a lot more than my minimum requirements.

I have tried to read most of the documentation that is given by the
respective companies.  Some of my remaining questions are: 

 - How easy is it to get up and running with the boards.  They both
   appear to come with custom download S/W.

 - Has anybody had any bad (or good) experiences with either of the
   boards.

 - What are typical delivery/shipping times for the boards.  Do they
   arrive when expected or are there delays.

 - Are the boards fairly rugged, for example, being able to hold out 
   well under the physical abuse of a typical university environment.
   (assuming of course that noboby blows the chips up)

 - Any other information related to the two boards, or any other cheap
   boards that you know of, would also be useful.  I am somewhat of a 
   novice in this area and so don't really know what are the right 
   questions to ask.
   

I also have a related question concerning S/W tools.  My development
software is running on a workstation (Sun Solaris).  Can I generate 
a configuration file on my workstation, copy it to my PC, and then 
download it to the card, or do I need to do some tweaking of the 
configuration file.  I am using the XactStep tools (in order to
be able to use the older chips).


Thanks,

Zeljko

Article: 10131
Subject: High Speed FPGAs??
From: tom karabinas <tom.karabinas@eng.sun.com>
Date: Tue, 28 Apr 1998 15:05:20 -0700
Links: << >>  << T >>  << A >>
Anyone have luck doing a 150MHz design using an FPGA??

Any suggestions on which FPGA might do the job?

QuickLogic seems to have fast parts.  Any comments on these parts?

Thanks for your input,

Tom

---------------------------------------
Tom Karabinas
ASIC Design Manager
Sun Microsystems Computer Corporation
email:  tom.karabinas@eng.sun.com
Article: 10132
Subject: Re: [Q] Cheap Xilinx Proto Boards
From: msimon@tefbbs.com
Date: Tue, 28 Apr 1998 22:34:59 GMT
Links: << >>  << T >>  << A >>
The output file is Intel Hex. Very easy to load.  The Xilinx people
will give you the format if you want it. 

All EPROM programmers accept Intel Hex. 

Simon
----------------------------------------------------------------------------------------------------------------------------------------------

zblazek@kasami.UVic.CA (Zeljko  Blazek) wrote:

>
>Hi everybody,
>
>I am interested in getting some information/opinions on prototyping
>boards for Xilinx chips.
>
>I was looking at getting a cheap prototyping board for a Xilinx XC4010PC84 
>FPGA.  From the Xilinx web page, I have found two companies that produce 
>what appear to be suitable boards:
>
> 1) APS-X84 FPGA Test Board from Associated Professional Systems (APS)
>
> 2) XS40 Prototyping Board from X Engineering Software Systems (XESS)
>
>
>My minimum requirements are a standalone board with a socket for the Xilinx 
>chip, a socket for a serial PROM (although I would also be happy with a 
>parallel EPROM) and access to some of the I/O pins on the Xilinx chip.  Both 
>products offer a lot more than my minimum requirements.
>
>I have tried to read most of the documentation that is given by the
>respective companies.  Some of my remaining questions are: 
>
> - How easy is it to get up and running with the boards.  They both
>   appear to come with custom download S/W.
>
> - Has anybody had any bad (or good) experiences with either of the
>   boards.
>
> - What are typical delivery/shipping times for the boards.  Do they
>   arrive when expected or are there delays.
>
> - Are the boards fairly rugged, for example, being able to hold out 
>   well under the physical abuse of a typical university environment.
>   (assuming of course that noboby blows the chips up)
>
> - Any other information related to the two boards, or any other cheap
>   boards that you know of, would also be useful.  I am somewhat of a 
>   novice in this area and so don't really know what are the right 
>   questions to ask.
>   
>
>I also have a related question concerning S/W tools.  My development
>software is running on a workstation (Sun Solaris).  Can I generate 
>a configuration file on my workstation, copy it to my PC, and then 
>download it to the card, or do I need to do some tweaking of the 
>configuration file.  I am using the XactStep tools (in order to
>be able to use the older chips).
>
>
>Thanks,
>
>Zeljko
>

Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.
Article: 10133
Subject: Re: [Q] Cheap Xilinx Proto Boards
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 28 Apr 1998 20:45:51 -0700
Links: << >>  << T >>  << A >>

Zeljko Blazek wrote in message <6i5j46$1heo$1@uvaix7e1.comp.UVic.CA>...
>
[snip]
>
> - Any other information related to the two boards, or any other cheap
>   boards that you know of, would also be useful.  I am somewhat of a
>   novice in this area and so don't really know what are the right
>   questions to ask.
[snip]

You seemed to have found the two simplest boards that I know of.  The
Programmable Logic Jump Station maintains a fairly comprehensive list of
available boards at http://www.optimagic.com/boards.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 10134
Subject: How to implement a UART use FPGA with less cells.
From: channing-wen@usa.net (Channing Wen)
Date: Wed, 29 Apr 1998 14:58:37 +0800
Links: << >>  << T >>  << A >>
As Title.
Article: 10135
Subject: Re: FPGA input data rate limitations?
From: staylor@dspsystems.com
Date: Wed, 29 Apr 1998 01:18:28 -0600
Links: << >>  << T >>  << A >>
In article <35464CEE.6BC2@fore.com>,
  Douglas Clayton <dclayton@fore.com> wrote:
>
> I am curious why you say two clocks will necessarily be out of phase. To
> interface to the asynchronous SRAMs I will use, I intended to use a
> doubled clock to generate a latched WE signal to avoid the delay
> problems discussed on another thread. Since some standard clock drivers
> create a doubled clock automatically, I had planned on using that. Will
> those clocks drift with respect to each other over time?
>

Douglas,

The clocks will only drift if the source of the clocks drift. The problem will
be that the delays in the FPGA may not be symetrical. Since you won't know
internally which leads, even being able to externally alter the phase won't
help. Why not just use a flip/flop to cause the slow registers to only update
every other clock cycle? That way your entire design is synchronous to a
single clock. Besides, simulation is far more complex, if even possible with
two clocks if you pass data between them. I recall getting message to that
effect when I tried it.

You can run at any speed you want by having clock enables divided further.
Your design will take more power and generate more heat, but not enough to
make it worth the hassle two clocks will cause.

Scott Taylor - DSP Fibre Channel Systems

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10136
Subject: Re: How to implement a UART use FPGA with less cells.
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Wed, 29 Apr 1998 20:23:57 +1200
Links: << >>  << T >>  << A >>
Channing Wen wrote:
> 
> As Title.

Less cells than what ?

There was a trick Intel used, on the C51, which made use of an
extra BIT on Shifter length, rather than a separate 4 Bit State separate
counter -
On TX, this bit is loaded H, L's are shifted IN, and when ALL bits are
Lo, you have finished ( and done the stop bit )

- jg


-- 
======= Manufacturers of Serious Design Tools for uC and PLD  =========
= Specialists in Development tools for C51 cored controllers
= Leaders in Rapid Application Development SW for C51 uC
= Ask for our Controller & Tools selector Guides
= mailto:DesignTools@xtra.co.nz  Subject : Selc51Tools


Article: 10137
Subject: Re: Xilinx Serial Proms
From: z80@ds2.com (Peter)
Date: Wed, 29 Apr 1998 09:11:24 GMT
Links: << >>  << T >>  << A >>

>RESET (low active) / OE (high active).  The following line may be added to
>the MCS file to force these locations low:
>
>:0440000000000000BC

Very smart! I completely forgot one *should* be able to simply add a
line, with an arbitrary (but valid) load address, to an intel hex
file. One just hopes that the hex loader code of whatever is reading
the file does it properly...


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10138
Subject: Re: FPGA input data rate limitations?
From: z80@ds2.com (Peter)
Date: Wed, 29 Apr 1998 09:11:25 GMT
Links: << >>  << T >>  << A >>

>I recently designed, built, and demonstrated a working copy of a
>complete frequency counter in an XC4002XL-09 that counts up to 420 MHz,
>admittedly without using any global clocks.

Peter,

Did you use a ripple counter to achieve this ?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10139
Subject: Re: Make a delay in Xilinx FPGAs (Help)?
From: nayak@cromp.ernet.in
Date: Wed, 29 Apr 1998 04:00:46 -0600
Links: << >>  << T >>  << A >>


> >Hi,
> >
> >I am working on an XC4025E FPGA with Synopsys (UNIX version).
> >
> >I would like to write some data in a SRAM at each edge of my clock, and
> >for this I must delayed my Write Enable signal from 4 or 5 ns?
> >
> >Could you give me some ideas to introduce a delay in Xilinx FPGA?
> >Is it possible to use a clock buffer (BUFGS) on my Write Enable signal
> >to do this?


Hi!

We had faced a similar problem when we wanted to do perform successive RD/WRs.
We had used the CLK as the CE to the SRAM to get it working. But I'm sure your
problem would have been solved by ORing the WE with the CLK as suggested by
someone earlier.

Bye,

Neeraj Nayak.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10140
Subject: Re: Enforcing Clock Enable Connection in Synthesis
From: "Tom Meagher" <tomm@icshou.com>
Date: Wed, 29 Apr 1998 08:54:30 -0500
Links: << >>  << T >>  << A >>
Scott,
Referring to the Altera data book (or "dsf10K.pdf" file) I interpret page 35 a
little differently. Figure 6 implies that the ENA input into the register is
configurably shared with the DATA1 input to the LUT, implying the existence of a
separate, high-speed clock enable path in the primitive architecture.
(Otherwise, why even bother with a clock enable at all, eh?)

Indeed, my Altera FAE, Steve Kliman, confirms the intent of this as being a
high-speed clock gate, independently of the LUT.  The bad news, as you correctly
point out, is that you are then reduced to a 3 input LUT.

With respect to AHDL, I agree.  In fact we have some large MAX9000 series
designs in AHDL, where we instantiate DFFE's and connect the .ENA inputs up to a
sub-clock pulse train.  One loses this with a behavioural VHDL description.

With regards to scrutinizing the .RPT file:  This becomes extremely tedious very
quickly because the names get so badly "spaghettied" and lost almost
immediately.  In fact, even though it is yet another level farther away from the
actual device, the .VHO file has more naming information that the .RPT file
does, and the DFFE connections are easier to follow (although relating stuff
back to the source code is still non-trivial).  But, the answer is, yes, the ENA
pins to the DFFE's are driven combinatorially.

I suppose the ENA input is used by the synthesis tool to take advantage of the
implied feedback from the output, and does indeed save a level of logic.
Unfortunately, this precludes it's use as a clock qualifier.

There is sort of a Catch-22 effect, though, isn't there?  I mean, I want a
dedicated clock enable because the logic is too slow to settle in one clock
cycle, but is the logic too slow because of the extra levels of logic incurred
by the clock enable?  (In fact, though, in this application I do need to use the
clock enable to match the core state machine logic to the data rate anyway).

The synchronous reset is tied off to '0' at a higher level for the reasons you
mention.

Best Regards,
Tom Meagher (last name pronounced "mar", don't ask why...)
tomm@icshou.com




staylor@dspsystems.com wrote in message <6i3v6o$q18$1@nnrp1.dejanews.com>...
>In article <6i2aug$f4s$1@supernews.com>,
>  "Tom Meagher" <tomm@icshou.com> wrote:
>>
>> We have something on the order of 10,000 lines of VHDL, which synthesizes
>> down to about 85-90% of an Altera 10K70 (the -3 speed grade is our target
>> part).  Now, it is neither possible nor necessary for the entire design to
>> meet the 25 MHz system clock requirement after place and route.  This is
>> because the most complex stuff only needs to process data at half system
>> clock speed.
>>
>> Therefore, we partition off the slow-speed blocks and desire to connect the
>> "CE" inputs to all the "DFFE" flip flops to a 12.5 MHz (sys clock divided by
>> 2) clock enable signal.
>
>Tom,
>
>A couple of points. First, the 10k logic elements use one of the 4 lookup
>table inputs for the clock enable (1998 Databook page 35). The I/O elements
>have true clock enables from global signals (1998 databook page 49), but the
>logic elements do not. Since you thyen only have 3 LUT inputs, you are more
>likely to have cascaded logic elements feeding the DFFEs. A non-global reset
>or preset takes another LUT input if you are using it. Under certain
>conditions global presets take a LUT input. Using both clear and preset always
>uses a LUT input. Having a synchronous load capability also uses a LUT input.
>The carry output uses one also. Some combinations are mutually exclusive.
>
>In effect the clock enable for a 10k logic element is really just a 4th input
>to the lookup table which would then imply a fifth [not shown] input, feedback
>from the Q output of the DFF. I/O elements can only have a single signal feed
>the D input though so that probably won't help. Since a logic element clock
>enable isn't global, there are routing delays associated with it. Using
>schematic entry wouldn't help. You are already telling Maxplus 2 to use the
>clock enable, you are just expecting too much from it.
>
>You need to look in the .RPT file and see how the DFFEs are synthesized. My
>opinion is that this is a case where AHDL would give you better results. Does
>VHDL retain the symbolic names in the .RPT file? (AHDL does if you do not use
>funtions) If you have some high speed signals and some that are static or
>lower speed you can cause the slower ones to have the longer delay paths by
>coding the preceeding logic cells yourself.
>
>I have been asking Altera to provide a way to do this at a higher level for
>several years, but so far nothing.
>
>Scott Taylor - DSP Fibre Channel Systems
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/   Now offering spam-free web-based newsreading


Article: 10141
Subject: Re: Enforcing Clock Enable Connection in Synthesis
From: "Tom Meagher" <tomm@icshou.com>
Date: Wed, 29 Apr 1998 09:05:17 -0500
Links: << >>  << T >>  << A >>
Scott,
100MHz makes me both jealous and depressed!  I would be happy to get my protocol
parser and TDMA dual ported RAM's to work at 25MHz (sigh).  Individual
sub-components seem to be OK, but when everything goes together into a 10K70
device that is much over 65% full, then look out, stuff never seems to fly as
fast as one thinks it should...

Tom Meagher


staylor@dspsystems.com wrote in message <6i52v4$pm8$1@nnrp1.dejanews.com>...
>In article <6i2aug$f4s$1@supernews.com>#1/1,
>
>I read your message again this morning. At 12.5MHz and 25MHz what you are
>doing should be a breeze. I do it at 60-100MHz frequently, even with slower
>speed grades (*see note). Look at your .RPT file and trace one of the logic
>elements that don't work. You could even post the relavent parts. You will
>probably find that the clock enable is going through several layers of
>combinatorial logic, and/or the rest of the data to the LUT is also.
>
>* Note: The speed listed in the Altera databook is for 16 bit synchronous
>counters. No tricks like lookahead carries are used to achieve those numbers.
>I have several times gotten higher speeds, validated by their simulator and
>timing analyser, by quite a bit.
>
>Scott Taylor - DSP Fibre Channel Systems
>



Article: 10142
Subject: Re: FPGA input data rate limitations?
From: Douglas Clayton <dclayton@fore.com>
Date: Wed, 29 Apr 1998 11:15:17 -0400
Links: << >>  << T >>  << A >>
staylor@dspsystems.com wrote:
> 
> Douglas,
> 
> The clocks will only drift if the source of the clocks drift. The problem will
> be that the delays in the FPGA may not be symetrical. Since you won't know
> internally which leads, even being able to externally alter the phase won't
> help. Why not just use a flip/flop to cause the slow registers to only update
> every other clock cycle? That way your entire design is synchronous to a
> single clock. Besides, simulation is far more complex, if even possible with
> two clocks if you pass data between them. I recall getting message to that
> effect when I tried it.


I'm afraid I still don't understand. What I had intended to do was have
one clock as an input to a clock driver which would then output several
versions of that clock as well as a clockx2 signal. My question is,
aren't those clocks guaranteed to be within some small variation in
phase?

This doubled clock will not even be in my main FPGA, but in a smaller
(and faster) controller CPLD, used solely to generate a low WE. The fact
that it is in a register rather than being an AND'd clock means that the
WE will go high much sooner after the clock--meaning the data hold issue
will be less important.


clock             +-----------+           +------
(20MHz)   ________|           |___________|

write    -----------+                       +------
(clocked with clock)|_______________________|


clockx2   --+     +-----+     +-----+     +-----
(40MHz)     |_____|     |_____|     |_____|
 
/WE      ------------------------+          +----------
(clocked with clockx2)           |__________|


As you can see, I am relying on the fact that both clocks are in phase.
For my 20MHz clock, this gives me a WE signal of 25 ns plus a hold time
of 5-7 ns (certainly faster than my FPGA). If I just AND'd the clock
with the write signal, I would get delays more like 15 ns, too long for
me to guarantee the address/data will be stable. 

Is there something I am missing?  (Maybe I should just use ZBT
synchronous SRAMs. :)

Douglas Clayton

-- 
Douglas_Clayton@fore.com               FORE Systems
Hardware Engineer-in-training          I don't speak for FORE.
Article: 10143
Subject: Re: High Speed FPGAs??
From: michael.lee@actel.com
Date: Wed, 29 Apr 1998 09:49:20 -0600
Links: << >>  << T >>  << A >>
Tom,
You should check out Actel's new SX family of FPGAs.  They have a 4.0 nS
clk-out and a 320MHz maximum clock frequency for the fastest device.  You
should visit our site at www.actel.com and you can download the datasheet.
You can also download a free version of our Designer Lite software that
allows you to do designs up to 16K gates.

Hope this helps!

Regards,
Michael Lee
ActelCorp
In article <354652A0.EDC111E@eng.sun.com>,
  tom karabinas <tom.karabinas@eng.sun.com> wrote:
>
> Anyone have luck doing a 150MHz design using an FPGA??
>
> Any suggestions on which FPGA might do the job?
>
> QuickLogic seems to have fast parts.  Any comments on these parts?
>
> Thanks for your input,
>
> Tom
>
> ---------------------------------------
> Tom Karabinas
> ASIC Design Manager
> Sun Microsystems Computer Corporation
> email:  tom.karabinas@eng.sun.com
>


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Article: 10144
Subject: Re: High Speed FPGAs??
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Wed, 29 Apr 1998 18:16:16 GMT
Links: << >>  << T >>  << A >>
Have you looked at DynaChip ??

They have ECL FPGA's.

Bill Seiler
DIVX


Article: 10145
Subject: USB infos ( Hardware - Software - Driver ) at ...
From: Pepito <jpbelin@myrica.com>
Date: Wed, 29 Apr 1998 19:46:48 +0100
Links: << >>  << T >>  << A >>
Hello,
As you , i was looking for some USB infos: hardware, software, drivers.
Please , read them at my web page :

http://www.angelfire.com/ok/jpbelin/Top_page.html

Hope this will help.
Pepito


Article: 10146
Subject: Re: Why Altera & Cypress Software Clashes (was: VHDL compiler differences?)
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Wed, 29 Apr 1998 19:22:09 GMT
Links: << >>  << T >>  << A >>
On Sat, 25 Apr 98 20:46:25 GMT, Steve@s-deweynospam.demon.co.uk (Steve
Dewey) wrote:

>Err... Let me clarify: I have not attempted to port VHDL code developed 
>in Altera's Maxplus to Cypress' Warp. I was asking whether it would be feasible 
>or not. 

Theoretically yes, VHDL is SUPPOSED to be a standard, but in practice,
this is extremely unlikely. Vendors sometimes use odd libraries or
constructs, so when you move your code to an independent tool you may
find that it won't compile first time.

>For a given piece of VHDL code, do the mega-bucks tools, e.g. Synopsys, 
>Exemplar, Synplicity actually implement it using fewer chip resources
>than the standard Altera tools ? I understand that the implementation of VHDL 

Mega-bucks? I guess that depends on what your engineering teams' time
costs you, what being late to market will cost you, and what having to
use a bigger faster part will cost you in production.

However wrt those three vendors, the answer is YES they will produce
smaller, and faster results in many cases.

If they didn't do things better than the vendor's tools then nobody
would be buying them (would they?).

Of course, if the design is 'small', then you may not necessarily need
all the horse-power on offer from the third party vendors to produce
an acceptable result.

>may be more complete, and the software able to target multiple vendors
>(but only with the vendors back-end tools...).

No problem there then.

If you have vendor independent tools, no FPGA vendor worth dealing
with is going to give you an argument about back-end tools when you
have a live project. It simply isn't a gamble they can afford to take,
because you can just go elsewhere.

When I was selling Lucent, we used to give away evals (no bitstream)
to anyone with 3rd party synthesis tools. If the silicon was right for
the particular design metrics, the deal was simple: First order for
silicon means the bitstream license turned on for free.

I can't guarantee that a disti/rep might not try to squeeze you for
the tools, but a quick scream at the local sales office that you'll
just go use brand X instead should put that right. Of course, if the
potential revenue stream is considered too small, they might not want
to play.

Look at QuickLogic, they don't muck about. Their entire back end tools
are available for free, no strings as far as I'm aware.

<snip>

Stuart
Article: 10147
Subject: Re: Enforcing Clock Enable Connection in Synthesis
From: staylor@dspsystems.com
Date: Wed, 29 Apr 1998 13:23:34 -0600
Links: << >>  << T >>  << A >>
In article <6i7cbr$68q$1@supernews.com>#1/1,
  "Tom Meagher" <tomm@icshou.com> wrote:
>
> Scott,
> 100MHz makes me both jealous and depressed!  I would be happy to get my
> protocol parser and TDMA dual ported RAM's to work at 25MHz (sigh).
> Individual sub-components seem to be OK, but when everything goes together
> into a 10K70 device that is much over 65% full, then look out, stuff never
> seems to fly as fast as one thinks it should...
>

Tom,

My off the cuff response would be that is because you are writing high level
syntax and expecting the compiler and fitter to know the difference between
critical and non-critical signals. If you have 10 inputs and only 2 are
critical, how is the compiler/fitter to know which ones are critical.

I don't know how true it still is, but Altera used to use alphabetical
ordering. Try placing A-Z on the front of critical signal names to see if that
helps. Since symbolic names are lost early in partitioned projects, I suspect
the same is true of VHDL. In that case the names will have little or no
effect.

VHDL to me is an improvement in the wrong direction. People want portability,
and they want performance too. I think VHDL is a long way from being able to
offer both. Pick your vendor, even if it is on a project by project basis and
write the code to fit the architecture. You will get higher performance and
more logic in a smaller lower speed grade device. Since I commonly run as fast
as the fastest speed grade will allow, I rarely have that option. While larger
devices can usually be gotten in the same speed grades, routing delays,
especially when soft buffers are inserted, make them appear slower.

Scott Taylor - DSP Fibre Channel Systems

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Article: 10148
Subject: Re: Enforcing Clock Enable Connection in Synthesis
From: staylor@dspsystems.com
Date: Wed, 29 Apr 1998 13:30:21 -0600
Links: << >>  << T >>  << A >>
In article <6i7c07$16d$1@usenet11.supernews.com>#1/1,
  "Tom Meagher" <tomm@icshou.com> wrote:
>
> Scott,
> Referring to the Altera data book (or "dsf10K.pdf" file) I interpret page 35
> a little differently. Figure 6 implies that the ENA input into the register
> is configurably shared with the DATA1 input to the LUT, implying the
> existence of a separate, high-speed clock enable path in the primitive
> architecture. (Otherwise, why even bother with a clock enable at all, eh?)
>

Tom,

Please disregard my comments on e-mail. Apparently the e-mail got to me more
quickly than your post did. I have included my e-mail response. I added the
part regarding soft buffer insertion. I know this is a VHDL newsgroup, but I
think at times high level languages are a step backward.

I guess I was a little unclear. I didn't mean to imply that data1 didn't
become a clock enable, only that it still has the variable routing delays
associated with it, including soft buffer insertion delays, the same as the
other LUT inputs, compared to the I/O element that has a global clock enable
capability that does not have such variable delays. All you gain is
elimination of the LUT delays. What this means is that the setup and hold
times will not be the same across the device. You can verify this by having 5
logic elements. Place them in the four corners and the middle and use the
timing analyser to determine the maximum frequency. I could be wrong, but I
have been reading and using Altera databooks and parts for over 8 years and
have learned to read between the lines.

>> But, the answer is, yes, the ENA pins to the DFFE's are driven
combinatorially.<<

Each logic element in the combinatorial path to the clock enable adds to the
variable routing delays. That is likely to be what is causing some of your
problems. By using AHDL and doing all combinatorial fan-in manually you can
steer the highest speed signals into the shortest paths.

I personally would use an entry method that enables the report file to be
utilized. A couple of times I modularized my code and used functions. Each
time the loss of ability to use the report file outweighed the advantage. Now
I just partition the code in the file instead. That way I can still come back
later and cut and paste previous work into new designs. The files get long,
but todays editors don't seem to mind.

%************** %
% C40 Comm Port %
%************** %
code

%*********************%
% Some other function %
%*********************%
code

etc.

I think you are a living and example I commonly cite. You will spend more time
simulating and wrestling with VHDL to get it to do what you want than it would
take to just do it in AHDL. Either that, or you will end up using a faster
speed device than you really need. For a 1 or 2 application that might be the
better choice, though I find eventually I regret it for some reason or another
when I come back and have to make changes.

If you do finally get VHDL to work, every time you make a [major] change you
will have to do it all over again. Like higher level programming languages
VHDL requires interpretation to comform to specific devices and architectures.
That usually results in compromised performance. AHDL on the other hand allows
you to write code in a form that has a direct translation to the architecture.
What You See Is What You Get, WYSIWYG, assuming that is the option you select,
I always do. I say that knowing it isn't always true, at times the software
people at Altera seem to feel they know better than I what I want, even when I
select WYSIWYG. One to two years later they find they don't in fact know
better and stop interpreting, only to do it with some other feature.

Scott Taylor - DSP Fibre Channel Systems

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Article: 10149
Subject: $$$Show me the money!!!
From: cash <cling0001@aol.com>
Date: Wed, 29 Apr 1998 14:45:29 -0500
Links: << >>  << T >>  << A >>
WORK SMARTER, NOT HARDER

ARE YOU READY TO GET $50,000 IN 5 WEEKS ON WITH JUST $6.00 ???

The fact that so many people have taken the time to post to 250
newsgroups or more should convince you that this really works!!!
BE HONEST AND FAIR and you will make money!  LOTS OF MONEY!!!
(Sure is a lot of mail though!  Heck, there’s $20.00 bucks
just in recycled paper!)

THANKS FOR READING
*******************************************************
PLEASE READ ON ABOUT SOMEONE WHO IS SUCCESSFUL AT THIS  AND
HOW TO BE SUCCESSFUL ALSO:
*******************************************************

A little while back, I was browsing these newsgroups, just like you are
now, and came across an article similar to this that said you could make

thousands of dollars within weeks with only an initial investment of
$6.00 ! So I thought," Yeah, right, this must be a scam", but like most
of
us, I was curious, so I kept reading. Anyway, it said that you
send..$1.00 to each of the 6 names and address stated in the article. 
You then place your own name and address in the bottom of the list at
#6, 
and post the article in at least 200 newsgroups.

(There are literally thousands of newsgroups)

No catch, that was it.

The main difference between this system and others is that you have a
mailing list of 6 instead of 5... This means that your average gain will

be approximately. 15 times higher!!! So after thinking it over and
talking to a few people first, I thought, what the heck, trying it is
just
like the lottery in a way, except you keep plunking down bucks after
bucks
over several weeks looking to hit the big one, only ending up with maybe
winning $50.00 after spending $75.00 in the long run.

I figured what have I got to lose except 6 stamps and $6.00, right?

Like most of us, I was a little skeptical, no make that really skeptical

and a little worried about the legal aspects of it all. So I checked it
out with the U.S. Post Office (1-800-725-2161) and they confirmed that
it is

indeed legal!

Then I cracked open the cookie jar and invested the measly $6.00........

Well GUESS WHAT!!!...I prayed and sweated for what I thought was an
eternity but low and behold... within 7 days, I started getting money in

the
mail!

I was shocked! Amused even! I still figured it would end soon and didn't

give it another thought, maybe I could buy another computer with the
little bit of money, if that.

But the money just kept coming in. In my first week, I made about $20.00

to $30.00 dollars. By the end of the second week I had made a total of
over
$1,000.00!!!!!! In the third week I had over $10,000.00 and it's still
growing. This is now my fourth week and I have made a total of just over

$42,000.00 and it's still coming in rapidly.......

It's certainly worth $6.00, and 6 stamps, I spent more than that on the
lottery!!

Let me tell you how this works and most importantly, why it
works....also, make sure you print a copy of this article NOW, so you
can get the
information off of it as you need it. The process is very simple and
consists of 3 easy steps:

STEP 1: Get 6 separate pieces of paper and write the following on each
piece of paper:
 "PLEASE PUT ME ON YOUR MAILING LIST."
  "$1.00 - US DOLLAR PROCESSING FEE ENCLOSED
Now get 6 US $1.00
bills (or equivalent in your local currency) and place ONE inside EACH
of the 6 pieces of paper so the bill will not be seen through the
envelope to prevent thievery. Next, place one paper in each of the 6
envelopes
and seal them. You should now have 6 sealed envelopes, each with a piece
of
paper stating the above phrase, your name and address, and a $1.00 bill.

What you are doing is creating a service by this. THIS IS ABSOLUTELY
LEGAL!

Mail the 6 envelopes to the following addresses:


#1
G A Gram
104 E. Fairview Ave #238
Meridian, ID  83642

#2
Daniel M. P.
P.O. Box 3001
Reston, VA  201701  USA

#3
P Ward
740 E. Republic
Salina, KS  67401   USA

#4
Michael
12302 E Appaloosa PL
Scottsdale, AZ  85259


#5
S. Perkins
14001 Saint Leo Ct.
Orlando, FL 32826

#6
Patrick
2100 Rebsamen Park Rd. #412
Little Rock, AR  72202

STEP 2: Now take the #1 name off the list that you see above, move the
other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as
number 6 on the list.

STEP 3: Change anything you need to, but try to keep this article as
close to original as possible. Now, post your amended article to at
least 200 newsgroups. (I think there is close to 34,000 groups) All you
need is 200, but remember, the more you post, the more money you make!

Don't know HOW to post in the newsgroups?

Well do exactly the following:


-----------------------------------------------

 DIRECTIONS - HOW TO POST TO NEWSGROUPS:

-----------------------------------------------

Step 1. You do not need to re-type this entire letter to do your own
posting, simply put your cursor at the beginning of this letter and
click and hold down your mouse button. While continuing to hold down the
mouse
button, drag your cursor to the bottom of this document and over to just
after the last character and release the mouse button. At this point the
entire letter should be highlighted. Then, from the 'edit' pull down
menu at the top of your screen select 'copy'. This will copy the entire
letter into the computers memory.

Step 2. Open a blank 'notepad' file and place your cursor at the top of
the blank page. From the 'edit' pull down menu select 'paste'. This will
paste a copy of the letter into notepad so that you can add your name to
the list.

Remember to eliminate the #1 position, move everyone up a spot
(re-number everyone else’s positions) and add yourself in as #6.

Step 3. Save your new notepad file as a .txt file. If you want to do
your postings in different sittings, you'll always have this file to go
back to.


-----------------------------------

  FOR NETSCAPE USERS:

-----------------------------------

Step 4. Within the Netscape program, go to the pull-down window entitled

'Window' select 'NetscapeNews'. Then from the pull down menu 'Options',
select 'Show all Newsgroups'. After a few moments a list of all the
newsgroups on your server will show up. Click on any newsgroup you
desire.  From within this newsgroup, click on the 'TO NEWS' button,
which should
be in the top left corner of the newsgroups page. This will bring up a
message box.

Step 5. Fill in the Subject. This will be the header that everyone sees
as they scroll through the list of postings in a particular group.

Step 6. Highlight the entire contents of your .txt file and copy them
using the same technique as before. Go back to the newsgroup 'TO NEWS'
posting
you are creating and paste the letter into the body of your posting.

Step 7. Hit the 'Send' Button in the upper left corner. You're done with
your first one! Congratulations...


----------------------------------------

  INTERNET EXPLORER USERS:

----------------------------------------

Step 4. Go to newsgroups and select 'Post an Article'.
Step 5. Fill in the subject.
Step 6. Same as #6 above
Step 7. Hit the 'Post' button.



----------------------------------------

THAT'S IT! All you have to do is jump to different newsgroups and post
away, after you get the hang of it, it will take about 30 seconds for
each
newsgroup!

**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL
MAKE!!
BUT YOU HAVE TO POST A MINIMUM OF 200**

That's it!

You will begin receiving money from around the world within day's!

You may eventually want to rent a P.O. Box due to the large amount of
mail you receive.

If you wish to stay anonymous, you can invent a name to use, as long as
the postman will deliver it.

              *JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.*

Now the WHY part:

Out of 200 postings, say I receive only 5 replies (a very low example).

So then I made $5.00 with my name at #6 on the letter. Now, each of the
5 persons who just sent me $1.00 make the MINIMUM 200 postings, each
with
my name at #5 and only 5 persons respond to each of the original 5, that
is
another $25.00 for me.  Now those 25 each make 200 MINIMUM posts with my 
name at #4 and only 5 replies each, I will bring in an additional
$125.00! 
Now, those 125 persons turn around and post the MINIMUM 200 with my name
at 
#3 and only receive 5 replies each, I will make an additional $626.00!

OK, now here is the fun part, each of those 625 persons post a MINIMUM
200 letters with my name at #2 and they each only receive 5 replies,
that
just made me $3,125.00!!!

Those 3,125 persons will all deliver this message to 200 newsgroups with
my name at #1 and if still 5 persons per 200 newsgroups react, I will
receive $15,625,00! With an original investment of only $6.00!

AMAZING!.....

And as I said, 5 responses is actually VERY LOW! Average is probably 20
to 30! So lets put those figures at just 15 responses per person Here is
what you will make:

at #6 $15.00
at #5 $225.00
at #4 $3,375.00
at #3 $50,625.00
at #2 $759,375.00
at #1 $11,390,625.00

When your name is no longer on the list, you just take the latest
posting in the newsgroups and send out another $6.00 to names on the
list,
putting your name at number 6 again. And start posting again.

The thing to remember is, that thousands of people all over the world
are joining the Internet and reading these articles everyday, JUST LIKE
YOU
are now!!

So can you afford $6.00 and see if it really works??

I think so...

People have said, "what if the plan is played out and no one sends you
the money ? So what! What are the chances of that happening when there
are
tons of new, honest users and new honest people who are joining the
Internet
and newsgroups everyday and are willing to give it a try?

Estimates are at 20,000 to 50,000 new users, every day, with thousands
of those joining the actual Internet.


        Remember, play FAIRLY and HONESTLY and this will work.

           **********You just have to be honest.**********


Make sure you print this article out RIGHT NOW and also, try to keep a
list of everyone that sends you money and always keep an eye on the
newsgroups to make sure everyone is playing fairly.

                Remember, HONESTY IS THE BEST POLICY.

You don't need to cheat the basic idea to make the money!!

GOOD LUCK to all and please play fairly and reap the huge rewards from
this, which is tons of extra CASH....By the way, I not only bought a new
computer, I'm in the process of buying a computer company.

Also remember, with your new found wealth, try to set up places for the
needy and those that need caring and food and love..... Don't just buy
cars and boats and houses and be greedy. This honestly and truly can
make
you independently wealthy.


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