Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 9700

Article: 9700
Subject: Re: Digital PLL's or Manual Synching?
From: Daniel Alley <dana@xetron.com>
Date: Tue, 31 Mar 1998 13:42:42 -0500
Links: << >>  << T >>  << A >>
If you allow for oscillators external to the FPGA, there are many
available.  Digikey shows DIP part at 80 MHz for $10 range (pg. 230).
If you build your own xtal osc, use a third overtone crystal where
third harmonic is the signal of interest.  Me - I'd use the stock
oscillator and move on.  Make sure there is a decoupling cap on the 
power pin and a 51 ohm series res. on the signal line to avoid
ringing/emi problems.


Stephen Phillipson wrote:
> 
> Martin Neilan wrote:
> >
> > Hi everyone,
> >
> > I have a need to implement a Digital Phase Locked Loop on and FPGA using
> > V-System as the VHDL compiler and Xilinx as the synthesis software. If
> > it is not possible, I will need to look at other ways to determine a
> > suitable clock for an incoming serial stream of data (of undetermined
> > frequency) and keep this clock in sync.
> >
> > However, in order to do this the second way (without a DPLL) I would
> > require a quartz clock crystal running at preferably greater than 80
> > MHz. Does such a thing exist? If not, is there a way of creating a
> > faster clock using some clever coding from a slower quartz crystal?
> > eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I
> > have a feeling this might be possible but has anyone else done it?
> >
> > Any suggestions or help is greatly appreciated!
> >
> > Kind Regards,
> > Steve Phillipson
> > - A confused undergraduate engineer!
> 
> Oopps! Had my details set wrong in Netscape :(
> Correct details:
> 
> Stephen Phillipson (hslcomp@iinet.net.au)
> 
> Sorry!
Article: 9701
Subject: Re: XactStep6 - The cure for a dongle
From: staylor@dspsystems.com
Date: Tue, 31 Mar 1998 14:08:59 -0600
Links: << >>  << T >>  << A >>
In article <351FF25A.BBC9DBE0@eng.efi.com>,
  Gareth Baron <gareth.baron@eng.efi.com> wrote:
>
> IMO, the removal of the dongle license is irrelevant.  What can you use
> the Xilinx s/w for other than developing Xilinx FPGAs ?  Xilinx can make
> good revenues from the silicon itself.  I have always mentioned to the EDA
> companies this fact.  What are they selling, Silicon or Software ?
>
> I'm not against using dongles, but I do disagree with the maintainence
> deals that go along with them.  You are tied in forever to buying their
> "Upgrades" (especially when they re-release new silicon!).

I agree. I have talked with Altera about this many times. It is not until more
people refuse to pay a 15% annual maintenance that things will change. I am
willing to pay for added features [that I want], but I see no reason I should
pay more to add the ability to use parts I am going to buy from them anyway.

Scott Taylor, DSP Systems Inc.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9702
Subject: Re: New radix-4 CORDIC for computing sine and cosine
From: mpercy@planetall.com
Date: Tue, 31 Mar 1998 14:29:26 -0600
Links: << >>  << T >>  << A >>
In article <3521143D.30B7@e-technik.uni-rostock.de>,
  Hagen Ploog <hp@e-technik.uni-rostock.de> wrote:
>
> Andrew V. Nesterov wrote:
> >
> > In article <351813B4.9DE25395@computer.org>, Vitit Kantabutra
<vkantabu@computer.org> wrote:
> > > Thanks.  Yes, I've written a paper about it and submitted it to ICCD '98
a few
> > > days ago.  I'll send you a copy via email.  I just didn't want to send a
paper
> > > to a newsgroup.
> > >
> >         I'd also like to take a look at it. Please send it to me too.
> > Thanks,
> >
> > --Andrew
>
> Please send me a version of your paper too.
>

Me too.  Might as well post it now, or at least put it somewhere we can get to
it?  Or else you'll end sending to it dozens of people.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9703
Subject: Altera Bitblaster or Byteblaster??
From: Felip Vicedo Roman <fvicedo@eug.upv.es>
Date: Tue, 31 Mar 1998 22:46:56 +0200
Links: << >>  << T >>  << A >>
I'm working in Altera FPGA's.I'm want to make a board configurable from
the computer, but I need the bitblaster or byteblaster. Somebody knows
how this devices are make?? 


Felip Vicedo Roman
feviro@eug.upv.es
Article: 9704
Subject: Re: Digital PLL's or Manual Synching?
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Wed, 01 Apr 1998 09:32:23 +1200
Links: << >>  << T >>  << A >>
Daniel Alley wrote:
> 
> If you allow for oscillators external to the FPGA, there are many
> available.  Digikey shows DIP part at 80 MHz for $10 range (pg. 230).
> If you build your own xtal osc, use a third overtone crystal where
> third harmonic is the signal of interest.  Me - I'd use the stock
> oscillator and move on.  Make sure there is a decoupling cap on the
> power pin and a 51 ohm series res. on the signal line to avoid
> ringing/emi problems.
> 
> Stephen Phillipson wrote:
> >
> > > Hi everyone,
> > >
> > > I have a need to implement a Digital Phase Locked Loop on and FPGA using
> > > V-System as the VHDL compiler and Xilinx as the synthesis software. If
> > > it is not possible, I will need to look at other ways to determine a
> > > suitable clock for an incoming serial stream of data (of undetermined
> > > frequency) and keep this clock in sync.

 Just HOW 'undetermined' is the frequency ?
All PLL designs have a catch and hold range, and this is normally kept
as small
as possible to improve noise.
 If you can swing over > 2:1, you also need to ensure you do not
harmonic lock.

For PLL info, look at 74HC4046 (vco), and 74HC297 ( digital Filter )

> > >
> > > However, in order to do this the second way (without a DPLL) I would
> > > require a quartz clock crystal running at preferably greater than 80
> > > MHz. Does such a thing exist? If not, is there a way of creating a
> > > faster clock using some clever coding from a slower quartz crystal?
> > > eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it?

Clock Doubling is reasonably simple, an XOR gate and delay line give a
pulse per
XTAL edge. 
This CAN have phase jitter, which depends on how close to 50.00% the CLK
duty
cycle is.

Going above that is harder, as you have to 'invent' time information,
and you get even more phase jitter, and become very process dependant.


If your regen CLK is low ( < 2MHz ), then a 80MHz clocked phase walking
sync
system is probably simplest, and gives reasonable noise immunity.

- jg

-- 
======= Manufacturers of Serious Design Tools for uC and PLD  =========
= Specialists in Development tools for C51 cored controllers
= Leaders in Rapid Application Development SW for C51 uC
= Ask for our Controller & Tools selector Guides
= mailto:DesignTools@xtra.co.nz  Subject : Selc51Tools

Article: 9705
Subject: Re: Floating point representation in FPGA
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 31 Mar 1998 23:30:19 -0500
Links: << >>  << T >>  << A >>
satish_me@hotmail.com wrote:
> 
> Hello,
>  I am intersted in putting designing FFT and DCT on FPGA. The same I want to
> implement just like Higher languages.Please help me how can I represent
> Floating point on FPGA.
> Thankyou for your valuable response
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/   Now offering spam-free web-based newsreading

 Satish,

While floating point processing is certainly doable in FPGAs, it comes
at a considerable cost.  A floating point macro is considerably larger
and slower than it's fixed point counterpart.  In most cases, doing your
homework will allow you to use a fixed point design and obtain better
performance, power,and device size numbers.  If you must do floating
point, you will want to look at a good text on computer arithmetic to
learn the basics.  Basically, for addition, you need to normalize one or
both inputs to get to a common exponent.  This is done with a barrel
shifter and an alu to compute the required shift.  After adding the
normalized mantissas you may need to shift again.  For multiplication,
you can add the exponents and multiply the mantissas.  again, you will
usually want to normalize after the operation.  THe shifters get
expensive in terms of routing and layers of logic.  In my practice, I do
occasionally do a flaoting point design, but I try to avoid it whenever
possible (so that the customer gets the best bang for the buck)

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance FPGA designs for digital signal
processing, computing and control applications.
Article: 9706
Subject: Re: Best solution
From: "Donna J. Wages" <donnaw@uniserve.com>
Date: 1 Apr 1998 07:15:15 GMT
Links: << >>  << T >>  << A >>
J.-

pDSP all the way.  Flexibility with compilers, cost of pDSP's are coming
down rapidly, speed will be higher for FPGA but by the time you do anything
of any complexity the next generation pDSP will have matched the speed.  I
can't speak to power it depends on your application and wich pDSP you use. 
If you choose a TMS320C54x or a Lucent 021 for GSM communication you will
have a hard time beating it from a power consumption standpoint with any
FPGA.  Other applications may give different results.

Regards,


J. Khatib <jamil.khatib@pemail.net> wrote in article
<35180577.878020@news.planet.edu>...
> Please  I want some hints and guidelines for selecting FPGA or pDSP
> for some applications and the trade-offs involved ( ie power
> consumption, speed, design flexibility ,etc)
> 
> thanks in advance
> 
Article: 9707
Subject: Re: Digital PLL's or Manual Synching?
From: z80@ds2.com (Peter)
Date: Wed, 01 Apr 1998 07:19:55 GMT
Links: << >>  << T >>  << A >>

>However, in order to do this the second way (without a DPLL) I would
>require a quartz clock crystal running at preferably greater than 80
>MHz. Does such a thing exist? If not, is there a way of creating a
>faster clock using some clever coding from a slower quartz crystal?
>eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I
>have a feeling this might be possible but has anyone else done it?

I am sure you will get a few other replies here, but you can *buy*
crystal oscillators of that sort of frequency, off the shelf. This is
a far easier option.

To generate a fast internal clock, using a DPLL, you will need a VCO
and *that* will have to run at 80MHz. You cannot have the VCO internal
to the FPGA, so you are looking at having an 80MHz signal outside the
FPGA anyway, whatever you do. 

Unless I am missing something obvious.



Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 9708
Subject: Re: XactStep6 - The cure for a dongle
From: Richard.Radix@BTinternet.com (Richard Dungan)
Date: Wed, 01 Apr 1998 08:24:18 GMT
Links: << >>  << T >>  << A >>
Zoltan Kocsi <root@127.0.0.1> wrote:

[snip loads of interesting stuff]

One of the most interesting threads for a long time.

I have to agree that ultimately the silicon vendors must decide
whether they are silicon vendors or software vendors. ISTR that the
original PALs (remember MMI?) did not start to take off properly until
PALASM was placed in the public domain.

Having said that, I am currently on software maintenance with Xilinx
and have been impressed by the helpfulness of both Xilinx and
Micro-Call (here in the UK).

I have few problems paying for maintenence / support if the service
offered is genuine, rather than an excuse for blackmail.

At least one other distributor of FPGAs here in the UK has lost my
clients' purchase order because they seem unable even to find the
reply button on their email, let alone compose a coherent answer. They
must be semi-conscious (private joke).

Richard
------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
  Email: Richard.Radix@BTinternet.com
---------------------------------------
Unsolicited Commercial Email is not welcome.
Kill filters are in operation.
Article: 9709
Subject: Re: XactStep6 - The cure for a dongle
From: David Pashley <David@fpga.demon.co.uk>
Date: Wed, 1 Apr 1998 10:48:01 +0100
Links: << >>  << T >>  << A >>
In article <3521f340.6145175@news.btinternet.com>, Richard Dungan
<Richard.Radix@BTinternet.com> writes
>Zoltan Kocsi <root@127.0.0.1> wrote:
>
>[snip loads of interesting stuff]
>
>One of the most interesting threads for a long time.
>
>I have to agree that ultimately the silicon vendors must decide
>whether they are silicon vendors or software vendors. ISTR that the
>original PALs (remember MMI?) did not start to take off properly until
>PALASM was placed in the public domain.

While in reminiscence mode, don't forget Signetics FPLAs which appeared
at about the same time, and their design tool - "H&L".

I would say that it was the appearance and adoption of the "vendor
independent" design tool ABEL (and also CUPL) in the mid-eighties that
really allowed the PLD market to expand and diversify. These allowed
users to migrate to exciting new devices like Lattice's GAL 20V8,
Altera's EP300, which would probably have been out of the question if
they had had to buy a new tool every time.

By the end of the eighties, the great majority of PLD design was
performed using vendor-independent tools. This allowed new suppliers to
encroach on AMD/MMI's and Signetics' market share.

The FPGA tool market seemed to be going the same way in '93 when NeoCAD
came along, but it was not to be.

The FPGA vendors have learnt the lessons of history, and know the
importance of the design and implementation tools in determining market
dynamics. So, IMHO, they're in the s/w business to stay.

-- 
David Pashley                 <
 ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| * The EDA Source *       <  <  <               Fax: +44 1280 700577      |
 ---------------------------  <  ------------------------------------------
Article: 9710
Subject: Re: XactStep6 - The cure for a dongle
From: z80@ds2.com (Peter)
Date: Wed, 01 Apr 1998 10:18:37 GMT
Links: << >>  << T >>  << A >>

>I agree. I have talked with Altera about this many times. It is not until more
>people refuse to pay a 15% annual maintenance that things will change.

15%? You did well! Here in the UK, I was asked to pay $1600 for annual
maintenance for XACT6, having purchased it for about $4000. Rather
more than 15%, and the other thing is that this was not many months
before Xilinx dropped XACT6 altogether...


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 9711
Subject: One time programmables
From: Joshua Schwartz <josh@gezernet.co.il>
Date: Wed, 01 Apr 1998 15:09:17 +0200
Links: << >>  << T >>  << A >>
Hi Everyone,
 I have two questions concerning one time programmables such as
Quicklogic
and Actel.

1) Why do they seem to be lagging behind the SRAM based FPGAs so far in
the
number of available FLIP-FLOPs? Not counting using logic resources as
latches
the biggest of them seem only to have ~2500 flip-flops or so in their
logic
elements.

2) It also seems that they don't have the claimed savings in price.
I think an Altera 10k40 is around $90 or so (maybe even cheaper by now).

where as Actel had the following price which I grabbed from their web
site.

Device           Time Frame  100 pc    Percent    High     Percent
                             Resale    Reduction  Volume   Reduction
A32200DX-FPQ208C March 1    $176.00     48%       $97.00     54%
                  4Q97       $87.50     74%       $47.60     77%

It seems to me that $87.00 verses $90.00 is not much of a savings when
you consider that the Altera
device is reprogrammable. And both Altera and Xilinx have very low cost
FPGAs (spartan and flex6k)
that are around $10.00 - $20.00 for a 36k gate device. I'm I missing
something? Since they use so much
less silicon I would think the one time programmable would be much less
expensive. So why aren't they?

I would go with the one time programmables only if I needed their speed.
But it suprises me that they are
so far behind in every other way it seems. If anyone can comment I'd
like to get a thread going to expose
the issues here a little more. Sorry if this is a rehash of something
that appears here a lot. It seems that it
is the kind of thing that would be talk about to the point of annoyance
like "which is better VHDL or Verilog".

Thanks in advance,
Joshua
--
Joshua Schwartz
ICC Design
972-8-9287375
Josh@gezernet.co.il


Article: 9712
Subject: Re: Digital PLL's or Manual Synching?
From: "Lev Razamat" <lrazamat@netvision.net.il>
Date: Wed, 1 Apr 1998 17:39:41 +0300
Links: << >>  << T >>  << A >>

Martin Neilan wrote in message <3520F2E0.7590@hotmail.com>...
>Hi everyone,
>
>I have a need to implement a Digital Phase Locked Loop on and FPGA using
>V-System as the VHDL compiler and Xilinx as the synthesis software. If
>it is not possible, I will need to look at other ways to determine a
>suitable clock for an incoming serial stream of data (of undetermined
>frequency) and keep this clock in sync.
>
>However, in order to do this the second way (without a DPLL) I would
>require a quartz clock crystal running at preferably greater than 80
>MHz. Does such a thing exist? If not, is there a way of creating a
>faster clock using some clever coding from a slower quartz crystal?
>eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I
>have a feeling this might be possible but has anyone else done it?
>
>Any suggestions or help is greatly appreciated!
>
>Kind Regards,
>Steve Phillipson
>- A confused undergraduate engineer!

Of coarse dubbling is possible
here is pies of AHDL code how to do this

subdesign double
(
    clkin    :input;
    clkout    :output;
)
variable
    flipflop    :dffe;
    doub        :node;
begin
    flipflop.d=!flipflop.q;
    flipflop.clk=doub;
    doub=lcell(clkin $ flipflop);  -- incoming clock is XORed with output of
flipflop
    clkout=doub;
end;

this design gives short spickes on each edge of incoming clock
Lev



Article: 9713
Subject: bootstrap loader
From: "christophe Macia" <christophe.macia@delta-technologies.fr>
Date: 1 Apr 1998 14:39:46 GMT
Links: << >>  << T >>  << A >>
how can i do to use the bootstrap loader of the microcontroller SAB80C167
using a PCI interface as AMCC?

excuse-me for my english : it's not good!!

thanks

chris

Article: 9714
Subject: Re: Dual port
From: Zhiping <zpyao@spoke.ece.utexas.edu>
Date: Wed, 01 Apr 1998 09:31:01 -0600
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------583F823DD7132D1A3F3CF1EE
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I think your answer is good, but I have one more question: in the present Dual port,
one LUT's write address and read address are the same , the other LUT's write address
is the same as the first, but the read address is dual port address, I think some
time just make the two LUTs' write and read address both seperated, that means, both
the write address are the same and both the read address are the same, this scheme
can double the RAM capacity, why not?



--------------583F823DD7132D1A3F3CF1EE
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Zhiping Yao
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             Zhiping Yao
n:              Yao;Zhiping
org:            SanCom Technology, inc
email;internet: zpyao@spoke.ece.utexas.edu
title:          Engineer
x-mozilla-cpt:  ;0
x-mozilla-html: FALSE
version:        2.1
end:            vcard


--------------583F823DD7132D1A3F3CF1EE--

Article: 9715
Subject: Xilinx post routed VHDL/VITAL simulation
From: Todd KLine <tkline@wgate.com>
Date: Wed, 01 Apr 1998 11:07:42 -0500
Links: << >>  << T >>  << A >>
Has anyone experienced problems trying to do post-routed simulations
with Xilinx VHDL netlists with SDF timing files?  

I am simulating an XC4062 which takes close to 30 minutes just to load
into the Modeltech simulator.  The equivalent netlist in an ASIC format
(Chip Express models from Synopsys Design Compiler) loads in less then 5
minutes.  What the h*ll is Xilinx doing in their net list to screw
things up so badly?  When the netlist is compiled or loaded, I'm afraid
my hard drive is going to come flying out the side of my PC it's
thrashing so much.  

The results are even worse with Viewlogic's Vantage simulator.  

Does anyone have any clues or suggestions?  Xilinx's website is quite on
this subject.

Todd
Article: 9716
Subject: fifo
From: SAMIR KHERICHA <skherich@cs.wright.edu>
Date: Wed, 1 Apr 1998 12:27:18 -0500
Links: << >>  << T >>  << A >>

 I was trying to build a fifo 512X8 on XC4020E and i have a macro of 16X8
fifo which has push and pop alongwith full, empty and last logic. I have
thinking of different ways to cascade it. I would appreciate if someone 
could show me a smart idea to cascade it.

samir
------------------------------------------------------                   
Samir Khericha
Graduate Research Assistant
Department Of Computer Engineering
Residence:                       
2383 duncan drive               
apt #8
fairborn OH 45324
PH No: 937-426-8076
_______________________________________________________


Article: 9717
Subject: Re: Altera Bitblaster or Byteblaster??
From: rdamon@BeltronicsInspection.com (Richard Damon)
Date: Wed, 01 Apr 1998 19:54:49 GMT
Links: << >>  << T >>  << A >>
Felip Vicedo Roman <fvicedo@eug.upv.es> wrote:

>I'm working in Altera FPGA's.I'm want to make a board configurable from
>the computer, but I need the bitblaster or byteblaster. Somebody knows
>how this devices are make?? 
>
>
>Felip Vicedo Roman
>feviro@eug.upv.es

Check the freecore library pages at
http://193.215.128.3/freecore/

They have a schematic for a byteblaster

-- 
richard_damon@iname.com (Redirector to my current best Mailbox)
rdamon@beltronicsInspection.com (Work Adddress)
Richad_Damon@msn.com (Just for Fun)
Article: 9718
Subject: New Technology !!!!
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Wed, 01 Apr 1998 19:55:31 GMT
Links: << >>  << T >>  << A >>
April 1, 1998

Are you tired of fighting with Xilinx, Actel, Altera, or
some other FPGA tools

I have an idea for a new technology.

I call it HSI (Huge Scale Integration).

HSI is based on TI's latest advance in Logic devices,
PicoGate Logic.  You can now get a single NAND gate in
a SOT5 package that is about 3 X 3 mm in size.
See http://www.ti.com/sc/docs/asl/sin_gate.htm
I figure you could make an array of 100 X 100 of these
PicoGate NAND gates on a board. The board would be about
1 square foot in area.  This would give you 10,000 gates.
You could could use a dependable PCB layout tool such as
PADS to route the board to implement your logic.
Every gate in the array could be probed for debuging.

What do you think?

Bill Seiler
3255-4 Scott Blvd, Suite 105
Santa Clara, CA 95054
408 982 5420 Direct
408 982 5430 FAX
ccwest@ix.netcom.com 



Article: 9719
Subject: Re: New Technology !!!!
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 1 Apr 1998 20:23:59 GMT
Links: << >>  << T >>  << A >>
In article <6fu6bu$jhf@sjx-ixn7.ix.netcom.com> ccwest@ix.netcom.com (Bill Seiler) writes:
>April 1, 1998
>
>Are you tired of fighting with Xilinx, Actel, Altera, or
>some other FPGA tools
>
>I have an idea for a new technology.
>
>I call it HSI (Huge Scale Integration).
>
>HSI is based on TI's latest advance in Logic devices,
>PicoGate Logic.  You can now get a single NAND gate in
>a SOT5 package that is about 3 X 3 mm in size.
>See http://www.ti.com/sc/docs/asl/sin_gate.htm
>I figure you could make an array of 100 X 100 of these
>PicoGate NAND gates on a board. The board would be about
>1 square foot in area.  This would give you 10,000 gates.
>You could could use a dependable PCB layout tool such as
>PADS to route the board to implement your logic.
>Every gate in the array could be probed for debuging.
>
>What do you think?
>
>Bill Seiler
>3255-4 Scott Blvd, Suite 105
>Santa Clara, CA 95054
>408 982 5420 Direct
>408 982 5430 FAX
>ccwest@ix.netcom.com 



An excelent idea, and no need for dongles, dual port can be implemented
with connectors at each end of the board, but best of all, the marketing
guys/gals would be able to EXACTLY give the gate count. I would recomend 
using the PCB sw from Protel as it would fit so well in with the other 
advantages of this idea.

Philip.


Article: 9720
Subject: Re: Altera Bitblaster or Byteblaster??
From: winf176@ab200.rz.uni-karlsruhe.de (Teilnehmer Informatik I)
Date: 1 Apr 1998 22:21:27 GMT
Links: << >>  << T >>  << A >>
Felip Vicedo Roman (fvicedo@eug.upv.es) wrote:
> I'm working in Altera FPGA's.I'm want to make a board configurable from
> the computer, but I need the bitblaster or byteblaster. Somebody knows
> how this devices are make?? 


> Felip Vicedo Roman
> feviro@eug.upv.es

* Look at www.altera.com
* Visit the literature
* Download the bit/byteblaster datasheet
* ....

Armin
Article: 9721
Subject: Re: Digital PLL's or Manual Synching?
From: murray@pa.dec.com (Hal Murray)
Date: 2 Apr 1998 00:46:01 GMT
Links: << >>  << T >>  << A >>
In article <3520F2E0.7590@hotmail.com>, Martin Neilan <s_tretch@hotmail.com> writes:

> However, in order to do this the second way (without a DPLL) I would
> require a quartz clock crystal running at preferably greater than 80
> MHz. Does such a thing exist? If not, is there a way of creating a
> faster clock using some clever coding from a slower quartz crystal?
> eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I
> have a feeling this might be possible but has anyone else done it?

80 MHz osc packages should not hard to find/get.  They will be harder
to find than slower speeds but they are available.


It is possible to implement Digital PLL designs by processing several
data samples in parallel.  This makes more complicated logic that runs
at a slower cycle time.  You do need a fast front end (or delay line?)
to grab the input samples.

A 2 bit wide implementation could use the other clock edge to grab
the other data sample.

-- 
These are my opinions, not necessarily my employers.
Article: 9722
Subject: Re: XactStep6 - The cure for a dongle
From: staylor@dspsystems.com
Date: Wed, 01 Apr 1998 18:53:42 -0600
Links: << >>  << T >>  << A >>
Third party tools do solve some problems, but I have found that vendor
specific tools provide support as much as 6-12 months before third party
tools. I have also had better results from vendor tech support when trying to
solve a compiler bug.

In article <6e0M$TAR1gI1MAr1@fpga.demon.co.uk>,
  David Pashley <david@fpga.demon.co.uk> wrote:
>
> In article <3521f340.6145175@news.btinternet.com>, Richard Dungan
> <Richard.Radix@BTinternet.com> writes
> >Zoltan Kocsi <root@127.0.0.1> wrote:
> >
> >[snip loads of interesting stuff]
> >
> >One of the most interesting threads for a long time.
> >
> >I have to agree that ultimately the silicon vendors must decide
> >whether they are silicon vendors or software vendors. ISTR that the
> >original PALs (remember MMI?) did not start to take off properly until
> >PALASM was placed in the public domain.
>
> While in reminiscence mode, don't forget Signetics FPLAs which appeared
> at about the same time, and their design tool - "H&L".
>
> I would say that it was the appearance and adoption of the "vendor
> independent" design tool ABEL (and also CUPL) in the mid-eighties that
> really allowed the PLD market to expand and diversify. These allowed
> users to migrate to exciting new devices like Lattice's GAL 20V8,
> Altera's EP300, which would probably have been out of the question if
> they had had to buy a new tool every time.
>
> By the end of the eighties, the great majority of PLD design was
> performed using vendor-independent tools. This allowed new suppliers to
> encroach on AMD/MMI's and Signetics' market share.
>
> The FPGA tool market seemed to be going the same way in '93 when NeoCAD
> came along, but it was not to be.
>
> The FPGA vendors have learnt the lessons of history, and know the
> importance of the design and implementation tools in determining market
> dynamics. So, IMHO, they're in the s/w business to stay.
>
> --
> David Pashley                 <
>  ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
> | Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
> | * The EDA Source *       <  <  <               Fax: +44 1280 700577      |
>  ---------------------------  <  ------------------------------------------
>


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9723
Subject: Re: New Technology !!!!
From: Roger Yau <rogeryau@net.polyu.edu.hk>
Date: Thu, 02 Apr 1998 09:45:14 +0800
Links: << >>  << T >>  << A >>
Hi Bill,

Yeah, this is a good ideal! No limit on routing resource. The problems
is the production and routing of the PCB. Inaddition, it's size,
emission and power consumption......maybe the price is much 
higher than a FPGA......:)
____________________________________________________________________
Roger Yau
CASIL R & D Co., Ltd.
Article: 9724
Subject: Altera Bitblaster or Byteblaster
From: eng50195@leonis.nus.sg (Ho Voon Yee)
Date: 2 Apr 1998 03:39:33 GMT
Links: << >>  << T >>  << A >>
In article <35215640.5CE9757B@eug.upv.es> you wrote:
: I'm working in Altera FPGA's.I'm want to make a board configurable from
: the computer, but I need the bitblaster or byteblaster. Somebody knows
: how this devices are make??


: Felip Vicedo Roman
: feviro@eug.upv.es                 

Check out the site 

http://www.acte.no/freecore/didnt.htm

Regards,
Ho Voon Yee




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search