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Messages from 9775

Article: 9775
Subject: Re: Rees-Solomon
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Sat, 04 Apr 1998 17:25:21 GMT
Links: << >>  << T >>  << A >>

>Isabelle Gonthier wrote:
>
>> sylvain dery wrote:
>> >
>> > Hi all!
>> >
>> >         I have to design a Reed-Solomon encoder in VHDL for
>> > a graduate university project. The semester is ending soon and
>> > I think I took a bigger bite than I can chew!
>> > So I'm looking for practical implementation of the Reed-Solomon
>> > algorithm.
>> >
>> > Can anyone give me a hint?
>> >
>> > Thanks in advance!
>> > SLY
>> I have seen in the Xilinx Cores Solutions databook that there is a 3rd
>> party that has developed a Reed-Soloman encoder.  You might want to
>> check that out.
>
>Yes but Sylvain is a student.  I doubt he can afford a soft core for $100k
>
>(or is it free?).
Not a real answer, but for what it's worth;

Luckilly, you said Encoder and not Decoder.  An RS decoder is probably
not easy to find for free.  The Encoder is simpler; the one I'm
working with takes the bytes and essentially does the XOR style
multiplying, etc.  It requires only one clock per output data byte or
parity byte.  Just sending it to you probably wouldn't be the right
thing to do, eh?  If I were you, I might scan the net for a C program
that does just the encoding.  Then I'd analysis it, remove all the
unneccsary sequential stuff, work through the bit-width twiddling that
the processor has to do, to get your hardware algorithm (you can then
use the C program to check your work).  I know I've seen RS Encoders
in C on the net... can't remember where..  Good luck.

>
>Sam Falaki
>
>

Article: 9776
Subject: Re: Smoking Crater in a Xilinx 3k FPGA
From: James LaLone <lalone@worldnet.att.net>
Date: Sat, 04 Apr 1998 12:44:20 -0500
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> This subject comes up from time to time, much to Xilinx's annoyance.
> 
> Yes, it is easy to get a 3k device to misconfigure, with internal
> shorts all over the place, and run quite hot. I have done it myself a
> few times.

	....[snip]
 
> The other problem is with non-monotonic Vcc rise. The data book says
> it EITHER must be monotonic OR (if not) you must wait until Vcc is
> stabilised (with RST HIGH) and *then* apply the reset pulse, RST LOW,
> and *then* return RST to HIGH. I now do this as standard on every
> board I do:
> 
>              _____________
>  VCC   _____/
> 
>  /RST  __________   ______
>                 |___|
> 

In fact, the problem is worse than this.  If you read the really fine
print, you'll see that there is a rise time spec on VCC.  I dont' have
the data book handy, so I can't look it up right now.  But I found that
it was close to being an unrealistic spec.  The solution was to keep the
device in reset until the power was stable.  Then, when reset was
released, configuration would be successful.
-Jim
Article: 9777
Subject: VHDL in synopsys -> M1
From: Ho Siu Hung <eg_hsh@stu.ust.hk>
Date: Sun, 5 Apr 1998 01:46:06 +0800
Links: << >>  << T >>  << A >>
Hello everybody,

I come up with a problem, that when I wrote a VHDL code that include other
VHDL module (by component), the "save to xnf" command will save design in
different files (top/module).  When the top level xnf is loaded in M1 and
map, it will show a lot of logical DRC error.  Any comments?  I have check
the connection in synopsys, between modules, which are all correct.  And
the port map is quite simple, connecting two modules together to form a
bigger module.  Do I need to use the break hierarchy function in synopsys
first, then to M1?

-------------------------------------------------------------------------------
| Best Regards, 	  +--------+   | Email: eg_hsh@stu.ust.hk	      |
| David Ho		  | к |   |	cshosh@cs.ust.hk	      |
| Ho Siu Hung		  +--------+   |   	                              |
| University of Science and Technology |  ICQ#: 798357			      |
| Computer Engineering Year 3 (CPEG)   =======================================|
-------------------------------------------------------------------------------


Article: 9778
Subject: Re: XactStep6 - The cure for a dongle
From: "rk" <stellare@erols.com.NOSPAM>
Date: 4 Apr 1998 23:05:37 GMT
Links: << >>  << T >>  << A >>
someone said:
: > Either way you have to add something to your
: > system that will more than likely cause you a problem at some point.
What do
: > you do when Win98 changes and the card is no longer compatible?

austin: 
: Why would you think this?  Network cards are much less trouble than
: parallel ports.  Anyway, MOST PC who do CAE have a network card already. 
I
: believe NOT having a network card is the exception...

rk:
this is  bunch of us w/ pc's at home that use a modem instead of a network
card.  i just recently added one to talk to the wife's laptop; otherwise i
wouldn't have bothered with the card for obvious reasons.


someone said: 
: > A dongle that fits on a parallel port is
: > platform independent.

austin: 
: Again, more people have had problems with parallel ports....

rk:
nope, they're not platform independent.  when the machines got faster, a
lot of dongles stopped working.  that was a pain.  also, i have seen (day
job) some modern pci network cards that would not work with some win '95
'puters, although these were some of the early pci machines.  had to swap
in a 3com isa one and put the pci card in a more modern motherboard and
that cleared things up.  not very scientific, but just wanna run the thing.
-- 
--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------
Article: 9779
Subject: Re: VHDL in synopsys -> M1
From: Nick Hartl <"nhartl[no spm]"@earthlink.net>
Date: Sat, 04 Apr 1998 21:27:52 -0600
Links: << >>  << T >>  << A >>
Hard to say with out seeing the code. Hierarchy is fully supported in Synopsys so I
think there is something not quite right with the way that you are doing it.

Oh Well
Have FUN!!!
Nick

Ho Siu Hung wrote:

> Hello everybody,
>
> I come up with a problem, that when I wrote a VHDL code that include other
> VHDL module (by component), the "save to xnf" command will save design in
> different files (top/module).  When the top level xnf is loaded in M1 and
> map, it will show a lot of logical DRC error.  Any comments?  I have check
> the connection in synopsys, between modules, which are all correct.  And
> the port map is quite simple, connecting two modules together to form a
> bigger module.  Do I need to use the break hierarchy function in synopsys
> first, then to M1?
>
> -------------------------------------------------------------------------------
> | Best Regards,           +--------+   | Email: eg_hsh@stu.ust.hk             |
> | David Ho                | к |   |        cshosh@cs.ust.hk              |
> | Ho Siu Hung             +--------+   |                                      |
> | University of Science and Technology |  ICQ#: 798357                        |
> | Computer Engineering Year 3 (CPEG)   =======================================|
> -------------------------------------------------------------------------------



Article: 9780
Subject: "Offshore" Design Services
From: "Peter Fenn" <PeteFenn@iafrica.com>
Date: Sun, 5 Apr 1998 06:34:20 +0300
Links: << >>  << T >>  << A >>

----------------------------------------------------------------------------
----
"CodeLogic" (Digital & Software Design Services), provides a cost-effective
outsourcing alternative for your electronic and software product
development:

   - FPGA and programmable logic design (VHDL)
   - Embedded and DSP firmware (C and Assembler)
   - Windows Test software and Apps (Delphi 3)
   - Technical Documentation & Tutorials (HTML, +other)

For more details go to:  http://home.intekom.co.za/codelogic



Article: 9781
Subject: "Offshore" design services
From: "CodeLogic" <CodeLogic@intekom.co.za>
Date: Sun, 5 Apr 1998 07:15:25 +0300
Links: << >>  << T >>  << A >>
"CodeLogic" (Digital, Software & Internet Design Services), provides
 high quality, cost-effective outsourcing alternative for your electronic
 and software product development: http://home.intekom.co.za/codelogic

   - FPGA and programmable logic design (VHDL)
   - Embedded and DSP firmware (C and Assembler)
   - Windows Test software and Apps (Delphi 3)
   - Technical Documentation & Tutorials (HTML, +other)

For more details go to:  http://home.intekom.co.za/codelogic
----------------------------------------------------------------------------


Article: 9782
Subject: Waveform To Verilog RTL Synthesis
From: "clement" <clement@etsoft.com>
Date: Sat, 4 Apr 1998 20:15:54 -0800
Links: << >>  << T >>  << A >>
SPECIAL SYNTHESIS PRODUCT OFFERING

ETI ( http://www.etsoft.com ) recently introduced a waveform driven
synthesis tool (WaveScript) for generating synthesizable Verilog RTL code. A
special promotional node-locked licensing is available at $495.00 per
workstation node before May 30, 1998. There is a 30-day return guarantee
(shipping and handling charges are not refundable).

To order WaveScript, please send e-mail to sales@etsoft.com or call
408-973-8124.


Article: 9783
Subject: Re: Rees-Solomon
From: zblazek@kasami.UVic.CA (Zeljko Blazek)
Date: 5 Apr 1998 05:12:22 GMT
Links: << >>  << T >>  << A >>
tcoonan@mindspring.com (Thomas A. Coonan) writes:
: 
: >Isabelle Gonthier wrote:
: >
: >> sylvain dery wrote:
: >> >
: >> > Hi all!
: >> >
: >> >         I have to design a Reed-Solomon encoder in VHDL for
: >> > a graduate university project. The semester is ending soon and
: >> > I think I took a bigger bite than I can chew!
: >> > So I'm looking for practical implementation of the Reed-Solomon
: >> > algorithm.
: >> >
: >> > Can anyone give me a hint?
: >> >
: >> > Thanks in advance!
: >> > SLY
: >> I have seen in the Xilinx Cores Solutions databook that there is a 3rd
: >> party that has developed a Reed-Soloman encoder.  You might want to
: >> check that out.
: >
: >Yes but Sylvain is a student.  I doubt he can afford a soft core for $100k
: >
: >(or is it free?).
: Not a real answer, but for what it's worth;
: 
: Luckilly, you said Encoder and not Decoder.  An RS decoder is probably
: not easy to find for free.  The Encoder is simpler; the one I'm
: working with takes the bytes and essentially does the XOR style
: multiplying, etc.  It requires only one clock per output data byte or
: parity byte.  Just sending it to you probably wouldn't be the right
: thing to do, eh?  If I were you, I might scan the net for a C program
: that does just the encoding.  Then I'd analysis it, remove all the
: unneccsary sequential stuff, work through the bit-width twiddling that
: the processor has to do, to get your hardware algorithm (you can then
: use the C program to check your work).  I know I've seen RS Encoders
: in C on the net... can't remember where..  Good luck.

A web site you may want to look at is:

   http://hideki.iis.u-tokyo.ac.jp/~robert/codes.html

It has links to a bunch of different R-S Codec implementations,
although they are in C, and not VHDL.  As mentioned above, the
encoder is pretty straight forward.  It's essentially a LFSR
although the math is in GF(2^??) instead of GF(2).

Hope this helps,

Zeljko Blazek

: 
: >
: >Sam Falaki
: >
: >
: 
Article: 9784
Subject: Re: Smoking Crater in a Xilinx 3k FPGA
From: z80@ds2.com (Peter)
Date: Sun, 05 Apr 1998 06:59:42 GMT
Links: << >>  << T >>  << A >>

>In fact, the problem is worse than this.  If you read the really fine
>print, you'll see that there is a rise time spec on VCC.  I dont' have
>the data book handy, so I can't look it up right now.  But I found that
>it was close to being an unrealistic spec.  The solution was to keep the
>device in reset until the power was stable.  Then, when reset was
>released, configuration would be successful.

Yes, Vcc needs to rise faster than 25ms, according to my XC3k data. If
it is slower, OR if the rise is not monotonic, then Xilinx recommend
the method I suggest.

The problem is that unless you design your own power supply, or
carefully characterise a bought-in PSU and ensure that the PSU type
will never change, the above requirements cannot be guaranteed. The
proper solution, i.e. a low-going /RESET pulse applied *after* Vcc is
stable, is easily generated with e.g. a TL7705 and a 74HC132, 1
resistor and 1 cap. Or it can be done in software, if the CPU is
running independently of the FPGA. There must be an awful lot of
designs out there whose designers got away with it by luck rather than
by design.

I also forgot to mention that this VCC rise business is nothing to do
with the subject header. One cannot make an FPGA go up in smoke by
applying slow or non-monotonic Vcc. All that happens, IIRC, is that
the device will never enter the programming mode.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 9785
Subject: Re: XactStep6 - The cure for a dongle
From: z80@ds2.com (Peter)
Date: Sun, 05 Apr 1998 08:49:15 GMT
Links: << >>  << T >>  << A >>
It is better to lock M1.x to the C: drive serial number, because one
can edit that if necessary.

There have been Ethernet network cards with a customer-settable serial
number. Also, the s/n is normally stored in a little serial EEPROM,
and one could always make a copy of that before installing the card,
allowing the card address to be duplicated if necessary.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 9786
Subject: Re: Choosing the right FPGA tools...
From: Richard Schwarz <aps@associatedpro.com>
Date: Sun, 05 Apr 1998 06:06:33 -0400
Links: << >>  << T >>  << A >>
Take a look at the options at http://www.associatedpro.com/aps

If you know you are going to stay with XILINX and 8K gates then look at
the APS-X84-FSV which comes with schematic cature XVHDL and SYNOPSIS
VHDL and the router and CPLD tools , and the X84 FPGA test board with
FPGA installed, all for under 900.00!!! That's a great deal.

THIEBOLT Francois wrote:

> Hi,
>
> We're looking for a 'right' FPGA tools (near up to 8k gates) and i
> wonder
> what kind of FPGA would i use...Xilinx and their Foundation software
> (along with VHDL) or buying tools from other company...?
>
> Any clue ?
>
> Franois.
>
> --
> -------------------------------------------------------------
> THIEBOLT Francois \ You think your computer run too slow ?
> UPS Toulouse III  \ - Check nobody's asked for tea !
> thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
> -------------------------------------------------------------



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 9787
Subject: Re: Choosing the right tools and company....
From: Richard Schwarz <aps@associatedpro.com>
Date: Sun, 05 Apr 1998 06:09:40 -0400
Links: << >>  << T >>  << A >>
Take a look at the options at http://www.associatedpro.com/aps

If you know you are going to stay with XILINX and 8K gates then look at
the APS-X84-FSV which comes with schematic cature XVHDL and SYNOPSIS
VHDL and the router and CPLD tools , and the X84 FPGA test board with
FPGA installed, all for under 900.00!!! That's a great deal.

THIEBOLT Francois wrote:

> Hi,
>
> We're looking for SRAM based FPGA up to 8k gates...and of corse
> with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx
> We also need VHDL synthesis.
>
> Any tips ?
>
> Franois.
>
> --
> -------------------------------------------------------------
> THIEBOLT Francois \ You think your computer run too slow ?
> UPS Toulouse III  \ - Check nobody's asked for tea !
> thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
> -------------------------------------------------------------



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 9788
Subject: Re: Rees-Solomon
From: ees1ht@ee.surrey.ac.uk (Hans)
Date: 5 Apr 1998 11:30:18 GMT
Links: << >>  << T >>  << A >>

Do a search in Alta Vista and you will find lots of info on RS codecs (e.g. 
look for CS252 project). I have done this some time ago and have found an VHDL 
implementation. Another thing you might want to do is simplify the RS algorithm 
by fixing the number of correctable errors. This way you can get rit of the 
error polynomials and your galois multipliers can be simplified. A good 
suggestion which was given before is to find a C implementation and then code 
it up in VHDL. This was done here by an Msc student who finished the project in 
three month time. 

Good luck,

Hans.


In article <35264D09.DED5E71B@nospam.videotron.ca>, falaki@nospam.videotron.ca 
says...
>
>Isabelle Gonthier wrote:
>
>> sylvain dery wrote:
>> >
>> > Hi all!
>> >
>> >         I have to design a Reed-Solomon encoder in VHDL for
>> > a graduate university project. The semester is ending soon and
>> > I think I took a bigger bite than I can chew!
>> > So I'm looking for practical implementation of the Reed-Solomon
>> > algorithm.
>> >

Article: 9789
Subject: Counter problem ?
From: "Alexandre Pechev" <A.Pechev@rdg.ac.uk>
Date: Sun, 5 Apr 1998 18:00:26 -0000
Links: << >>  << T >>  << A >>
Hi Everyone,
I am designing a counter using Lattice isp1016 CPLD. Very strange (for me)
when the clk input was pulled up or even down, the counter was continue to
increment its value with random increments. I have checked the counter
design :o) many times - everything was OK. Finally I have decided to put 1nF
between clk and ground.
Now the circuit is working properly ... but I still have not answer why...?
The clk input was NOT nosy at all !
I really appreciate if someone give me an answer and are there any tricks,
tips or "recommended design" with Lattice's CPLD...
Thanks!
Alex



Article: 9790
Subject: Re: One time programmables
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sun, 05 Apr 1998 10:25:31 -0800
Links: << >>  << T >>  << A >>
Nick Hartl wrote:

> Maybe I am confused.  You write that Spartan needs a config prom with
> clock
> generation on board.  What do you mean? Surely you can't be saying
> that Spartan
> does not have an onboard clock for configuration purposes?  Because if
> that is what
> you are saying I suggest you look at the data sheet where an onboard
> clock for
> configuation is specified.
>  

Will Torgerson's posting is the type of propaganda that we can do
without in this newsgroup.
Not only is he factually wrong
( Spartan works in Master serial and Slave serial configuration exactly
the same way as XC4000. It is Altera that has an SPROM with built-in
clock generator...)
but his whole posting is the kind of breathless hype that we don't need
here.

I know that I also put the best Xilinx foot forward, but at least I try
to be subtle.
Let's not degenerate into Marketing hype.

Peter Alfke, Xilinx Applications

Article: 9791
Subject: Re: Counter problem ?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sun, 05 Apr 1998 10:39:17 -0800
Links: << >>  << T >>  << A >>
Unless you have excessive ground bounce or a poorly decoupled Vcc or
floating inputs, your problem seems to be noise on the clock input.
Modern flip-flops consider a 1-to-2 ns spike a good enough reason to
toggle, and many designers do not have a 'scope that would show such
spikes.
Also, when distributing fast clock signals for more than a few inches,
the designer must consider transmission-line characteristics,
reflections ( ringing ) and appropriate termination methods.
Remember: a slow application does not make the flip-flops slow!

Good luck
Peter Alfke, Xilinx Applications
 

Alexandre Pechev wrote:

> Hi Everyone,
> I am designing a counter using Lattice isp1016 CPLD. Very strange (for
> me)
> when the clk input was pulled up or even down, the counter was
> continue to
> increment its value with random increments. I have checked the
> counter
> design :o) many times - everything was OK. Finally I have decided to
> put 1nF
> between clk and ground.
> Now the circuit is working properly ... but I still have not answer
> why...?
> The clk input was NOT nosy at all !
> I really appreciate if someone give me an answer and are there any
> tricks,
> tips or "recommended design" with Lattice's CPLD...
> Thanks!
> Alex

  

Article: 9792
Subject: installation altera maxplus2 8.2
From: j.kreyssig@fh-wolfenbuettel.de
Date: Sun, 05 Apr 1998 15:35:47 -0600
Links: << >>  << T >>  << A >>
The installation of maxplus2 v. 8.2 is no problem on all our PCs exept one.
There it stops immediately after the first installation window appears with an
error in installw.

Who can help ?

Juergen

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9793
Subject: Re: XactStep6 - The cure for a dongle
From: Rick Collins <redsp@writeme.com>
Date: Sun, 05 Apr 1998 20:51:43 -0400
Links: << >>  << T >>  << A >>
rk wrote:

> ...snip...
>
> : > i'd say this qualifies as a pita, [ok, pain in the *ss], since after
> : > investing dollars to upgrade one piece of software, two designers, both
> : > licensed for Brand 'X', can no longer work on the same project, unless
> they
> : > spend more $.  now what to do with those useless dongles sitting in my
> desk
> : > draw ... get out the hockey stick?

> rick c.:
> : I had exactly this problem using Viewlogic in my last job. When it came
> time to
> : buy FPGA design tools for my current posistion, I didn't even consider
> : Viewlogic. I was also very negatively impressed with their tech support.
> Now
> : that I am using the Orcad product, I feel that I made the right decision.
>
> rk:
>
> how is the orcad simulation?
>
> do they still give you all those pcb netlisters, for no additional $?
>
> we gotta know!
>
> as for viewlogic tech support, i've had mixed results.  some very good guys
> that just jump right on a problem and solve it.  and some other
> experiences, too.
>
> --------------------------------------------------------------
> rk

I don't have any problems with the Orcad simulation. I have used it almost
exclusively to run VHDL testbench simulations of both VHDL and schematic
designs. So far I have only run a small part of my design to use as a learning
tool. I have written VHDL, designed a schematic with the VHDL as components and
simulated all of the pieces and the total design. Now I am testing the ways to
control the routing and placement of the Xilinx part. I am having more trouble
with this since there is very little documentation. I have had to make several
calls to both Orcad and Xilinx customer support to get any useful info on
constraints.

I have no info on PCB netlisters. But Orcad gives you the total interface
package for all six FPGA vendors that they support. Of course this was not
cheap either. Bundled with the layout software and the "Enterprise" software,
it was about $17,000.

I'll be happy to tell you more as my design progresses. Right now I am caught
in a documentation phase. I should resume design work shortly.

Rick Collins

redsp@writeme.com




Article: 9794
Subject: Re: One time programmables
From: staylor@dspsystems.com
Date: Sun, 05 Apr 1998 23:53:50 -0600
Links: << >>  << T >>  << A >>
Peter,

This was in your reply.

>> It is Altera that has an SPROM with built-in clock generator...)

I use Altera and noticed that the 10k series has the SPROM supplying the clock
while the 8k series has the FPGA supplying the clock. I haven't asked anyone
at Altera why and have not read any explanations as to why the change was
made. Do you know of any good reasons? A disadvantage that I have already come
across when I used both a 10k and 8k device on the same board is that I cannot
use a single SPROM to configure them both. The new SPROMs are backwards
compatible in that they will disable their internal clock, but then they will
not configure 10k devices without exteranl help (something else generating the
clock). Even then is is not clear it will work.

I will give you a chance to plug your products with a question I have asked
several marketing people from Xilinx when they have called, but so far is
still unanswered.

I used XACT version 5.0 to do a design using an XC3190. I was told at the time
I could use ABEL and boolean entry instead of OrCAD and schematic entry. When
I actually tried I found I could only use ABEL for the buried cells but not
the I/O cells. I was told by Xilinx tech support that capability was coming. I
checked for a year or so and it never materialized. Consequently I let my
maintenance expire and have not used the development software since.

Can an entire design using the 3000 series and 4000 series now be done
entirely using ABEL? And, if so, does Xilinx provide the support or does
DataIO? I have never been impresses by DataIO response time to bugs and hence
prefer vendor tools.

Scott Taylor - DSP Systems Inc.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 9795
Subject: Re: VHDL in synopsys -> M1
From: Koenraad Schelfhout VH14 8993 <ksch@sh.bel.alcatel.be>
Date: Mon, 06 Apr 1998 08:38:14 +0200
Links: << >>  << T >>  << A >>
Two suggestions :

 either : do a "write -hierarchy"

 or (as Xilinx suggests) :
    ungroup -flatten -all
    write xnf output (here you have only 1 level)
-- 

 Koenraad SCHELFHOUT

 Switching Systems Division          http://www.alcatel.com/
 Microelectronics Department - VH14     _______________
________________________________________\             /-___
                                         \           / /
 Phone : (32/3) 240 89 93                 \ ALCATEL / /
 Fax   : (32/3) 240 99 47                  \       / /
 mailto:ksch@sh.bel.alcatel.be              \     / /
_____________________________________________\   / /______
                                              \ / /
 Francis Wellesplein, 1                        v\/
 B-2018  Antwerpen
 Belgium
Article: 9796
Subject: Re: installation altera maxplus2 8.2
From: chakanp@hem1.passagen.se
Date: Mon, 06 Apr 1998 02:23:36 -0600
Links: << >>  << T >>  << A >>
Please have a look at www.altera.com and then the ATLAS solutions database.
The Error in installw appears sometimes when there is an illegal path in the
search path. Or if you try to install the MAX+PLUS II from a networked CD-ROM.
If you do please add that networked CD in to the PATH or just plainly copy all
the PC subdirectory from the CD on to the harddrive and then install MAX+PLUS
II from the harddrive.

Best Regards
Hkan
In article <6g8pv3$8nh$1@nnrp1.dejanews.com>,
  j.kreyssig@fh-wolfenbuettel.de wrote:
>
> The installation of maxplus2 v. 8.2 is no problem on all our PCs exept one.
> There it stops immediately after the first installation window appears with
an
> error in installw.
>
> Who can help ?
>
> Juergen
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/   Now offering spam-free web-based newsreading
>


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 9797
Subject: Re: Xilinx routing optimization?
From: peterc <peterc@hmgcc.gov.uk>
Date: Mon, 06 Apr 1998 09:58:54 +0100
Links: << >>  << T >>  << A >>
Jacob W Janovetz wrote:
> 
> Howdy...
> 
>    I have a design which generates a divided clock internally.
> I had a few problems with this until I brought the clock out to
> an external pin.  The problems disappeared.  (the routing of this
> signal to the outside is all that changed in the HDL).  I checked
> the two designs using EPIC and found that the good design had
> delays of < 10ns on that signal.  The bad design had delays of
> up to 17ns which are causing the trouble.  The bad design routes
> the signal all over the chip and doesn't really need to.
> 
>    My question is, how can I setup the xilinx tools to optimize
> this sort of thing.  I can set constraints in Leonardo (my HDL
> software), but they only optimize for logic.  Likewise, I can
> setup optimization in Xilinx's "map" program to optimize for
> speed, but that only does logic.  How can I make the Xilinx tools
> realize they can route this thing better?
> 


Are you using the divided clock as an internal clock (connected to CLB
clks)?

If so you should add a gclk or aclk (3k) or bufgs/bufgp (4k). This will
gaurentee low clock skew between all clock pins, which could be your
real problem. Is clock skew or clock delay the problem?
Article: 9798
Subject: Actel gear available
From: "Douglas W. Olsen" <dwolsen@ra.rockwell.com>
Date: Mon, 06 Apr 1998 09:19:06 -0400
Links: << >>  << T >>  << A >>
FOR SALE    Actel Programming System
		Barely used

        $2500 for all this
             (cost > $7000 new)

Designer Series 3.1 and 3.1.1 Software
  (Product code DAT-PC)
   All disks and documentation intact

Activator 2S Hardware Programmer
   with ACT12-144PQFP adapter
   Used three times

ALS-218 Action Probe (debugger)
   never used

        $2500

Contact:
-----------------------------------------------------------
Douglas W. Olsen     | voice:   770.622.6286               |
Rockwell Automation  | FAX:     770.623.9163               |
2150 Boggs Road      | email:   dwolsen@ra.rockwell.com    |
Duluth, GA 30096     |
Article: 9799
Subject: Re: Xilinx routing optimization?
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 6 Apr 1998 13:47:25 GMT
Links: << >>  << T >>  << A >>
peterc <peterc@hmgcc.gov.uk> writes:

>Jacob W Janovetz wrote:
>> 
>> Howdy...
>> 
>>    I have a design which generates a divided clock internally.
>> I had a few problems with this until I brought the clock out to
>> an external pin.  The problems disappeared.  (the routing of this
>> signal to the outside is all that changed in the HDL).  I checked
>> the two designs using EPIC and found that the good design had
>> delays of < 10ns on that signal.  The bad design had delays of
>> up to 17ns which are causing the trouble.  The bad design routes
>> the signal all over the chip and doesn't really need to.
>> 
>>    My question is, how can I setup the xilinx tools to optimize
>> this sort of thing.  I can set constraints in Leonardo (my HDL
>> software), but they only optimize for logic.  Likewise, I can
>> setup optimization in Xilinx's "map" program to optimize for
>> speed, but that only does logic.  How can I make the Xilinx tools
>> realize they can route this thing better?
>> 


>Are you using the divided clock as an internal clock (connected to CLB
>clks)?

>If so you should add a gclk or aclk (3k) or bufgs/bufgp (4k). This will
>gaurentee low clock skew between all clock pins, which could be your
>real problem. Is clock skew or clock delay the problem?


As I said, some of the signal are routed all over the damn place
and aquire about 17ns of delay.  Some only get up to 9ns.  I've
added buffers when needed, but this is a case where I can get away
without using one.  A buffer would help of course, but when the
tools route poorly, I'd like a way to fix it.

   Cheers,
   Jake

--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html


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