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Hi,
I know this is the not the exact place to talk about system
generator but I felt that this is the closest one. I have access to a
system that has Matlab R2006a on it. I wanted to try system generator
evaluation version but it just won't install as only 8.1.1i supports it
and that is only available for purchase. Is there any alterantive to
make System Generator 8.1i work with Matlab R2006a or do I have to wait
till that service pack is available for evaluation too?
cheers,
kishore.
Article: 103001Ben Jones wrote > The veritable deluge of complaints - both from customers and from internal > users - has not simply leaked away into the Water Table of Inaction: > rather, > it has been funneled through the Downpipe of Customer Support and > collected > in the Water Butt of the Change Request System. Some of it is currently > leaking through the Damp-Proof Course of Management. Erm, stop me when > I've taken the analogy too far... :) Quoting a England football manager: "I don't believe in metaphor. I believe in calling a spade a spade."Article: 103002
Thank you for your advice. I'm running a new long time test with a glitch-free frame_rdy_out. DennisArticle: 103003
Marco, If you have access to a tool such as ChipScope (embedded Logic analyzer from Xilinx http://www.xilinx.com/ise/optional_prod/cspro.htm ) this will provide a more convenient debug solution. However the picoblaze approach is definitely more fun. Vivian -- Sandbyte > Falk, > really interesting your idea of using a Picoblaze as a terminal server, > I have to deal with a Spartan3, could you please give more details on > the way you do that? > Thanks, > Marco >Article: 103004
bijoy wrote: > Hi I am facing the following problem during P&R of my design > > =================================== Error - Description Phase 1.1 ERROR:Place:341 - The design contains 3 Block RAM components that are configured as 512x36 Block RAMs and 11 Multiplier components. The Multiplier site adjacent to the location of a 512x36 Block RAM component must remain free because of resource sharing. Therefore a device must have at least 14 Multiplier sites for this design to fit. The current device has only 12 Multiplier sites. > > =================================== > > I am using FFT core with 18-bit as the input data width, then all these above errors pops up if i reduce the input width to 17-bit, the design won't give any error. > > can any body help me to sort this problem ?? > > Thanks in advance > > Bijoy I believe someone mentioned recently that you cant use a block ram and it's adjacent multiplier at the same time if the block ram is configured in 36 bit mode. A possible solution, which may or may not work, would be to build each 512x36 RAM you require out of two RAM's configured as 1024x18. Cheers, Andy.Article: 103005
"Marco" <marco@marylon.com> wrote in message news:1148475677.352442.62550@y43g2000cwc.googlegroups.com... > Hi, > how does debug work in with fpga? > On common processor you can move from line to line of code, check > variables values and have the whole system control with the jtag. > How do things change here? > Thanks, > Marco Most functional debug is done with a simulator. The techniques Falk has outlined are useful for debugging real world interface problems but for debugging the majoroty of typos, logical errors etc then you need a simulator. Simulation can range from a quick and dirty simple module level testbench to a full system tests modelling the behaviour of external RAMS, PCI interfaces etc. Nial.Article: 103006
I'm prototyping a design on an Altera NIOS evaluation board with an EP2C35. The design will eventually be targeted at a much smaller device, possibly an EP2C5. I have a couple of FIR filters that I want implemented in the FPGA fabric rather than in the dedicated multipliers so I can guage the footprint/performance. Quartus keeps using the multipliers and I can't work out how to stop it. Can anyone help? Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103007
Nial Stewart wrote:
> I have a couple of FIR filters that I want implemented in the FPGA
> fabric rather than in the dedicated multipliers so I can guage the
> footprint/performance. Quartus keeps using the multipliers and
> I can't work out how to stop it.
Could you code something that uses up all the multipliers?
-- Mike Treseler
Article: 103008I want to constrain the max fanout for a particular net in my design. I am using the XPS flow and the net I want to constrain is a BRAM address signal and is generate by xps, during platgen I suppose. I don't think I can just go in and add attribute constraints to the system.vhd file in the hdl/ directory because those files seem to be regenerate every time. How can I constrain the fanout for this net? Thanks for any pointers. MattArticle: 103009
The I2C interface is pretty simple for just talking to a slave. I personally find it much easier to just infer a shift register and small state machine rather than putting in pico or microblaze and all the baggage that goes with it.Article: 103010
"Andy Ray" <andrewray@blueyonder.co.uk> wrote in message news:vg%cg.202900$tc.171588@fe2.news.blueyonder.co.uk... > > > I believe someone mentioned recently that you cant use a block ram and > it's adjacent multiplier at the same time if the block ram is configured > in 36 bit mode. > > A possible solution, which may or may not work, would be to build each > 512x36 RAM you require out of two RAM's configured as 1024x18. > > Cheers, > Hi Andy, Yeah, that might work. Make the 512*36 a 1024*36 made from 2 off 1024*18. Then it should fit, as you've still only used 6 BlockRAMs. Cheers, Syms. Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103011
it depends, :) microblaze is true overkill, but picoblaze isnt, specially if you have some other minor managements taks to take also, then it really pays the fpga resource price it takes anttiArticle: 103012
Antti (Antti.Lukats@xilant.com) wrote: : it depends, :) microblaze is true overkill, but picoblaze isnt, : specially if you have some other minor managements taks to take also, : then it really pays the fpga resource price it takes Also if the 'I2C' device isn't following the spec particularly well then debugging the interface by reloading the picoblaze ROM at run time makes for a much better interactive debugging experience than recompiling VHDL! Of course this isn't relevant as nobody would ever ship a device with a broken I2C compatible interface... cdsArticle: 103013
In article <1148420806.519398.325680@u72g2000cwu.googlegroups.com>, Kishore <kishore2k4@gmail.com> wrote: >Hi, > > I know this has been brought up many times in various groups but >here is my view on them and I would really appreciate some >clarification. I started working on FPGA design and stuff some 3 months >back or so. All the time I was switching back and forth between verilog >and VHDL for various projects. I personally feel that one can be very >productive as in time with Verilog? I only use VHDL if there is no >choice but I am not aganist VHDL or anything. > > After some searching on google and various usenet groups I came >across many arguments regarding Verilog vs VHDL summarising either as >"use the right the tool for the right job" or "leading to language >wars". I am open-minded and I am biased to the former at the same time >a bit biased to verilog :) I just wanted to know some things. > >-> Are there things that VHDL does better than verilog or vice-versa >-> What is the most widely used language in the industry i.e. FPGA and >ASIC designs. I think VHDL is the dominant one as Xilinx totally uses >VHDL? > > All kinds of thoughts, experiences and constructive criticisms will >be helpful. Here be dragons and I should perhaps not jump into the dragon pit, but here's an observation: One thing I notice is that people who have had exposure to software development seem to prefer VHDL because VHDL allows one to define new types whereas with Verilog you've gotta be happy with the types that come with it out-of-the-box. Hardware engineers with lots of software background might therefore tend to prefer VHDL whereas Hardware engineers with less software development experience might tend to prefer Verilog because they may not care about the potential benefits of being able to define new types. ...but I don't want to over generalize... ;-) PhilArticle: 103014
John Adair schrieb: > I don't understand where the there are issues of jitter unless you use a DCM > in which case you will have issues with all Xilinx FPGAs and to varying > extent other vendors too. The point of our board is that you can have a high > speed clock with low jitter and not necessarily using the DCM which does > have jitter of some 10s of picoseconds. Even with a zero jitter 1GHz clock the generated delay will jitter 1ns. The output will arrive anytime in a clock period, but the output will be generated a fixed time after a clock edge. The delay is the difference between input and output. It will have +-500ps error. The 50ps jitter in the DG535 spec really means that the delay is fixed with 50ps accuracy, not only that the output time can be predicted with 50ps accuracy. Kolja SulimmaArticle: 103015
In sci.electronics.design mljohnson00@yahoo.com wrote: >Hi Sanjay, >I'm afraid I can't answer your question directly, but I can offer some >food for thought. Be very careful treading into 64/66 PCI territory. >The technology is new(ish), somewhat unproven, and mostly untested. >I've had experience with board vendors that flat out lie about the >64/66 capability of the boards or at least they never bothered to test >to see if it really worked. >Be sure you REALLY need that extra throughput. Good luck Isn't PCI 64/66 a dead end considering PCI-express these days ?Article: 103016
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:4djilhF1annadU1@individual.net... > I'm prototyping a design on an Altera NIOS evaluation board with > an EP2C35. The design will eventually be targeted at a much smaller > device, possibly an EP2C5. > > I have a couple of FIR filters that I want implemented in the FPGA > fabric rather than in the dedicated multipliers so I can guage the > footprint/performance. Quartus keeps using the multipliers and > I can't work out how to stop it. > > Can anyone help? In the multiplier megafunction (LPM_MULT) on page 2 there are switches available to turn off the use of the chips dedicated multipliers and use logic elements instead. SlurpArticle: 103017
Hello all: Is there a way in Xilinx ISE of knowing the percentage of routing resources that have been utilized after Place and Routing? Until now I was happy just knowing if a design was routable or not. Now I need to have a more quantitive idea of the routing resource usage and I don't know where to start looking. The default Place and Route report gives only logic and I/O resource information. Thanks, Rafael Arce University of Puerto RicoArticle: 103018
"Slurp" <slip@slop.slap> wrote in message news:4474b484$0$2661$ed2619ec@ptn-nntp-reader01.plus.net... > In the multiplier megafunction (LPM_MULT) on page 2 there are switches available to turn off the > use of the chips dedicated multipliers and use logic elements instead. > Slurp I'm inferring the multipliers so don't have this control unfortunately. Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103019
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4djk48F1auig8U1@individual.net... > Nial Stewart wrote: >> I have a couple of FIR filters that I want implemented in the FPGA >> fabric rather than in the dedicated multipliers so I can guage the >> footprint/performance. Quartus keeps using the multipliers and >> I can't work out how to stop it. > > Could you code something that uses up all the multipliers? > -- Mike Treseler I suppose I could Mike, but it's a lot of hassle for what will hopefully just be a switch/constraint. Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103020
Isn't ISA a dead end considering PCI, yet it is still used !!!! <pbdelete@spamnuke.ludd.luthdelete.se.invalid> a écrit dans le message de news: 4474b0be$0$490$cc7c7865@news.luth.se... > In sci.electronics.design mljohnson00@yahoo.com wrote: >>Hi Sanjay, > >>I'm afraid I can't answer your question directly, but I can offer some >>food for thought. Be very careful treading into 64/66 PCI territory. >>The technology is new(ish), somewhat unproven, and mostly untested. >>I've had experience with board vendors that flat out lie about the >>64/66 capability of the boards or at least they never bothered to test >>to see if it really worked. > >>Be sure you REALLY need that extra throughput. Good luck > > Isn't PCI 64/66 a dead end considering PCI-express these days ? >Article: 103021
> Quartus keeps using the multipliers and > I can't work out how to stop it. > How about setting Analysis and Synthesis settings -> More Settings -> Maximum DSP Block Usage to 0? (Default -1)Article: 103022
I am currently using ISE 8.1 and am receiving this message after entering a clock period constraint: WARNING:XdmHelpers:662 - Period specification "TS_U1_gen_clk1" references the TNM group "U1/gen_clk1", which contains both pads and synchronous elements. The timing analyzer will ignore the pads for this specification. You might want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads from this group. This clock (2 Khz) is generated using a counter and is internal to the device. What is the correct way to specify the qualifier so this warning goes away? Thanks, JoelArticle: 103023
In article <4474ba59$0$294$7a628cd7@news.club-internet.fr>, John@nospam.com says... > Isn't ISA a dead end considering PCI, yet it is still used !!!! > ISA is still used because it's trivial to hack. PCI is anything but. -- KeithArticle: 103024
"Henry Wong" <henry@stuffedcow.net.nospam> wrote in message news:mvOdnZ8y7KReJunZnZ2dnUVZ_tSdnZ2d@teksavvy.com... >> Quartus keeps using the multipliers and >> I can't work out how to stop it. > How about setting > > Analysis and Synthesis settings > -> More Settings > -> Maximum DSP Block Usage > > to 0? (Default -1) Thanks Henry, that did it. I mistakenly presumed that -1 was a lower number than 0 and so changing this to 0 wouldn't have made any difference. Intuitive isn't it :-) Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.uk
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z