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Kolja Sulimma wrote: > John Adair schrieb: > > I don't understand where the there are issues of jitter unless you use a DCM > > in which case you will have issues with all Xilinx FPGAs and to varying > > extent other vendors too. The point of our board is that you can have a high > > speed clock with low jitter and not necessarily using the DCM which does > > have jitter of some 10s of picoseconds. > > Even with a zero jitter 1GHz clock the generated delay will jitter 1ns. > The output will arrive anytime in a clock period, but the output will be > generated a fixed time after a clock edge. The delay is the difference > between input and output. It will have +-500ps error. To reduce jitter that is caused by unsynchronized triiger and 1GHz clock, I think to use oversampling method. It means 1GHz clock will be shifted four or eight times and used for sampled input trigger. In this way jiiter (error) will be reduced for 4-8 times. AmirArticle: 103051
This afternoon I run a flow (ISE 8, Linux) and got in the log a warning message. The word 'Warning' was an hyper link so I clicked on it hopping to get a more detailed description of the warning. Few seconds later I was surprise to find myself in Xilinx site in a page that displays the full path of the file I compiled. The path included sensitive information such as my name, the name of my employer and the code name of the project I was working on. Xilinx, please be more sensitive to the privacy of your customers. JimArticle: 103052
Thanks.Article: 103053
Hi! I'm running Quartus in remote Linux workstation and I use Cygwin X-server in my PC. If I use gnome desktop (xwin -query) Quartus opens nicely. But if I use a single X-terminal (ssh -X) to open Quartus it doesn't work. I receive an empty white Quartus splash screen. Option -no_splash doesn't help, then the main window is empty white. Any ideas? Antti Tyrv=E4inen ElektrobitArticle: 103054
Thanks guys for these interesting posts... Why is ISA still out there ? Look at the PowerPC architecture, there's ISA in it. Look at any PC - there's ISA in it (even if the bus does not come out on connectors on the mobo it's in the chipset). It's still there for legacy issues. Same reason we (well less and less it's true) carry on some of the initial limitations imposed by MD-DOS on our windows systems. When a new std comes out, it usually sticks around some time. Look at the VME bus, still out there ! When those guys from the military make a new equipement, they have to be capable to insure that the technology will still be out there in 20 years (in most Xtreme cases). Some never really did make it through (IBM_PS2 ... SUN_SBUS and a few others). Rgds, John "krw" <krw@att.bizzzz> a écrit dans le message de news: MPG.1edee8d2bcf4487c9896d0@news.individual.net... > In article <1279jbqev8c163d@corp.supernews.com>, > JKolstad71HatesSpam@yahoo.com says... >> "Keith" <krw@att.bizzzz> wrote in message >> news:MPG.1ede86986bc24a65989a95@News.Individual.NET... >> > In article <4474ba59$0$294$7a628cd7@news.club-internet.fr>, >> > John@nospam.com says... >> >> Isn't ISA a dead end considering PCI, yet it is still used !!!! >> >> Hopefully not in *new* designs. :-) As far as I can tell, ISA only >> sticks >> around in industrial PC boards so that already working systems can be >> maintained, which makes perfect sense. (There's at least one company out >> there still making replacement PDP-11 boards, after all...) >> >> > ISA is still used because it's trivial to hack. PCI is anything >> > but. >> >> Only if you're planning to actually implement the PCI interface >> yourself... > > What's so hard to understand about "hack"? > >> which really only makes sense if you're planning to try to squeeze the >> last >> once of performance out of the bus. For most designs, using interface >> ICs >> from the likes of PLX Technology make PCI pretty darned friendly to >> implement >> to (their chips have options to treat the "card" side of the bus as >> anything >> from reasonably sophisticated down to dumb-as-a-PIC). Cypress has an IC >> that >> places a dual-port RAM (and a couple of FIFOed mailboxes) across the PCI >> bus, >> also making it trivial for even the "dumbest" logic to interface. > > Sure, but that's hardly hacking. I've used PLX chips and they're > certainly not trivial to use. Even given that the chip simply > works, the board layout is 100x harder than ISA. Programming is > equally hard (comparatively). Any damned fool can build an ISA > channel card with a few 74xx gates. PCI is *hard* even with PLX > doing the heavy lifting. > >> USB is quite similar -- unless you're after an education, for the vast >> majority of designs the various USB interface ICs (e.g., from FTDI) or >> USB-based microcontrollers with supplied low-level code (from Cypress, >> Atmel, >> Microchip, etc) let you worry about the unique aspects of your design >> rather >> than interfacing with Yet Another Bus. > > Certainly, but USB ain't ISA either. > >> For FPGAs or standard-cell logic, there are lots of USB and PCI cores out >> there from the usual suspects. > > Sure, but FPGAs or standard-cell aren't a coupla 74xx buffers > either. ISA was a piece of cake for an idiot (and still lives in > the ATA connector for those who want to play ;). > > -- > KeithArticle: 103055
To each his own. PCI is just a vehicle for me to get data from the CPU to my logic. It could be anything else for that matter. Like it has been said earlier in the post, there are many vendors with standard pci controllers that cost less than a low end spartan. I therefore, would like to see a board that uses these of the shelf PCI semiconductors. It woudl not be very productive and cost effective to integrate 3rd party PCI core into the fpga. Not sure with PCI Express, but it certainly isn't as easy and cheap to use as PCI.Article: 103056
Jim wrote: > Few seconds later I was surprise to find myself in Xilinx site in a > page that displays the full path of the file I compiled. The path > included sensitive information such as my name, the name of my employer > and the code name of the project I was working on. Hi Jim, If true that's a horrible thing for them to do, but remember that what you see in your browser window resides on your own computer. I'm no web guru, but it might be possible that the Xilinx website generates Dynamic HTML (or Javascript, etc) that is interpreted by your browser and used to create what you see your screen without actually transferring any sensitive information to Xilinx. For example, when they dynamically create a web page for your browser, they might send a reserved environment variable name instead of the real path (for example), which your browser then renders as the actual absolute path. Perhaps a Xilinx rep could clarify? RonArticle: 103057
>...Altera Cyclone...immediately after programming... >the board resets... It could be many things. Why do you think that it's a problem in programming? One common reason for reset when an Altera device starts to run is leaving the "unused pins" configuration set to "output driving low" (a stupid default in Quartus).Article: 103058
<roiavidan@gmail.com> wrote in message news:1148539184.893813.216500@u72g2000cwu.googlegroups.com... > Hello everyone, > > I am trying to program an Altera Cyclone (EP1C20) device, which comes > with the NiosII processor already in it, using the Quartus 5.0 > software. > My connection to the board is via the JTAG connection. > > When programming, I get no errors from the Quartus software, but > immediately after programming has been completed, the board resets and > starts the Nios system again, as if nothing happened. > > What am I doing wrong? Is this a NiosII design of your own targeted at the Altera Nios eval board? If so then the config prom has a line from the FPGA, reconfig_req, that allows any Nios to request a reconfiguration. You need to set this permanently high (and assign it to the correct pin). Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103059
Using a LVDS buffer can be one way to achieve a simple comparitor providing the level is within common mode range. Tie one end to the level you want. if you are going to use a very accurate comparitor general pickup of noise will introduce jitter and general development may not be what you want. If you are that worried about jitter I certainly would not use a DCM in the clock structure. The LVDS wire pairs in boards don't have inherent jitter themselves only the chips at either end. The local noise at a FPGA that may introduce jitter will depend on your design and it's implementation within the FPGA amongst other factors and I doubt if anyone on this group could give you jitter guarantees as absolute numbers without a design implementation measurement. All you can do is start with the best clock you can and do everything else as best practise. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex4 Development Board. http://www.enterpoint.co.uk "amko" <sinebrate@yahoo.com> wrote in message news:1148481217.144437.89430@g10g2000cwb.googlegroups.com... > Since that I should add still LVDS/ECL or LVDS/NIM converters/drivers > what will results in additional jitter. > Can you guarantee that jitter on your LVDS (high speed links) is less > than 50ps. > What about external trigger uncertainly domain. For this case I > probably need very accurate input comparator. > Spartan 3 DCM period Jitter is +/150ps. >Article: 103060
Hi Folks, Altera does the same as well. In Quartus II, they have a feature called "TalkBack" which reports back to Altera via an XML file, details about the software tools you are using(including synthesis, simulation, timing analysis and "others" , design constraints, IP usage, name of top level file, time of compilation etc). Also reported back include hostid, NIC ID and C: drive info), which they state in their EULA (whoever reads that !!!) that they may use to determine the identity of the user. Even if you are disconnected from the Net, all details are saved for later transmission. However, I'm sure it is all used to help the user....hmmm. Bob PS you can disable this feature, but I'll let you read the EULA to enable you to do this. Jim wrote: > This afternoon I run a flow (ISE 8, Linux) and got in the log a warning > message. The word 'Warning' was an hyper link so I clicked on it > hopping to get a more detailed description of the warning. > > Few seconds later I was surprise to find myself in Xilinx site in a > page that displays the full path of the file I compiled. The path > included sensitive information such as my name, the name of my employer > and the code name of the project I was working on. > > Xilinx, please be more sensitive to the privacy of your customers. > > JimArticle: 103061
The amount of web linkage is getting very annoying. Personally I block all requests with my firewall and run some machines internet isolated but this does lead to occasional other issues as the tools are beginning to assume the connection is always there to web. Question is - how long until license codes for software rely on a web access for authorisation? John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Jim" <cairosearch@gmail.com> wrote in message news:1148540842.709080.19670@u72g2000cwu.googlegroups.com... > This afternoon I run a flow (ISE 8, Linux) and got in the log a warning > message. The word 'Warning' was an hyper link so I clicked on it > hopping to get a more detailed description of the warning. > > Few seconds later I was surprise to find myself in Xilinx site in a > page that displays the full path of the file I compiled. The path > included sensitive information such as my name, the name of my employer > and the code name of the project I was working on. > > Xilinx, please be more sensitive to the privacy of your customers. > > Jim >Article: 103062
On a sunny day (Thu, 25 May 2006 01:07:48 -0700) it happened Ron <News5@spamex.com> wrote in <mBddg.484$qy5.339@fe05.lga>: >Jim wrote: >> Few seconds later I was surprise to find myself in Xilinx site in a >> page that displays the full path of the file I compiled. The path >> included sensitive information such as my name, the name of my employer >> and the code name of the project I was working on. > > >Hi Jim, > >If true that's a horrible thing for them to do, but remember that what >you see in your browser window resides on your own computer. I'm no web >guru, but it might be possible that the Xilinx website generates Dynamic >HTML (or Javascript, etc) that is interpreted by your browser and used >to create what you see your screen without actually transferring any >sensitive information to Xilinx. > >For example, when they dynamically create a web page for your browser, >they might send a reserved environment variable name instead of the real >path (for example), which your browser then renders as the actual >absolute path. > >Perhaps a Xilinx rep could clarify? > >Ron Just run snort (packet sniffer) snort -i eth0 -v -d > test.txt Thne grep for your project's codename in grep my_secret_project_name test.txt If it shows anything move to Altera.Article: 103063
On a sunny day (Thu, 25 May 2006 10:30:29 +0100) it happened "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in <1148549430.36769.0@iris.uk.clara.net>: >The amount of web linkage is getting very annoying. Personally I block all >requests with my firewall and run some machines internet isolated but this >does lead to occasional other issues as the tools are beginning to assume >the connection is always there to web. Question is - how long until license >codes for software rely on a web access for authorisation? Or worse, as Billy Windows long time ago suggested: The tool (applictation) will run on the server. So you upload your design.... secure link of course ;-) It has no quite happened that way, although some movies and audio sites try hard. Maybe you then simply pay for access time to the tools. Solves any update problem too.Article: 103064
Nial Stewart wrote: > <roiavidan@gmail.com> wrote in message news:1148539184.893813.216500@u72g2000cwu.googlegroups.com... > > Hello everyone, > > > > I am trying to program an Altera Cyclone (EP1C20) device, which comes > > with the NiosII processor already in it, using the Quartus 5.0 > > software. > > My connection to the board is via the JTAG connection. > > > > When programming, I get no errors from the Quartus software, but > > immediately after programming has been completed, the board resets and > > starts the Nios system again, as if nothing happened. > > > > What am I doing wrong? > > > Is this a NiosII design of your own targeted at the Altera Nios eval > board? This is a design of my own not related in any way to NiosII. For the sake of testing, I also tried to program a simple blinking led design, and got the same result. > > If so then the config prom has a line from the FPGA, reconfig_req, that > allows any Nios to request a reconfiguration. You need to set this > permanently high (and assign it to the correct pin). How do I do that? is it a jumper or a Quartus setting or what? > > > Nial. > > > > ---------------------------------------------------------- > Nial Stewart Developments Ltd Tel: +44 131 561 6291 > 42/2 Hardengreen Business Park Fax: +44 131 561 6327 > Dalkeith, Midlothian > EH22 3NU > www.nialstewartdevelopments.co.ukArticle: 103065
Hi Nicky, Sending configuration words using Impact is possible however I don't think this is the way to go. If you did want to try this use an rbt file instead of a bit file (Its one of the bitgen options in ISE). Using this approach I can see how you'd send the readback configuration instructions but can't see how you'll then read the frame data (I don't think impact will support this). I've never tried this approach but would be interested to know if it yields any success. My suggestion would be to start off using the xilinx xtclsh program, a library is provided with ChipScope called tcljtag.tcl (You'll need a ChipScope license). This provides a high level access to the JTAG chain and is well documented in the ChipScope manual. Using this will however mean you'll need to know a bit about JTAG and embed your configuration instruction words in with JTAG instructions. If getting ChipScope isn't an option perhaps you should try something like jbits (free download from Xilinx) I'm not sure if the 1000e is supported. Its been a while since I looked at jbits but I'm guessing this option won't be pain free unless your board and FPGA are directly supported by the download. Their is also software called JHDL which provides readback capability again I'm not sure about board and FPGA support. I hope this is helpful, Vivian -- Sandbyte harbinxiaoting@hit.edu.cn wrote: > hi all, > I have a trouble in reading-back a frame of xcv1000e.According to > xapp138,139,151,I wrote a .bit file and download it into FPGA via > iMPACT.It seems to be successful, but I can't get the data back from > TDO.I wander if there is something wrong with my operations.My .bit > file is shown bellow: AA99 5566 > 3000 2001 > 0000 0000 > 3000 8001 > 0000 0004 > 2800 6001 > 1/Do I have to add some starting bits and end bits to my .bit file? > 2/what kind of .bit file format I can use to download my instructions? > 3/Is there anybody who has a successful experience about xapp > 138(readback via JTAG)? > > Any imformation about readback is welcome! > many thanks! > > Nicky >Article: 103066
>> > I am trying to program an Altera Cyclone (EP1C20) device, which comes >> > with the NiosII processor already in it, using the Quartus 5.0 >> > software. >> > My connection to the board is via the JTAG connection. >> > >> > When programming, I get no errors from the Quartus software, but >> > immediately after programming has been completed, the board resets and >> > starts the Nios system again, as if nothing happened. >> > What am I doing wrong? >> Is this a NiosII design of your own targeted at the Altera Nios eval >> board? > > This is a design of my own not related in any way to NiosII. > For the sake of testing, I also tried to program a simple blinking led > design, and got the same result. Are you using the NiosII development board to test your design? What did you mean by "which comes with the NiosII processor already in it"? If so, then the FPGA configuration is controlled by a small CPLD. When the board boots up I think this looks for the presence of several images in flash, picks one then configures the FPGA. There's a line from the FPGA to this config controller, called reconfigreq_n which allows a Nios to cause the FPGA to be re-configured. If you don't drive this inactive then as soon as your design boots up the FPGA will go through a re-configuration and one of the valid Nios images will be loaded. >> If so then the config prom has a line from the FPGA, reconfig_req, that >> allows any Nios to request a reconfiguration. You need to set this >> permanently high (and assign it to the correct pin). > > How do I do that? is it a jumper or a Quartus setting or what? You need to add an output to your design (call it anything you want), set it high and assign it to the correct pin. On the CycloneII board with the EP2C35 it's pin AA14. Nial ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 103067
Jan Panteltje wrote: > On a sunny day (Thu, 25 May 2006 10:30:29 +0100) it happened "John Adair" > <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in > <1148549430.36769.0@iris.uk.clara.net>: > >> The amount of web linkage is getting very annoying. Personally I block all >> requests with my firewall and run some machines internet isolated but this >> does lead to occasional other issues as the tools are beginning to assume >> the connection is always there to web. Question is - how long until license >> codes for software rely on a web access for authorisation? > > Or worse, as Billy Windows long time ago suggested: > The tool (applictation) will run on the server. > So you upload your design.... secure link of course ;-) > > It has no quite happened that way, although some movies and audio sites > try hard. > > Maybe you then simply pay for access time to the tools. > Solves any update problem too. That, of course, is called "time sharing", and is what we used 30 years ago, before PCs arrived. Back to the future...Article: 103068
On a sunny day (Thu, 25 May 2006 03:11:39 -0800) it happened David R Brooks <davebXXX@iinet.net.au> wrote in <44759173$0$3638$5a62ac22@per-qv1-newsreader-01.iinet.net.au>: >Jan Panteltje wrote: >> On a sunny day (Thu, 25 May 2006 10:30:29 +0100) it happened "John Adair" >> <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in >> <1148549430.36769.0@iris.uk.clara.net>: >> >>> The amount of web linkage is getting very annoying. Personally I block all >>> requests with my firewall and run some machines internet isolated but this >>> does lead to occasional other issues as the tools are beginning to assume >>> the connection is always there to web. Question is - how long until license >>> codes for software rely on a web access for authorisation? >> >> Or worse, as Billy Windows long time ago suggested: >> The tool (applictation) will run on the server. >> So you upload your design.... secure link of course ;-) >> >> It has no quite happened that way, although some movies and audio sites >> try hard. >> >> Maybe you then simply pay for access time to the tools. >> Solves any update problem too. >That, of course, is called "time sharing", and is what we used 30 years >ago, before PCs arrived. Back to the future... Not all old ideas are bad.... Fire is also an old idea. There are more.Article: 103069
Thanks. I've actually turned it around on them and asked them to tell me what the cheapest FX device they can give me in 100K quantity. We'll see what they come back with. -Clark "Peter Alfke" <peter@xilinx.com> wrote in message news:1148513951.238065.141730@g10g2000cwb.googlegroups.com... > Hi, Clark > The difference between the two prices is very large, as you correctly > stated. > But you never provided details for the device you want, obviously not > the simplest and cheapest.: > What speed grade, what package, what temperature grade? > These factors can each raise the price. > But I still think the $112 quote looks like an attempt not to bid for > your business. > BTW, no EasyPath for a device this small. > In order to achieve a lower price, the device must be bigger, so that > Xilinx has a way to save cost through higher yield and shorter test > time. For small devices, that saving is insignificant (for large die > the saving is substantial). > > Peter Alfke >Article: 103070
Hans Hübner wrote:
> LISP Hardware breakout group: http://vaxbusters.org/workshop/
I think instead of implementing the SECD machine, like described at
http://vaxbusters.org/workshop/secd.xml (BTW: in Internet Explorer there
are no scrollbars), with bytecodes and a compile step, it would be more
interesting to implement an interpreter within a FPGA, like I've started to
describe at http://www.frank-buss.de/lispcpu/
But using some ideas of LispKit is a good idea. First I'll implement it in
software and then translating it to VHDL. Below is a first implementation
of an interpreter for a modified version of LispKit lisp. Currently it is
non-lazy (I think for the first version of the FPGA implementation this is
easier, too). I've started with the description of the interpreter from the
the book "Functional Programming" by Peter Henderson, page 120/121, but
modified the syntax a bit to make it easier for people who know alreay
Common Lisp:
- let and letrec uses a syntax more like Common Lisp
- numbers needs not to be quoted
And expressions are evaluated like when entered in the REPL, the expression
needs not to return a callable function.
The next step will be to implement a more hardware oriented simulation of
the interpreter (with my own memory management and GC, e.g. like
implemented in the original Pascal implementation of the SECD machine at
ftp://ftp.comlab.ox.ac.uk/pub/Packages/LispKit/ ).
#+:Lispworks (editor:setup-indent "letrec" 2 0 2)
(defun test ()
(loop for (result expression) in
'(;; some simple tests
(nil nil)
(1 1)
(3 (+ 1 2))
(9 (let ((square (lambda (x) (* x x))))
(square 3)))
;; creating a list
((0 1 2 3 4 5)
(letrec ((i (lambda (n)
(cons n
(if (< n 5)
(i (+ n 1)))))))
(i 0)))
;; creating primes
((2 3 5 7 11 13 17 19 23 29 31 37 41 43 47)
(letrec
((reverse
(lambda (l)
(letrec ((reverse-impl
(lambda (l acc)
(if (atom l)
acc
(reverse-impl (cdr l)
(cons (car l) acc))))))
(reverse-impl l))))
(is-prime (lambda (p l)
(let ((divisor (car l)))
(if divisor
(if (= (rem p divisor) 0)
nil
(is-prime p (cdr l)))
p))))
(create-primes (lambda (n)
(letrec ((primes-impl
(lambda (test l)
(let ((l (if (is-prime test l)
(cons test l)
l)))
(if (< test n)
(primes-impl (+ 1 test) l)
l)))))
(reverse (primes-impl 2 '()))))))
(create-primes 50))))
do (assert (equalp result (secd expression)))))
(defun secd (expression)
(let ((n '())
(v '()))
(secd-eval expression n v)))
(defun secd-eval (e n v)
(when e
(let ((unary-functions '(car cdr atom))
(binary-functions '(cons eql + - * / rem < <= > >= =)))
(cond
((numberp e)
e)
((atom e)
(secd-assoc e n v))
((member (car e) unary-functions)
(funcall (car e)
(secd-eval (cadr e) n v)))
((member (car e) binary-functions)
(funcall (car e)
(secd-eval (cadr e) n v)
(secd-eval (caddr e) n v)))
((eql (car e) 'quote)
(cadr e))
((eql (car e) 'if)
(let ((e1 (cadr e))
(e2 (caddr e))
(e3 (cadddr e)))
(secd-eval (if (secd-eval e1 n v) e2 e3) n v)))
((eql (car e) 'lambda)
(cons (cons (cadr e)
(caddr e))
(cons n v)))
((eql (car e) 'let)
(let ((y (secd-vars (cadr e)))
(z (secd-eval-list (secd-exprs (cadr e)) n v)))
(secd-eval (caddr e) (cons y n) (cons z v))))
((eql (car e) 'letrec)
(let* ((y (secd-vars (cadr e)))
(v2 (cons nil v))
(z (secd-eval-list (secd-exprs (cadr e)) (cons y n) v2)))
(secd-eval (caddr e) (cons y n) (rplaca v2 z))))
(t (let ((c (secd-eval (car e) n v))
(z (secd-eval-list (cdr e) n v)))
(secd-eval (cdar c)
(cons (caar c)
(cadr c))
(cons z (cddr c)))))))))
(defun secd-vars (d)
(when d
(cons (car (car d))
(secd-vars (cdr d)))))
(defun secd-exprs (d)
(when d
(cons (car (cdr (car d)))
(secd-exprs (cdr d)))))
(defun secd-assoc (x n v)
(if n
(if (member x (car n))
(secd-locate x (car n) (car v))
(secd-assoc x (cdr n) (cdr v)))
(error "variable not found: ~a" x)))
(defun secd-locate (x l m)
(if (eql x (car l))
(car m)
(secd-locate x (cdr l) (cdr m))))
(defun secd-eval-list (l n v)
(when l
(cons (secd-eval (car l) n v)
(secd-eval-list (cdr l) n v))))
--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Article: 103071>>That, of course, is called "time sharing", and is what we used 30 years >>ago, before PCs arrived. Back to the future... > >Not all old ideas are bad.... >Fire is also an old idea. >There are more. So is lighting one by rubbing sticks. Good luck. I don't want to return to what we did 30 years ago. Those of us who had to deal with 1Mb of memory with multiple power rails in three fan-cooled cabinets (and processors in eight) are glad to see the end of them and all the hassle. There's no point pretending that processing power and RAM are still expensive. They're cheap. They're very cheap. That's why we now have it locally. Do you want a server to render your graphics images, too? Or maybe you'd prefer to do everything on a command-line? Get real.Article: 103072
On a sunny day (Thu, 25 May 2006 14:14:16 +0100) it happened MikeShepherd564@btinternet.com wrote in <slab725a1q4ntho7f45uq7ad04hp6fpk0c@4ax.com>: >>>That, of course, is called "time sharing", and is what we used 30 years >>>ago, before PCs arrived. Back to the future... >> >>Not all old ideas are bad.... >>Fire is also an old idea. >>There are more. > >So is lighting one by rubbing sticks. Good luck. > >I don't want to return to what we did 30 years ago. Those of us who >had to deal with 1Mb of memory with multiple power rails in three >fan-cooled cabinets (and processors in eight) are glad to see the end >of them and all the hassle. > >There's no point pretending that processing power and RAM are still >expensive. They're cheap. They're very cheap. That's why we now >have it locally. Do you want a server to render your graphics images, >too? Or maybe you'd prefer to do everything on a command-line? Get >real. I think you mis the point. Now, to do the synthesis, many people have to buy advanced (very fast) hardware. A FPGA vendor could team up with say (for example) Sun, and you would use their server farm. The FPGA vendor would take care of all updates and software related problems transparent to the customer. Think how many man hours you spend installing, updating, finding install problems, with the XST, things you tried to get it working. And then multiply that by the amount of people using it. At the current cost of manhours, and now you do not need the latest hardware, no new software purchases, site licenses made simple, there could well be a financial advantage. ESPECIALLY if the server farm was significantly faster then the normal high end PC used by (for example) you today. That is also [saving] hours (waiting for a design to finish). Waiting for software to ship, etc etc. If I really listen to your blunt remarks I almost think you have no clue about software at all (regarding the graphics remark). There is only very little data to be transferred (listing and bitfile returned, some graphs, really not a lot), but a lot of calculations to be done by the software. The perfect setup for a client server model. The FPGA vendor could then also team up with other companies to make the best tools availabe at all times to all. That would 4 sure make thing a lot better to work with. There actually exists a PCB manufacturer (cannot remember the name of that company) that lets you do boards that way (with their own soft). People seem to be satisfied with that. So, save time, money, have the latest bugs fixed all the time, save disk space, hardware, no illegal copy problems for the FPGA tool vendor, work faster, it would make sense to work it out in detail.Article: 103073
Hi, I've been experimenting using the FPGA Editor to modify ChipScope monitor/trigger signals and reduce the requirement to do a full P&R. The ILA command (in FPGA Editor) appears to have a bug which adds REV signals to the sampling Flip Flops. These REV signals then result in incorrect results being reported in the ChipScope Analyzer, however if the REV signals are removed (in the FPGA Editor) the correct results are reported. I've now used this approach successfully on a several Virtex 4 and Spartan 3 designs. The issues I've had have left me suspicious of this technique, but I still remain hopeful. I was wondering if anyone else has used this approach and with what success? Thanks, Vivian -- SandbyteArticle: 103074
Hello, Please excuse me posting a presumably lame question here, but despite a rather thorough search I can't find answers to two bothering questions. 1. I understand that when, say, a D flop's input changes along with the arrival of the active clock edge, the flop is likely to go metastable. But assuming it does, what will happen when no timing violations occur on the next active clock edge (i.e. the flop's input is ready and steady). Will the flop remain metastable or will its output settle to the valid input? 2. What happens if a metastable flop's output is presented to the following (in a chain) flop's input? Will it go metastable too? Or is its action undefined? Regards, Tomasz Dziecielewski
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