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I'm using an xc2vp70-ff1704-7. The delay from the net is 4.052 ns, the total delay is 4.692 ns. Matt Peter Alfke wrote: > What device, and what delay at fanout=32? > Peter AlfkeArticle: 103101
Hello All, We are looking into the Xilinx PCI Express Endpoint Logicore to develop a high speed serial link on the Xilinx ML321 development board (v2pro rocketio). Is there a daughter card available to add PCIe functionality on the board. We would like to be able to connect a PC w/ a PCIe connection to the board. I had a look at the PCI-SIG Compliance Load baord for this application, but I'm not sure if I'm on the right track. Thanks, EshwarArticle: 103102
Matt Blanton wrote: > I'm using an xc2vp70-ff1704-7. The delay from the net is 4.052 ns, the total > delay is 4.692 ns. A fanout of 32 shouldn't be excessive. You would probably benefit from a little floorplanning. If you constrain this logic to a small area, the routing delays will decrease. Look for 'area group' in the constraints guide --- Joe Samson Pixel VelocityArticle: 103103
Unfortunately this signal is going to several modules which are in different parts of the chip. Thanks for the suggestion though. Matt Joseph Samson wrote: > Matt Blanton wrote: >> I'm using an xc2vp70-ff1704-7. The delay from the net is 4.052 ns, the >> total delay is 4.692 ns. > A fanout of 32 shouldn't be excessive. You would probably benefit from a > little floorplanning. If you constrain this logic to a small area, the > routing delays will decrease. Look for 'area group' in the constraints > guide > > > --- > Joe Samson > Pixel VelocityArticle: 103104
V2pro rocket io is not PCIe compliant on the 'lock range' of the CDR so at least you need an external clock recovery circuit to be added - in short the answer is no, if you want PCIe functionality with Xilinx FPGA you should seek some other platform - as V2Pro is 2 families past the latest and greatest I dont think there will be any new things developed for it or for ML321 platform. AnttiArticle: 103105
Nial Stewart wrote: > >> > I am trying to program an Altera Cyclone (EP1C20) device, which comes > >> > with the NiosII processor already in it, using the Quartus 5.0 > >> > software. > >> > My connection to the board is via the JTAG connection. > >> > > >> > When programming, I get no errors from the Quartus software, but > >> > immediately after programming has been completed, the board resets and > >> > starts the Nios system again, as if nothing happened. > >> > What am I doing wrong? > > >> Is this a NiosII design of your own targeted at the Altera Nios eval > >> board? > > > > This is a design of my own not related in any way to NiosII. > > For the sake of testing, I also tried to program a simple blinking led > > design, and got the same result. > > > Are you using the NiosII development board to test your design? > Yes. I am using Nios development kit cyclone edition. > > What did you mean by "which comes with the NiosII processor already in it"? As soon as you plug the device to power, it configures itself as a nios processor. this is also confirmed by the nios manual which comes with the board. > > If so, then the FPGA configuration is controlled by a small CPLD. When the > board boots up I think this looks for the presence of several images in flash, > picks one then configures the FPGA. > This seems like what's happening. the safe mode led is on, btw. > There's a line from the FPGA to this config controller, called reconfigreq_n > which allows a Nios to cause the FPGA to be re-configured. If you don't > drive this inactive then as soon as your design boots up the FPGA will go > through a re-configuration and one of the valid Nios images will be loaded. > > > >> If so then the config prom has a line from the FPGA, reconfig_req, that > >> allows any Nios to request a reconfiguration. You need to set this > >> permanently high (and assign it to the correct pin). > > > > How do I do that? is it a jumper or a Quartus setting or what? > > You need to add an output to your design (call it anything you want), set it high > and assign it to the correct pin. On the CycloneII board with the EP2C35 it's > pin AA14. > I am using a Cyclone EP1C20 chip and not EP2C35 and I couldn't find where the reconfig_req is located in it. i have the pin list for that device, but I must say that I am not familiar with most of the acronyms used there. the previous device I used to work with was a Flex10k and it was way lot simpler to locate what I needed there. could you help me with the pin number that should be driven high in my design? > > Nial > > > ---------------------------------------------------------- > Nial Stewart Developments Ltd Tel: +44 131 561 6291 > 42/2 Hardengreen Business Park Fax: +44 131 561 6327 > Dalkeith, Midlothian > EH22 3NU > www.nialstewartdevelopments.co.ukArticle: 103106
I managed to get around the issue by manually inserting copies of the register containing the signal with the high fanout. This solves my initial problem but unfortunately doesn't explain why setting the max fanout wasn't working. Thanks to all that replied. Matt Matt Blanton wrote: > I want to constrain the max fanout for a particular net in my design. I am > using the XPS flow and the net I want to constrain is a BRAM address > signal > and is generate by xps, during platgen I suppose. I don't think I can > just go in and add attribute constraints to the system.vhd file in the > hdl/ directory because those files seem to be regenerate every time. How > can I constrain the fanout for this net? Thanks for any pointers. > > MattArticle: 103107
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Article: 103108Jan Panteltje wrote > A FPGA vendor could team up with say (for example) Sun, and you would > use their server farm. > The FPGA vendor would take care of all updates and software related > problems > transparent to the customer. > Think how many man hours you spend installing, updating, finding install > problems, with the XST, things you tried to get it working. > And then multiply that by the amount of people using it. That was the system we had at Sun Labs when I worked there a few years ago. And very productive it was, despite not having the zillion PC programs I supposedly rely on. The thin clients were activated by smart cards. When you had a problem you could take your smart card to the guru down the corridor and show her the exact screen with the problem on display. And when you wanted to work nearer home for a few hours you could take the smart card to a local Sun facility and pick up from exactly the point you left off.Article: 103109
Sanjay, I do not renember if this board handles PCI64/66. I can ask Hunt Engineering if you want. However, I am not really sure this is what you're looking for. This is a system I am throwing away for a few euros because I am tired of seing it sleep in my attick ! What exactly is it you are trying to do ? Those TIM fpga modules from Sundance are great but they are tied to the TIM std which may not be the best way to start playing around with fpgas. Modules from alpha-data are great and are PMC modules (meaning you can stick them in your PC easily or in any cPCI system) but they are expensive. Whatever it is I can point you to people from these companies if ever you are interested but I think that you should start of by describing your exact needs. Thanks, Rgds, John "fpgabuilder" <fpgabuilder-groups@yahoo.com> a écrit dans le message de news: 1148578538.513026.295340@g10g2000cwb.googlegroups.com... > John, > > The link does not clearly mention PCI 32/33 or PCI 64/66. Looks quite > similar to the one from http://www.4dsp.com/PCI.htm . > > What's your experience been with it? > > Thanks. > -sanjay >Article: 103110
Hello PPL, I would like to know what are the current implementations for the internal blocks inside a DSP48E. This of course applies to the new Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier (is it a booth?) as well as the 48 X 48 adder blocks? Thanks for any help JacquesArticle: 103111
John, I am just trying to make some windows/linux application talk to the FPGAs over PCI in an ATX motherboard. Not wanting to spend too much time getting the PCI hardware to work, I would like to have standard PCI bridge on the PCI board. Hopefully that also comes with any software drivers/API, etc. that I can call in my application to talk to the Logic inside the FPGA. So it is not something new... well software interfacing will be new to me. But thats where I would like to be as fast as possible. So I do not want to spend any time putting a PCI core into the FPGA and making sure the PCI timing is met. What kind of FPGAs are on the TIMs that you have? Thanks. -sanjayArticle: 103112
Jacques, I think you cannot expect an answer in a public forum like this. Part of the answer might divulge secrets that Xilinx tries to keep away from the competition. Some of it should be kept under wraps to reduce the support burden, for there are always smart people who then could poke around in the innards and cause great stress to our support organization. When I was Zilog Applications I found all those undocumented Z-80 instruction, and wanted to make them public. But I was told in no uncertain terms that that would not be in the interest of the company, since it might cause future compatability problems. My advice to you is to attend conferences and read papers where designers proudly talk and write (sometimes too much) about their achievements. Patents are also a good source of information, but you never know whether the patented idea really got implemented that way. The shorter answer to your question would be a question: Why do you want to know? Peter AlfkeArticle: 103113
Jacques, The actual implementation and circuits of our DSP48E is proprietary information. What has been published: http://www.xilinx.com/publications/xcellonline/xcell_52/xc_pdf/xc_v4topview52.pdf Austin jaxato@gmail.com wrote: > Hello PPL, > > I would like to know what are the current implementations for the > internal blocks inside a DSP48E. This of course applies to the new > Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier > (is it a booth?) as well as the 48 X 48 adder blocks? > > Thanks for any help > Jacques >Article: 103114
Mr. Andraka (and others), I am curious as to how you specify a single logic-layer in these high-speed designs. Do you explicitly specify the individual LUTs in an HDL, or can you code at a higher level and synthesize down to single-layer logic between flops? Thank you, Stephen CravenArticle: 103115
Hi Peter, Thanks for your prompt reply to my post. I have been asked by my professor to write a comprehensive report on the various arithmetic building blocks which exists in the FPGA world. So here I am probing here and there. But the thing is that it is most probably a "classic" implementation that Xilinx is using or maybe with some adaptation. If such information is too much asking, then I will most probably use a N/A in my report. I am just starting though and I will try to dig deeper into papers, in particular, those dealing with the Virtex-4, as I am sure that most of the DSP48E is based on its predecessor. JacquesArticle: 103116
Jacques, OK. That is fair. If you read the article I sent you, it will tell you that the IP for V4 was licensed from Arithmatica. If you then go to their website, you may get some idea of what they are doing, although you will not know what we did with their IP, you can probably assume we made it work well (which we did). I can not say more about V5, as it has not been printed anywhere (yet). Austin jaxato@gmail.com wrote: > Hi Peter, > > Thanks for your prompt reply to my post. I have been asked by my > professor to write a comprehensive report on the various arithmetic > building blocks which exists in the FPGA world. So here I am probing > here and there. But the thing is that it is most probably a "classic" > implementation that Xilinx is using or maybe with some adaptation. If > such information is too much asking, then I will most probably use a > N/A in my report. I am just starting though and I will try to dig > deeper into papers, in particular, those dealing with the Virtex-4, as > I am sure that most of the DSP48E is based on its predecessor. > > Jacques >Article: 103117
On 25 May 2006 14:05:39 -0700, jaxato@gmail.com wrote: >Hello PPL, > >I would like to know what are the current implementations for the >internal blocks inside a DSP48E. This of course applies to the new >Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier >(is it a booth?) as well as the 48 X 48 adder blocks? First of all there is no RTL (one which gets synthesized anyway). Second I remember Xilinx licensing some IP from a high speed module generator company a while back. Their design methodology was a little more public.Article: 103118
John Adair wrote: > The amount of web linkage is getting very annoying. Personally I block all > requests with my firewall and run some machines internet isolated but this > does lead to occasional other issues as the tools are beginning to assume > the connection is always there to web. Question is - how long until license > codes for software rely on a web access for authorisation? Hopefully, that will never happen, as vendors will realise it will kill their business . ( I suppose some 'slow learners' will have to find out the hard way..) There was an interesting case IIRC, last year in europe, where a internet-connected machine in a lab, was breached and valuable information extracted - as in trade secrets/patent relevent stuff, not your usual email lists... now that's WAY above the normal nuisance level of So, there is if anything a _growing_ trend to disconnect design-lab machines from the NET, or have one Document-NET PC in the corner... Vendors that miss this trend, will get their fingers burnt. -jgArticle: 103119
Jan Panteltje wrote: > > Maybe you then simply pay for access time to the tools. > Solves any update problem too. but just imagine the version control nightmares from that (shudder)....! -jgArticle: 103120
Ben Jones wrote: > > It's a very interesting idea (I was thinking about this sort of model the > other day). Some of the barriers to adoption would be: > > (1) Privacy concerns - do you want your company's crown jewels stored on > someone else's server? I think vendors would have to guarantee not only an > encrypted link, but strongly encrypted storage for your files as well (and > only you have the key). I didn't now Xilinx et al tools, could swallow encrypted source files ? If they have to be decrypted to run the tools, then that makes a joke of anyones' "strongly encrypted storage" claims ? Plus some error messages are cryptic enough now, imagine what they'd be like over this system.... ? -jgArticle: 103121
Jacques, the days of "normal textbook design methods" for such highly-tuned circuits are definitely passee. No more simple adder trees, or -heaven forbid- ripple-carry adders. It's all far more sophisticated, because there is this enormous pressure to achieve high performance, while keeping power low. May make your assignment more difficult, but it gives the user better results. Peter AlfkeArticle: 103122
One question... Is it correct to say that the A+ and Ax technology was used in the DSP48, as the V4's DSP is CellMath based? I am confident that Xilinx improvements were at balancing the power to speed ratio by adapting the technology to 90nm. JacquesArticle: 103123
Hi! I have a question regarding the VHDL's "after" keyword. I've read that it is not synthesizable but only used for simulation and I was wondering if this is true for real-world programs. I'm working with Xilinx Spartan-2 (so it's Xilinx's systhesizer in question) and I've connected a soft processor to an external memory chip via my VHDL memory controller but the design isn't working if I deselect CS at the end of a cycle. I attempted to create delays using afters, ie. "CS <= '0' after 12ns;", but that doesn't seem to be working. I could be I misinterpreted the memory's datasheet but these afters are bugging me. So, will a statement like "CS <= '0' after 12ns;" cause 12ns delay in the FPGA circutry or not? And if not, how could I create a delay? Thanx! - R.Article: 103124
after is only simulation you must use some clocked process from some clock to generate the required timing antti
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