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Messages from 10575

Article: 10575
Subject: BiPolar Prom 2 PLD
From: Mike Panson <mikep@sgi.net>
Date: Tue, 02 Jun 1998 01:19:39 GMT
Links: << >>  << T >>  << A >>
Has anyone found an easy way to convert BiPolar PROM images (like the
N82S185, etc) to
simple PLD such as 16V8 without doing a manual look up table and typing
in the data?

I am just a lazy, cheep designer and know someone out there has come up
with an easy way to replace the old TTL Proms that are $$ and getting
tougher to find.  It seems like to me that a $0.90 16V8 should replace
the $4-5 PROM.

Any help ??

Thanks,

Mike

Article: 10576
Subject: HELP: Bidirectional I/O's in state machine
From: Vo To <vto@polymail.calpoly.edu>
Date: Tue, 02 Jun 1998 07:32:53 GMT
Links: << >>  << T >>  << A >>
Hello,


I've been trying to configure the bidirectional I/O of the XC4025 to
communicate with another chip. Somehow the data read from the
bidirectional pins is not correct --bad data is being read.

The way I'm inferring bidirectional ports is within a state machine, but
I'm not sure if it's done correctly. The only example of inferring a
bidirectional is from this example from XILINX:


-----------------------------------------------------------------------------------

entity bidir_infer is
    port (DATA :       inout STD_LOGIC_VECTOR(1 downto 0);
   READ_WRITE :  in    STD_LOGIC
   );
end bidir_infer;

architecture XILINX of bidir_infer is
   signal LATCH_OUT : STD_LOGIC_VECTOR(1 downto 0);
begin
    process(READ_WRITE, DATA)   begin
        if (READ_WRITE = '1') then
            LATCH_OUT <= DATA;
        end if;
    end process;

    process(READ_WRITE, LATCH_OUT) begin
        if (READ_WRITE = '0') then
            DATA(0) <= LATCH_OUT(0) and LATCH_OUT(1);
            DATA(1) <= LATCH_OUT(0) or LATCH_OUT(1);
        else
             DATA(0) <= 'Z';
             DATA(1) <= 'Z';
        end if;
    end process;
end XILINX;
------------------------------------------------------------------------------------



By the way, when I compile this example in Foundation Express, two
warning appears:
    1) Latch inferred in design 'bidir_infer' read with
'hdlin_check_no_latch'. (HDL-307)
    2) The pin '/bidir_infer/C0/Z[0]' is not connected to any net.
(FE-CHECK-1);



Anyway, do you know the correct (or working) way to infer a
bidirectional within a state machine?
Thanks for your help.


-Vo To



Article: 10577
Subject: VHDL, Processor Design, 3D Graphics, to 35k, Cambridge, UK - ECM
From: ECM Selection Ltd <vanessa@ecmsel.demon.co.uk>
Date: Tue, 2 Jun 1998 09:59:41 +0100
Links: << >>  << T >>  << A >>
Subject: Ref:n.8682 - VHDL, Processor Design, 3D Graphics, to35k,
Cambridge, UK

This innovative company develops state of the art 3D Graphics
technology, recently producing the worlds first ray-tracing hardware.

This is an opportunity for a high calibre Lead Chip Designers to work
on new 3D Graphics Hardware Design.

With a good degree you will have at least 3 years real word experience
and skills in:

Processor Design
VHDL
400K+ gates sub 0.8 micron

 

For further information on ECM and to search our ONLINE VACANCY DATABASE 
visit  http://www.ecmsel.co.uk.

Please contact us by Email: topjob@ecmsel.co.uk.

Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB
Phone: 01638 742244                             Fax: 01638 743066
Article: 10578
Subject: VHDL, 3D Graphics, Embedded Systems, to 35k, Cambridge, UK - ECM
From: ECM Selection Ltd <vanessa@ecmsel.demon.co.uk>
Date: Tue, 2 Jun 1998 10:00:11 +0100
Links: << >>  << T >>  << A >>
Subject: Ref:n.8683 - VHDL, 3D Graphics, Embedded Systems, to35k,
Cambridge, UK

This innovative company develops state of the art 3D graphics
technology, recently producing the world's first ray-tracing
hardware.

This is a new position for an OEM Product Developer/Hardware Engineer
to work with external consultants on the design of new products using
the company's 3D Hardware products.

With a good degree you will have skills in

- high performance computing
- embedded product design
- VHDL circuit simulation
- motherboard design
- experience of managing/working with external consultants
- 3+ years real world experience

 

For further information on ECM and to search our ONLINE VACANCY DATABASE 
visit  http://www.ecmsel.co.uk.

Please contact us by Email: topjob@ecmsel.co.uk.

Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB
Phone: 01638 742244                             Fax: 01638 743066
Article: 10579
Subject: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
From: mpa@comlab.ox.ac.uk (Matt Aubury)
Date: 2 Jun 1998 11:17:21 GMT
Links: << >>  << T >>  << A >>
Tim Tyler (tim@BITS.bris.ac.uk) wrote:
> I'm interested in implementing one relatively complex and one very
> simple cellular automata on SRAM FPGAs.  I'd be interested to know how 
> much storage there is per gate on the type of Xilinx FPGAs typically used
> for such things.

Each CLB, which is essentially two 4-input look-up-tables, contains
two one-bit flip-flops. The LUTs can also be configured as RAM or ROM,
providing 16 bits of storage each. See http://www.xilinx.com for more
details.

> : The fundamental life cell uses around 5 CLBs, so without all the 
> : interfacing you could theoretically do 115 cells per clock cycle [snip]
> 
> That sounds pretty good.  I looked briefly at the Oxford Hardware
> Compilation Group's web site but didn't find any relevant details.
> Is there a diagram of the ~=5 gates anywhere?

Nope, since I'm working from a high-level language I'm haven't
previously looked at the mapping to CLBs. I've just tried to work out
how the Xilinx tools manage it, but I can't figure it out. The best I
can do is 11 4-input LUTs, but the Xilinx tools get 10 4-input LUTs,
and a depth of four. My solution consists of counting the population
of seven of the neighbours, getting a 2-bit result (which represents a
population of 1, 2, 3 or "some other") and combining this with the one
remaining neighbour and the current state, to get a new state. The 7
to 2 coding seems to need at least 5 full CLBs.

Matt
--
Matt Aubury
Oxford University Computing Laboratory, Hardware Compilation Group
Article: 10580
Subject: More Xilinx timing constraints
From: ems@see_sig.com (ems)
Date: Tue, 02 Jun 1998 15:48:07 GMT
Links: << >>  << T >>  << A >>
I've had this problem with Xilinx tech support for a couple of weeks,
but without any resolution; it's related to multiple clock domains on
a device.

When you've got a fairly high frequency device clock, you'll often
need to divide it down internally to generate a lower frequency clock
for slow logic. As an example, assume that I've got a 64Meg clock
(CLK15) for the fast bits of the device, and I divide it by 2, and
route the result through a BUFG, to get a 32Meg clock (CLK30) for the
rest of the device.

Now, at some point, a register which is clocked by CLK15 needs
some phase information from the slow bit of the circuit, and
therefore needs CLK30 combined into its logic. CLK30 could
go directly to a CE input, or it could be combined into the
logic function.

The simplest example has three FFs, ie. FFA, FFB, and FFC (see pic
below; you'll need a fixed-pitch font). All three are clocked on
CLK15. FFA generates the lower frequency clock as UCLK30, which goes
through a BUFG to generate CLK30 for the rest of the device.  FFB and
FFC are part of a circuit which has to cycle at CLK15, and the output
of FFB is connected, via some combinatorial logic, to the input of
FFC. However, FFC also requires CLK30 in its logic, and so CLK30 also
goes into the combinatorial logic to generate the data input for FFC.

My original timespecs for this circuit just had period specs for CLK15
and for CLK30. However, this doesn't work, since PAR doesn't realise
that FFC should cycle at 15ns, and the timing simulation fails.  This
is presumably because the CLK30 timespec forward traces to FFC, and
the analyser thinks that it's actually got 30ns for the inputs to FFC,
instead of 15ns.

One solution is to use UCLK30 (which isn't constrained) in the input
to FFC, instead of the constrained CLK30. This works ok and FFC then
cycles at 15ns. However, this isn't practical in my design, since the
fanout on UCLK30 is then too high and the routing delay puts it out of
spec (ie. CLK15 -> FFA -> UCLK30 -> FFC won't fit into 15ns).

I've also tried prioritising CLK15 and CLK30 so that CLK15 has a
higher priority than CLK30, but this also results in a failure (ie.
timing analyser reports no violations, but timing simulation fails
on a constrained path).

The only solution I've found is to explicitly identify *all* the data
sources to FFC (not just the ones originating at CLK30), specify
timegroups on all these sources, and then explicitly constrain all
these timegroups to 15ns. However, this is very tedious and error-
prone, since I have a lot of these F/Fs (ie. equivalent to FFC) and
they have a lot of sources.

If you've got this far, do you have any ideas/solutions/thoughts?

Thanks -

Evan (ems@riverside-machines.com)

======================================================================
                                                      
              FFA                                    
             ----- UCLK30    CLK30	                              
             |   |--------|>----------------------------------------
          ---|>  |	     |                      
          |  -----           |    		    
          |                  | &&& 		    
          |   FFB            --&&&&            	           FFC  
       	  |  -----     SRCB  &&&&&&&                      ----- DSTC
          |  |   |-----------&LOGIC&&---------------------|   |-----
          ---|>  |     SRCX   &&&&&&                   ---|>  | 
          |  -----     --------&&&&                    |  ----- 
  CLK15   |                                            |        
  ------------------------------------------------------

		 	     
(A) FAILS

NET CLK15 TNM = CLK15;
NET CLK30 TNM = CLK30;
TIMESPEC TS_CLK15 = PERIOD CLK15   15.6;
TIMESPEC TS_CLK30 = PERIOD CLK30   TS_CLK15 * 2;

(B) FAILS

NET CLK15 TNM = CLK15;
NET CLK30 TNM = CLK30;
TIMESPEC TS_CLK15  = PERIOD CLK15   15.6         PRIORITY 15;
TIMESPEC TS_CLK30  = PERIOD CLK30   TS_CLK15 * 2 PRIORITY 30;

(C) PASSES, BUT IMPRACTICAL

TIMEGRP UCLK30 = FFS(UCLK30);
TIMEGRP FFC    = FFS(DSTC);
TIMEGRP FFB    = FFS(SRCB);
TIMEGRP FFX    = FFS(SRCX);
... repeat dozens of times.....
TIMESPEC TS_CLK15_1 = FROM:UCLK30:TO:FFC: TS_CLK15;
TIMESPEC TS_CLK15_2 = FROM:FFB:TO:FFC:    TS_CLK15;
TIMESPEC TS_CLK15_3 = FROM:FFX:TO:FFC:    TS_CLK15;
... repeat dozens of times.....

======================================================================

Article: 10581
Subject: Re: More Xilinx timing constraints
From: Ed McCauley <edmccauley@bltinc.com>
Date: Tue, 02 Jun 1998 17:04:04 -0400
Links: << >>  << T >>  << A >>
Here's what might be a dumb-dumb work-around....

Duplicate FFA (a few times if needed) and use the duplicate's Q as
inputs to your additional logic.

You also might RLOC FFA and/or its duplicates to their loads.  Wastes a
little logic but routing/timing becomes a lot easier.

Another technique might be to use a end point (ala from
FASTFFS:TO:FASTFFS) timespec method.  If you've taken the training
class, the priority of the timespecs in in that section.  Period has a
lower priority than IGNORE and TO/FROM specs.


-- 
Ed McCauley
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0817
Article: 10582
Subject: Xilinx Foundation
From: "s.timm" <s.timm@fh-westkueste.de>
Date: Wed, 03 Jun 1998 01:27:55 +0200
Links: << >>  << T >>  << A >>
I have a problem with Foundation 1.4 from Xilinx.

I cant start the program. Every time messages of errors ocour if I try
to start the program. The messages are different; missing device;
PCM.EXE not found; differnt types of DLL  have errors; ...
My System is a Pentium 133; 64 MB RAM; HDD1 with 2GB and HDD2 with 12 GB
(exlusive for the cad-system)
The OS is WIN95B.

I have insall the OS and the software more times and it dosent help.


Has anyone a idea ?

S. Timm

Article: 10583
Subject: Re: Xilinx Foundation
From: Mike Panson <mikep@sgi.net>
Date: Wed, 03 Jun 1998 02:43:12 GMT
Links: << >>  << T >>  << A >>
s.timm wrote:

> I have a problem with Foundation 1.4 from Xilinx.
>
> I cant start the program. Every time messages of errors ocour if I try
>
> to start the program. The messages are different; missing device;
> PCM.EXE not found; differnt types of DLL  have errors; ...
> My System is a Pentium 133; 64 MB RAM; HDD1 with 2GB and HDD2 with 12
> GB
> (exlusive for the cad-system)
> The OS is WIN95B.
>
> I have insall the OS and the software more times and it dosent help.
>
> Has anyone a idea ?
>
> S. Timm

I had a problem installing it too; however, the messages I got while
installation from
CD ROM was a error writing to drive C.  Not having a problem with my
hard drive
with anything else, I suspected some unusual installation on Xilinx's
side.  I ended
up cranking down the performance of the CD and Hard drive in Windows95
under
the System Properties folder, Performance, Advanced Settings (reduce to
small cache),
and Trouble Shooting (disable all).

Once I did above, it installed OK, I then reset to warp speed, and the
Xilinx package
works great.  Additionally, Xilinx has a patch on their site to fix some
minor problems
with M1.4.

I don't know if the above will help, I know what a pain PC & WIN95 &
Apps can be.
Its worth a try.

- Mike

Article: 10584
Subject: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
From: John <jsmeltze@columbus.rr.com>
Date: Wed, 03 Jun 1998 01:15:53 -0400
Links: << >>  << T >>  << A >>


    I can relate, I completed a 5210 with M1 F1.3, half of the design
worked and half not. Of course the design simulated properly. I had to
wait till Feb. to get 1.4 since the fixes for 1.3 did not work. When I
finally got 1.4 the half of the design that didn't work did.... however
the half that originally work didn't. I have since converted all state
diagrams to schematic, and avoid them.

    The only thing I can tell you is to get all of the latest patches.
These are consistently being updated on their web page, even this week.
My last count was ~60 bugs in 1.4. I have been very displeased with
Xilinx help line, they take a week to respond. I have had much better
luck with my regions FAE.


Steve Mitchell wrote:

> I seem to recall that a while back there was a thread going on about
> the problems people were having with the Xilinx M1 tools and their
> 5200 family designs.  Well, I just received my Foundation Base Express
>
> M1.4 package, and I'm running into (probably) the same problems.
>
> I have a 5210 design that is currently on a production PCB that I
> developed with the old Foundation/Metamor/XACT 6.0.1 tools.  As it
> is on a production PCB, the pinout is fixed.  When I tried to run the
> same design through Foundation Express and M1.4 Design Manager, the
> design wouldn't map since Express assigned CLKIOB's to some signals
> whose pins (fixed) didn't contain CLKIOB's.  Unfortunately, the Base
> Express package doesn't allow the user to edit constraints in Express,
>
> so I have no backward compatibility route with the M1.4 tools.
>
> Also, when I removed the pin locking constraints, I could map the
> design,
> but it wouldn't route, indicating that I should use the next larger
> package.  However, the same XNF netlist routed with no problems in
> XACT
> 6.0.1.
>
> I could go on, but I'm not here to whine.  What I'd like to know is if
>
> anyone has resolved their problems with the M1 tools and their 5200
> designs,
> and what Xilinx has to say about them.  I've had my case open with
> their
> tech support for over a week, with no acceptable resolution.
>
> Thanks guys/gals.
>
> Steve Mitchell






Article: 10585
Subject: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
From: z80@ds2.com (Peter)
Date: Wed, 03 Jun 1998 10:31:56 GMT
Links: << >>  << T >>  << A >>

>    I can relate, I completed a 5210 with M1 F1.3, half of the design
>worked and half not. Of course the design simulated properly. I had to
>wait till Feb. to get 1.4 since the fixes for 1.3 did not work. When I
>finally got 1.4 the half of the design that didn't work did.... however
>the half that originally work didn't. I have since converted all state
>diagrams to schematic, and avoid them.
>
>    The only thing I can tell you is to get all of the latest patches.
>These are consistently being updated on their web page, even this week.
>My last count was ~60 bugs in 1.4. I have been very displeased with
>Xilinx help line, they take a week to respond. I have had much better
>luck with my regions FAE.

Why not just stay with XACT6.01 ?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10586
Subject: Example of 8051 codes to configure Xilinx fpga
From: damon <damon@larc.nasa.gov>
Date: Wed, 03 Jun 1998 08:48:33 -0400
Links: << >>  << T >>  << A >>
Hello all,
    I am trying to program the xilinx fpga  in a serial slave mode with
an 8051. Anyone knows where I can get an example of the 8051 codes that
read the Xilinx configuration data from the 8051's eprom and program the
Xilinx fpga ?

Thank you for your help,

Damon

Article: 10587
Subject: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
From: "smitch01" <smitchell@emergevision.com>
Date: Wed, 03 Jun 1998 13:00:39 GMT
Links: << >>  << T >>  << A >>
The question was posed  - why don't I stay with XACT 6.0.1 for my 5210
design
instead of trying to make M1.4 work.

I currently have HW working that uses the 5210, and for the next
version of my
HW I'd like to target the Spartan XCS20.  I can do some FPGA
development for my
next version HW on my current HW.  Since 6.0.1 doesn't support Spartan,
I need
to use M1.4.

I'm currently looking to have both installed on my machine.  A
cumbersome solution
indeed, but the only workable one to date.  I've actually gotten past
the tech support
at Xilinx and have talked to the prouct managers.  They don't instill
much hope in me
that the M1 tools will ever work well with the 5200 family.

Steve Mitchell


 This message sent via http://www.talkway.com/.  Surf Usenet!

Article: 10588
Subject: Foundation M1.4 functional simulation problems
From: dfrevele@li.net
Date: Wed, 03 Jun 1998 13:39:38 GMT
Links: << >>  << T >>  << A >>
I'm using M1.4 on a PC running NT4.0 and am having trouble with the initial
states of flip flops during functional (pre-route) simulation. I need some
flip flops to initialize to the set ('1') state in my SPARTAN design.

I have set the INIT=S property on some FDCE components, but they initialize to
'0' during function simulation. They work correctly after place and route
during a timing simulation. I know that there is a problem with the INIT
property not being passed down thru a macro for simulation, but I am modifying
the attribute on a primitive.

Here is what I have tried, none of which worked:
   - Uppercase S and Lowercase s for attribute value
   - Driving and not driving SimGlobalReset
   - Including and not including a Startup body (and driving GSR, GTS)
   - Enabling and Disabling "Global Reset" option in simulator
   - Set project type to 4000 series device

Any ideas? Has anyone gotten this simulation to work?

Thanks
Don Frevele

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Article: 10589
Subject: Re: Foundation M1.4 functional simulation problems
From: "Kim Hofmans" <kim.hofmans@barco.com>
Date: 3 Jun 1998 16:00:40 GMT
Links: << >>  << T >>  << A >>
Yes indeed, init=S doesn't work (as far as I know) during function
simulation.
Instead of a FDCE component, you should use a FDPE component.
It has the same function as a FDCE with init=s, but it works with a
functional
simulation.

Cheers,

Kim Hofmans
kim.hofmans@barco.com

dfrevele@li.net wrote in article <6l3jmq$718$1@nnrp1.dejanews.com>...
> I'm using M1.4 on a PC running NT4.0 and am having trouble with the
initial
> states of flip flops during functional (pre-route) simulation. I need
some
> flip flops to initialize to the set ('1') state in my SPARTAN design.
> 
> I have set the INIT=S property on some FDCE components, but they
initialize to
> '0' during function simulation. They work correctly after place and route
> during a timing simulation. I know that there is a problem with the INIT
> property not being passed down thru a macro for simulation, but I am
modifying
> the attribute on a primitive.
> 
> Here is what I have tried, none of which worked:
>    - Uppercase S and Lowercase s for attribute value
>    - Driving and not driving SimGlobalReset
>    - Including and not including a Startup body (and driving GSR, GTS)
>    - Enabling and Disabling "Global Reset" option in simulator
>    - Set project type to 4000 series device
> 
> Any ideas? Has anyone gotten this simulation to work?
> 
> Thanks
> Don Frevele
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/   Now offering spam-free web-based newsreading
> 
Article: 10590
Subject: Re: Foundation M1.4 functional simulation problems
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 3 Jun 1998 16:41:15 GMT
Links: << >>  << T >>  << A >>

Try using a "FDPE" instead of an "FDCE with the INIT=S"  It should give 
you the same compiled results, and the simulation should match what you 
desire.

Philip Freidin



In article <6l3jmq$718$1@nnrp1.dejanews.com> dfrevele@li.net writes:
>I'm using M1.4 on a PC running NT4.0 and am having trouble with the initial
>states of flip flops during functional (pre-route) simulation. I need some
>flip flops to initialize to the set ('1') state in my SPARTAN design.
>
>I have set the INIT=S property on some FDCE components, but they initialize to
>'0' during function simulation. They work correctly after place and route
>during a timing simulation. I know that there is a problem with the INIT
>property not being passed down thru a macro for simulation, but I am modifying
>the attribute on a primitive.
>
>Here is what I have tried, none of which worked:
>   - Uppercase S and Lowercase s for attribute value
>   - Driving and not driving SimGlobalReset
>   - Including and not including a Startup body (and driving GSR, GTS)
>   - Enabling and Disabling "Global Reset" option in simulator
>   - Set project type to 4000 series device
>
>Any ideas? Has anyone gotten this simulation to work?
>
>Thanks
>Don Frevele
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/   Now offering spam-free web-based newsreading


Article: 10591
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: lellis@my-dejanews.com
Date: Wed, 03 Jun 1998 17:06:58 GMT
Links: << >>  << T >>  << A >>
In article <35754620.638FBDC5@larc.nasa.gov>,
  damon <damon@larc.nasa.gov> wrote:
>
> Hello all,
>     I am trying to program the xilinx fpga  in a serial slave mode with
> an 8051. Anyone knows where I can get an example of the 8051 codes that
> read the Xilinx configuration data from the 8051's eprom and program the
> Xilinx fpga ?
>
> Thank you for your help,
>
> Damon
>
>

Take a look at XC9500 In-System Programming Using an 8051
Microcontroller at http://www.xilinx.com/xapp/xapp058.pdf

The code for this is at
for  PC    ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_pc.zip
or SunOS   ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_sn.tar.Z
or Solaris ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_sol.tar.Z
or HP      ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_hp.tar.Z

Hope this helps

Lee

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Article: 10592
Subject: Re: Example of 8051 codes to configure Xilinx fpga
From: z80@ds1.com (Peter)
Date: Wed, 03 Jun 1998 21:43:23 GMT
Links: << >>  << T >>  << A >>

Assuming you can write software at all, you don't need a code example.
Have a look at the slave serial mode in the Xilinx data book, and
implement that. It is trivial.

>Hello all,
>    I am trying to program the xilinx fpga  in a serial slave mode with
>an 8051. Anyone knows where I can get an example of the 8051 codes that
>read the Xilinx configuration data from the 8051's eprom and program the
>Xilinx fpga ?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 10593
Subject: LATTICE 2032 problems
From: John Chambers <johnc@ihr.mrc.ac.uk>
Date: Thu, 04 Jun 1998 08:56:30 +0100
Links: << >>  << T >>  << A >>
I've recently had a problem with Lattice ispLSI2032-80LJ parts no
programming correctly.  I could program them but not verify them. 
Changing for a 1016 or a different speed 2032 solved the problem.  Has
anyone else had trouble?
Article: 10594
Subject: Re: LATTICE 2032 problems
From: Benedikt Huber <bhuber@brd.de>
Date: Thu, 04 Jun 1998 10:26:48 +0200
Links: << >>  << T >>  << A >>
John Chambers schrieb:
> 
> I've recently had a problem with Lattice ispLSI2032-80LJ parts no
> programming correctly.  I could program them but not verify them.
> Changing for a 1016 or a different speed 2032 solved the problem.  Has
> anyone else had trouble?

Hi,

I had the same problem when I tried to program that chip using a
self-built download-cable from my PC. I had a microcontroller
running with a 4 Mhz xtal running on the same breadboard. The
Problem disappeared when I (temporarily) removed power supply 
from that oszillator. Blocking the supply lines with capacitors 
didn't help.
What was the speed type of your 2032?
Article: 10595
Subject: Re: LATTICE 2032 problems
From: Benedikt Huber <bhuber@brd.de>
Date: Thu, 04 Jun 1998 10:27:08 +0200
Links: << >>  << T >>  << A >>
John Chambers schrieb:
> 
> I've recently had a problem with Lattice ispLSI2032-80LJ parts no
> programming correctly.  I could program them but not verify them.
> Changing for a 1016 or a different speed 2032 solved the problem.  Has
> anyone else had trouble?

Hi,

I had the same problem when I tried to program that chip using a
self-built download-cable from my PC. I had a microcontroller
running with a 4 Mhz xtal running on the same breadboard. The
Problem disappeared when I (temporarily) removed power supply 
from that oszillator. Blocking the supply lines with capacitors 
didn't help.
Article: 10596
Subject: Announce: Free On-Line EDA Newsletter Release
From: APS <resp@associatedpro.com>
Date: Thu, 04 Jun 1998 07:13:45 -0400
Links: << >>  << T >>  << A >>
-------------------------------------------------
Quarter 2 98 Newsletter Release Announcement
-------------------------------------------------

The On Line APS EDA Quarterly is now available at:

http://www.associatedpro.com/Newsletter/2q98/NL_Q2_98.html

To subscribe to this and future releases just go to this web page:

http://www.associatedpro.com/aps_sub.html
--------------------------------------------------------------------------------

This issue features:

In this issue of the EDA Quarterly we discuss several topics. In our
VHDL discussion topic for this Quarter we discuss the use of  signed and

unsigned types.While this quarter's VHDL tip involves avoiding the
repetitive use of COMPONENT declarations by instead using the USE
statement.
***
In this issue's Prototyping Corner we discuss Direct Digital Synthesis,
and the APS-DDS-1 Module. This module is a complete high resolution
programmable clock oscillator in a 28 pin dip package. The module allows
programming frequencies from .5 Mhz to 30 Mhz in less than 1 hz
steps. The module can be programmed serially or in parallel.
***
In EDA Notable developments we highlight some of the latest developments
in the industry.  This issue's Interesting Newsgroup threads
discusses Random Number generators and Linear recursive Sequences.
***
NEW EDA HDL FPGA ON LINE BOOKSTORE !!  <-- Click here
***
The APS CD ROM which includes various examples, labs and test code for
using the X84 board, X208 board and our other APS products. The
new CD (which comes with every APS product)  includes a demo VHDL
simulator and VHDL synthesizer, with working examples.
***
The X84 and X208 online User's Guide is also available for download.
Both our ISA XILINX board offerings offer the ease of use of the PC ISA
bus for control and downloading of the XILINX image file. The X84 board
is a great low-cost platform , while the X208 offers higher gate count
FPGA, much more IO connections, a direct digital sythesized (DDS)
programmable clock option, SRAM option,  and a more complete software
support package. Both Kits come with schematics and VHDL example code.
The support pages for both the X84 and the X208 are shown
below.
***
X84 Support Page: http://www.associatedpro.com/x84/support/x84_sup.html
X208 Support Page:
http://www.associatedpro.com/x208/support/x208sup.html
***
The X Boards are also available with XILINX Foundation Software kits at
very reasonable prices. These kits are the full up Foundation Kits which

include Latest M1 router/Synopsis VHDL Compiler/ Schematic Capture/ PLD
Software/Parallel JTAG Cable VHDL Tutorial. Complete BASE
kits which include an FPGA test board are available from $329.00!!! More
details can be seen at:
***
XILINX Foundation Software:
http://www.associatedpro.com/found/prod/fndprod.html
***
If you wish to work with XILINX FPGAs with a microcontoller on board,
APS now sells the XESS family of CPLD and FPGA test boards which
come with an on board 8031 UController. Details of this board and
corresponding Student Lab Handbooks can be seen at the following pages:
***
XILINX XCESS CPLD and FPGA
Boards:http://www.associatedpro.com/XS/prod/XS.html
***
The Lucent based L84 board is also also highlighted. It's on board dual
DA and programmable Direct Digital Synthesizer as well as on board
SRAM make it a very practical and flexible board for FPGA projects and
algorithm testing.
***
http://www.associatedpro.com/l84/prod/L84prod.html
**
Our new ATMEL A-84 kits are now on line. The ATMEL kits come with a free
VHDL and VERILOG  synthesis TOOL called EVEREST, and
support the new ATMEL 40K series of FPGAs. The kits come complete with
router and synthesis (VERILOG and VHDL), a APS-A84 test board
with a 20K FPGA on board. The kits are selling for $350.00 which is an
outstanding value, and to top it all off, the A84 board is really just
the X84
board with a slight modification. What this means is that the A84 and
X84 can use either XILINX or ATMEL FPGAs!!!

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 10597
Subject: graphical edif writer
From: "Adam J. Elbirt" <aelbirt@viewlogic.com>
Date: 4 Jun 1998 13:53:40 GMT
Links: << >>  << T >>  << A >>
Could someone email me the proper syntax for using the Mentor graphical
EDIF writer (I believe it is called ESIWRITE).

Thanks.

Adam
-- 
Adam J. Elbirt
aelbirt@viewlogic.com
Article: 10598
Subject: PhD forum at DAC -- Update
From: soha@cs.washington.edu (Soha Hassoun)
Date: Thu, 4 Jun 1998 18:10:39 GMT
Links: << >>  << T >>  << A >>

Hi,
Below is a list of participants in the poster session associated with
the PhD forum at DAC.  

This session gives students the chance to preview their thesis work
and to receive feedback from members of the DA community.  The DA
community then will get a chance to review the latest and greatest in
academic research.

Please stop by and check it out.  Your participation would be appeciated.

Thank you.
Soha Hassoun

+------------------------------------------+------------------------------+
| Soha Hassoun				   | phone : 617 628 5000   	  |
| Assistant Professor			   |   	     ext. 5177	          |
| Dept. of Elec. Eng. & Computer Science   | fax   : 617 627 3220   	  |
| 161 College Ave.			   | e-mail: soha@eecs.tufts.edu  |
| Tufts University			   | web: www.eecs.tufts.edu/~soha|
| Medford, MA 02155			   |           	                  |
+------------------------------------------+------------------------------+

------------------------------------------------------------------------
                        Poster Session -- OPEN to ALL

                              Hosted by SIGDA

                      Tuesday, June 16, 1998, 7:00-9:00 p.m.
		      Room:  Golden Gate A, the SF Marriott


Discussion Sessions:
Wednesday, June 17, 1998, 6:00-7:30 p.m.   If you are interested in
participating in a focused discussion regarding any of the marked (*)
submissions, please send e-mail to daforum@cs.washington.edu

Visit www.cs.washington.edu/homes/soha/forum for more information.
------------------------------------------------------------------------

   -- *Julio Faura , E.T.S.I. Telecomunicacion, Universidad Politecnica de
     Madrid, Spain
        o Title:  Design and Implementation of Microprocessor-Based
          Mixed-Signal Dynamically Reconfigurable Architectures


   -- * Debabrata Ghosh, North Carolina State University
        o Title:  Synthesis of Equivalence Class Circuit Mutants and
          Applications to Benchmarking


   -- Silvina Hanono, Massachusetts Institute of Technology
        o  Title:  Retargetable Code Generation for Embedded Systems.


   -- *Frank Hsu, University of Illinois at Urbana-Champaign
        o Title:  High-Level Testability Analysis and Enhancement for
          Digital Systems


   -- *Hemang Lavana, North Carolina State University
        o T Title:   Internet-based Workflows: A Paradigm for Dynamically
          Reconfigurable Desktop Environments


   -- Tai-Hung Liu, The University of Texas at Austin
        o Title: Synthesis for Pass-Transistor Logic
        o Advisor:  Adnan Aziz


   -- Fahim Rahim-Sarwary,  University of Paris VI
        o Title: Compositional Model Checking, Application to VHDL with
          Computational Results


   -- * Kavita Ravi, University of Colorado
        o Title:  Efficient Techniques to Improve State Space Search in
          Formal Verification


   -- Shantanu Tarafdar, Cornell University
        o Title: Midas:  Using Data-Transfers and Floorplanning in
          High-Level Synthesis


   -- * Heinkel Ulrich , University of Erlangen
        o Title:   Timing and Behavior Specification and Validation
          Environment
------------------------------------------------------------------------




Article: 10599
Subject: Non-periodic clock
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 5 Jun 1998 00:16:53 GMT
Links: << >>  << T >>  << A >>
Gang:

I have to design a board that talks to a pre-existing processor
board.  It's actually pretty simple, if sorta wacky: the processor
board outputs a bunch of discrete bits, a clock, and various clock
enables.  If a clock enable is asserted, the bits it controls are
registered. Since there's a whole bunch of these bits, I'm going to
put the whole mess into a Xilinx part (probably a 9500 series) of
appropriate size, write fifteen or twenty lines of VHDL, and I'll be
done.  This is all pretty standard.  

With the following exception:

The clock doesn't run all the time: it is only asserted when some
bits are output and we need to latch them.

A little more detail: all of these bits, the enables and this clock
are generated from a state machine that has a 50ns tick.  For
example, if a 1 needs to be stored in one of these registers, the
hardware puts out a 1 on that data line.  50ns later, the clock line
is asserted for 50ns.  These outputs are registered to a 20MHz clock.

The question: does it really matter if the clock is aperiodic like
this?

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM


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