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Messages from 10800

Article: 10800
Subject: [Question] Xilinx Foundation FPGA Express..
From: shinwk@eolith.co.kr (Shin Woo Kyun)
Date: Sat, 20 Jun 1998 03:25:07 GMT
Links: << >>  << T >>  << A >>
Hi... 

I'm a rookie on FPGA Express. 

It's a very simple device to implement using schematic. but I'd like

 to use verilog.

My problem is how I can  express the Bidirection PAD on XilinxFPGA

like 74LS245  using verilog..



For example.......


input MSEL;
inout A;
inout B;

reg A;
reg B;

always @(MSEL or A or B )
	if(MSEL) A = B;
	else B = A;




that is compiled well.  But I can't  implement it on Xilinx.

Article: 10801
Subject: Re: Getting into using FPGAs
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 20 Jun 1998 10:09:53 -0700
Links: << >>  << T >>  << A >>
I would like to recommend The Programmable Logic Jump Station at
http://www.optimagic.com as a good place to start.  In specific, you may be
interested in our list of Frequently-Asked Questions at
http://www.optimagic.com/faq.html.

Some of the articles that appear on our site may also be useful.

An introduction to programmable logic and associated terms
http://www.optimagic.com/progsoup.html

An overview of programmable logic design software
http://www.optimagic.com/designsw.html

If you are just getting started, various vendors supply free or low-cost
versions of their software--most available for download over the web.  A
fairly comprehensive link of packages is available at
http://www.optimagic.com/lowcost.html.  You can also find books on the
subject at http://www.optimagic.com/books.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Christopher Fairbairn wrote in message <898297473.933147@Chaos.es.co.nz>...
>Hi,
>
>I would like to get into using FPGAs but I havn't really been able to find
a
>lot of good information about how to use them and what I need to program
>them etc.
>
>Could anyone suggest a web site etc that I could find out such information.
>This is primarly a hobby so I don't really want to be able to do anything
>flash and I cann't afford an expensive programmer etc.
>
>Thanks
>Christopher Fairbairn
>lgcl01@es.co.nz
>


Article: 10802
Subject: Control skew due to routing in Xilinx M1
From: richard@devidia.demon.co.uk (Richard J Warburton)
Date: Sun, 21 Jun 1998 13:46:07 GMT
Links: << >>  << T >>  << A >>

Okay, I'm using a 4kXL device, and want a way to control the skew
between a bunch of signals from FFS to PADS, all FFS are clocked from
the same clock.  I don't care what the delay is, but the skew between
the bunch of signals must be low (I want to specify).

The only way I have found of doing it at the moment is to specify a
TIMESPEC that the routing delay from FFS to PADS is kept v.small, but
this places a needless constraint on the already struggling PAR.

Any ideas?

Richard.
Article: 10803
Subject: Re: Control skew due to routing in Xilinx M1
From: Phil Hays <pdhays@sprynet.com>
Date: Sun, 21 Jun 1998 09:30:06 -0700
Links: << >>  << T >>  << A >>
Richard J Warburton wrote:
> 
> Okay, I'm using a 4kXL device, and want a way to control the skew
> between a bunch of signals from FFS to PADS, all FFS are clocked from
> the same clock.  I don't care what the delay is, but the skew between
> the bunch of signals must be low (I want to specify).

First, I would try to get the skew by design:
If you can make a copies of the registers in the IOBs you can cut your
skew down to the skew on the clock line plus the skew on the board,
maybe as low as a few 10's of ps.  If you have logic between the
registers and the pads this will not work directly, but if you can bring
in a second clock for just these IOBs you might be able to add registers
on all these outputs.

If you can't solve the problem by design:
Are you doing any floorplanning?  If not, this might be a good design. 
Using the .ucf file nail down the FFS, any logic between the FFS and the
IOBs, and the IOBs.  While Xilinx has a graphical floorplanner, it's in
beta and not ready for prime time yet.  Now you should be able to put a
tight timing constraint on these signals and have a hope of getting a
route on the rest.  You still need to think about the next two steps.

If all else fails, and I can think of a pile of reasons why not to do it
this way, there is syntax in the documentation on setting a maximum
skew.  I have never used it.

Warning: The delays that are used for par are worst case delays: minimum
voltage, maximum temperature and slow process.  It's quite possible that
you can meet your skew spec at these conditions and fail it at some
other condition.  

-- 
Phil Hays
"Irritatingly,  science claims to set limits on what 
we can do,  even in principal."   Carl Sagan
Article: 10804
Subject: Re: [Question] Xilinx Foundation FPGA Express..
From: jmcgibbon@aics.net
Date: Sun, 21 Jun 1998 17:12:14 GMT
Links: << >>  << T >>  << A >>
Synplicity codes this well into pads with obuft and ibufs.

module test(MSEL, A, B);
 input MSEL;
 inout A;
 inout B;
 wire A =  MSEL ? B : 'bz;
 wire B = !MSEL ? A : 'bz;
endmodule

John

On Sat, 20 Jun 1998 03:25:07 GMT, shinwk@eolith.co.kr (Shin Woo Kyun)
wrote:

>Hi... 
>
>I'm a rookie on FPGA Express. 
>It's a very simple device to implement using schematic. but I'd like
> to use verilog.
>My problem is how I can  express the Bidirection PAD on XilinxFPGA
>like 74LS245  using verilog..
>For example.......
>
>input MSEL;
>inout A;
>inout B;
>
>reg A;
>reg B;
>
>always @(MSEL or A or B )
>	if(MSEL) A = B;
>	else B = A;
>that is compiled well.  But I can't  implement it on Xilinx.
>

Article: 10805
Subject: Re: Control skew due to routing in Xilinx M1
From: richard@devidia.demon.co.uk (Richard J Warburton)
Date: Sun, 21 Jun 1998 17:52:53 GMT
Links: << >>  << T >>  << A >>

Phil,
     Thanks for your help, what you suggest is much of what should be
done anyway to ensure timing, and will be done when my design gets out
of development and into the debug/tweaking phase.  I just wondered if
there was a quick and easy way to group a bunch of nets and say what
the group skew would be due to logic paths and routing.  Since there
are commands to control ouput signals when they should arrive relative
to a clock edge, I thought it would be useful to specifiy a group
skew, rather than relative to a clock edge.

>First, I would try to get the skew by design:
>If you can make a copies of the registers in the IOBs you can cut your
>skew down to the skew on the clock line plus the skew on the board,
>maybe as low as a few 10's of ps.  If you have logic between the
>registers and the pads this will not work directly, but if you can bring
>in a second clock for just these IOBs you might be able to add registers
>on all these outputs.

I will analyze the timing and system again, and see if I can add extra
registers on the output and then lock them into the IOBs.  (There was
a reason I didn't do this to begin with though....can't remember
off-hand).

>If you can't solve the problem by design:
>Are you doing any floorplanning?  If not, this might be a good design. 
>Using the .ucf file nail down the FFS, any logic between the FFS and the
>IOBs, and the IOBs.

Since the design is still being developed I haven't yet done any
floorplanning, this stage will be done once I am happy with the
overall design and functionaility, then I can optimize all the timing.

>  While Xilinx has a graphical floorplanner, it's in
>beta and not ready for prime time yet.  Now you should be able to put a
>tight timing constraint on these signals and have a hope of getting a
>route on the rest.  You still need to think about the next two steps.
>
>If all else fails, and I can think of a pile of reasons why not to do it
>this way, there is syntax in the documentation on setting a maximum
>skew.  I have never used it.

The syntax for max skew is used to control the max skew on a
particular net, useful if you have already used all your global
buffers but still want to distribute a local clock.

Richard.
Article: 10806
Subject: Re: Foundation M1.4 functional simulation problems
From: richard@devidia.demon.co.uk (Richard J Warburton)
Date: Sun, 21 Jun 1998 18:05:51 GMT
Links: << >>  << T >>  << A >>
On Wed, 10 Jun 1998 15:59:30 +0200, THIEBOLT Francois
<thiebolt@irit.fr> wrote:

>I saw last day your news talking about SPARTAN serie; well my question
>is
>about bitstream configuration since i'm still unable to download xxx.bit
>using the // Xchecker cable, have you experienced such troubles or did
>you
>only use SPROM download ?

Have you tested the Xchecker with other devices?  I had a problem with
XChecker and Lab install of Alliance M1.4 tools, that it wouldn't
download xxx.bit files on certain devices, a patch from xilinx's web
site fixed this problem.

Richard.
Article: 10807
Subject: FPGA design tools for Xilinx and Altera on WinNT and Alpha
From: "Rick McBain" <rmcbain@istar.ca>
Date: Sun, 21 Jun 1998 19:10:29 GMT
Links: << >>  << T >>  << A >>
Are there any available? Or has anybody tried using !FX32 successfully with
Xilinx foundation or alliance series tools (or Altera's Max tools) (or any
FPGA tools)?

Regards,
Rick McBain
Senior Engineer
LMI DynaVision


Article: 10808
Subject: Re: VHDL testbench in Maxplus2
From: "Rick McBain" <rmcbain@istar.ca>
Date: Sun, 21 Jun 1998 19:27:39 GMT
Links: << >>  << T >>  << A >>
I guess we've all had problems with OrCad (my big one was a feature  for
creating heirachy via reuasable components - Orcad has since delared it a
bug and got rid of it! You can still do heirachy and reuasble components,
but I have to change all my blocks - argh).

Having used Viewlogic, Orcad, PCAD, Futurenet (then later Synario), and
foundation tools, I still think Orcad is the best for creating truly well
documented, reusable circuit blocks.  In general, we're able to produce what
we want in a reasonable amount of time (even considering deleted
features/bugs).  The worst was Viewlogic - the DOS version was complicated,
and then they took all the complexity and put a windows GUI on it - what a
disaster! I assume it's improved since then - they had nowhere to go but up.

We're not experienced in using their VHDL stuff beyond a bit of diddling
around, so I can't comment on the quality there.  But given Orcad's
strengths in integrating with other vendors tools, we'll probably just pick
the best in breed, and integrate it with Orcad.

Just thought you might like an alternate point of view.

Regards, Rick

ps.  Using Orcad for both FPGAs and PCBs is a nice benefit also. Something
some of the other tools are somewhat behind on.  We don't use Orcad layout,
however, our PCB guy likes Protel.  Interfacing between the two is quite
seemless (backannotation, etc.), but I haven't tried any postlayout signal
integrity tools (although HyperLynx seems to be saying they can make it all
work together.)


Rickman wrote in message <358B1710.F186D508@yahoo.com>...
>Simon Ramirez wrote:
>>
>> Rick,
>>    Every Orcad product I ever used was riddled with bugs and problems.
One
>> has to invent workarounds and even then, one has to be very careful about
>> what actually gets generated.
>>    If the Orcad output to the Xilinx place and route tool was unroutable,
>> then it is intolerable.  I would never tolerate such a tool, although I
do
>> tolerate problems with tools, as we all do.  But at least my suite of
tools
>> always produced working designs that were very simulatable.
>>    Thanks for warning me about Orcad.
>> -Simon ramirez
>>  Consultant/Contractor
>>  s_ramirez@msn.com
>
>The real shame is that I think the Orcad product has a better user
>interface in many respects than the Xilinx Foundation. If they got rid
>of all of the bugs and "rough edges" it would only have a single problem
>for doing FPGAs. It would still be a third party tool which is not
>tightly integrated with the backend tool. This shows up when you try to
>deal with things like timing or location constraints.
>
>For now I am using the Xilinx Foundation tool. It is a little less
>sophisticated in some respects and more in others, such as the state
>machine editor which Orcad doesn't even have. But the main point is that
>every problem I have had with the tool has been resolved in a half hour
>or less either by myself or Xilinx tech support! When they get FPGA
>Express integrated in the next release it should be an even better tool.
>If they could just get testbench simulation into the mix!!!
>
>
>
>
>--
>
>Rick Collins
>
>rickman@XYwriteme.com
>
>remove the XY to email me.


Article: 10809
Subject: Re: FPGA design tools for Xilinx and Altera on WinNT and Alpha
From: Erik de Castro Lopo <e.de.castro@REMOVE-THIS.fairlightesp.com.au>
Date: Mon, 22 Jun 1998 13:52:21 +1000
Links: << >>  << T >>  << A >>
Rick McBain wrote:
> 
> Are there any available? Or has anybody tried using !FX32 successfully with
> Xilinx foundation or alliance series tools (or Altera's Max tools) (or any
> FPGA tools)?

I don't know about the Xilinx or Altera tools but I have a collegue who
has 
successfully run Orcad Layout for Intel WinNT on an Alpha WinNT machine.
He 
was quite pleased with the performance.

My suggestion would be to get an Alpha machine on evaluation and try it
out.

Erik
Article: 10810
Subject: Re: Problems with XILINX 1.4
From: Frank Gilbert <gilbert@informatik.uni-kl.de>
Date: Mon, 22 Jun 1998 11:11:26 +0200
Links: << >>  << T >>  << A >>
Mohsin Riaz wrote:
> 
> Hi everybody,
> 
> I am a grduate student, working in the area of hardware implementation of
> Private_key Block ciphers using FPGAs as the target devices. While using the
> Design manager of the XILINX 1.4, i tried to extract the "time_sim.vhd"  file
> generated after placement and routing to use as an input for the Synopsys
> simulator to verify my design.But the problem is that while i try to
> compile this time_sim.vhd file, the Synopsys compiler(vhdlan) gives an error
> 
>         **Error: vhdlan,74 time_sim.vhd(33):
>     Corrupt intermediate file - SIMPRIM.VCOMPONENTS.sim (written using newer
>     version of the analyzer).
> 
> Can anybody help me in this matter as i am stuck at this stage of my
> design, because i need this timing simulation to be the same as the one
> that i got just after comiling my VHDL code in SYNOPSYS. this way i would
> be sure of the correctness of my design.
> 
> Thanks,

Hi

This looks familiar to me. You use an earlier version of Synopsys than
Xilinx did when they compiled the simprim-library. All you (or your
system administrator) have to do is recompile the simprim library.
Xilinx provides a shell script for this purpose:
$XILINX/synopsys/libraries/sim/src/simprims/analyze.csh .

Hope that helps 

Frank
____________________________________________________________________

Frank Gilbert                       | University of Kaiserslautern
mailto:gilbert@informatik.uni-kl.de | Center for Microelectronics (ZMK)
 phone: ++49/0 631 205 3608         | Erwin-Schroedinger-Strasse
   fax: ++49/0 631 205 3616         | D-67663 Kaiserslautern, Germany
Article: 10811
Subject: Xilinx carry logic (XC4000)
From: gibsond@bournemouth.ac.uk
Date: Mon, 22 Jun 1998 12:11:25 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm designing some fast arithmetic circuits with VHDL and I want to use the
carry logic these devices have. Is it possible to infer the carry logic? Can
it be instantiated?  The circuits so far are always mapped to CLB's.  The
tools I'm using are Synopsys 3.4 and Xilinx 5.2.1.

Darrell Gibson.

------------------------------------
Darrell Gibson
Bournemouth University,
P309b Poole House,
Talbot Campus,
POOLE. (UK)

Tel: (01202) 595535
Fax: (01202) 595559
email: gibsond@bournemouth.ac.uk

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10812
Subject: Re: Getting into using FPGAs
From: Richard Schwarz <aps@associatedpro.com>
Date: Mon, 22 Jun 1998 11:56:37 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Chris check out http://www.associatedpro.com Take a look ath the introductory
low cost FPGA kits. They are a great way to get started.

Christopher Fairbairn wrote:

> Hi,
>
> I would like to get into using FPGAs but I havn't really been able to find a
> lot of good information about how to use them and what I need to program
> them etc.
>
> Could anyone suggest a web site etc that I could find out such information.
> This is primarly a hobby so I don't really want to be able to do anything
> flash and I cann't afford an expensive programmer etc.
>
> Thanks
> Christopher Fairbairn
> lgcl01@es.co.nz



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


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Article: 10813
Subject: Re: books on vhdl
From: Richard Schwarz <aps@associatedpro.com>
Date: Mon, 22 Jun 1998 11:59:11 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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This is most probably technology specific. But if you check out our book
store on FPGAs and HDLs at http://www.associatedpro.com you will find a lot
of good FPGA books.

SAMIR KHERICHA wrote:

>  Are there any good books which would help in predicting how many CLB's a
> particular code in vhdl will take....I assume that's quite far is there
> book or means to determine how much logic a particular statement in vhdl
> will take and which is registered and which is non registered.
>
> samir
>
> ------------------------------------------------------
> Samir Khericha
> Graduate Research Assistant
> Department Of Computer Engineering
> Residence:
> 2383 duncan drive
> apt #8
> fairborn OH 45324
> PH No: 937-426-8076
> _______________________________________________________



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


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Article: 10814
Subject: ASIC&FPGA design
From: Romanovsky Sergey <rom@thesys.kiev.ua>
Date: Mon, 22 Jun 1998 19:49:31 +0300
Links: << >>  << T >>  << A >>
Group of microelectronics engeniers in Kiev,Ukraine specializes in:

- 0.6u/0.8u MPW cycle from idea to some specimen;
- design of digital ICs for 0.6u/0.8u standard CMOS
  (any technology is possible if Design Rules and Process Specification
could
   be get in our disposal);
- design of 0.8u CMOS IC with embedded EEPROM blocks;
- standard digital/analog cell design (Hspice models are needed);
- IC's layouts editing, DRC, LVS and layout support in accordance with
customer task;
- any projects on ACTEL's FPGAs;

Please respond to me at 
	rom@thesys.kiev.ua
or at 
	38 044 241 7115 
if you are interested, or would like to discuss any of your problems!

Thank you for your time.

Regards,

tel   38 044 241 7115
fax   38 044 241 7031
email rom@thesys.kiev.ua
Romanovsky Sergey,
DesignManager
Kiev Ukraine
Article: 10815
Subject: Re: [Question] Xilinx Foundation FPGA Express..
From: Brian Philofsky <brianp@xilinx.com>
Date: Mon, 22 Jun 1998 10:01:42 -0700
Links: << >>  << T >>  << A >>
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In order to describe a synthesizable bi-directional I/O in a Xilinx
device, you must not only declare the port as an inout but you must
describe the proper data flow structure in and out of the device.  What
I mean by this is you must describe a tri-stated output that connects
directory to the port (that will map into an OBUFT or OBUFE) and an
input path (be it registered or direct).

Some sample code may look like:

inout bidir_port;

assign bidir_port = sel ?  1'bZ : my_signal;

always @ (clk)
   another_signal <= bidir_port;


I know this was a very simple example but I did not want to put too much
thought into it.

There are other methods to creating bidir I/O such as instantiating the
I/O primitive or using LogiBLOX but both of those methods have their
obvious drawbacks.

Please see the following design guide,
ftp://ftp.xilinx.com/pub/documentation/interfaces/hdl_dg.pdf
It will go into further detail about creating bi-directional I/O as well
as other HDL synthesis and simulation topics that may be of interest to
you.


--  Brian Philofsky
      Xilinx Product Applications




Shin Woo Kyun wrote:

> Hi...
>
> I'm a rookie on FPGA Express.
>
> It's a very simple device to implement using schematic. but I'd like
>
>  to use verilog.
>
> My problem is how I can  express the Bidirection PAD on XilinxFPGA
>
> like 74LS245  using verilog..
>
> For example.......
>
> input MSEL;
> inout A;
> inout B;
>
> reg A;
> reg B;
>
> always @(MSEL or A or B )
>         if(MSEL) A = B;
>         else B = A;
>
> that is compiled well.  But I can't  implement it on Xilinx.



--
-------------------------------------------------------------------
 / 7\'7 Brian Philofsky   (brian.philofsky@xilinx.com)
 \ \ `  Xilinx Applications Engineer             hotline@xilinx.com
 / /    2100 Logic Drive                         1-800-255-7778
 \_\/.\ San Jose, California 95124-3450          1-408-879-5199
-------------------------------------------------------------------



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&nbsp;
<BR>&nbsp;

<P>In order to describe a synthesizable bi-directional I/O in a Xilinx
device, you must not only declare the port as an inout but you must describe
the proper data flow structure in and out of the device.&nbsp; What I mean
by this is you must describe a tri-stated output that connects directory
to the port (that will map into an OBUFT or OBUFE) and an input path (be
it registered or direct).

<P>Some sample code may look like:

<P>inout bidir_port;

<P>assign bidir_port = sel ?&nbsp; 1'bZ : my_signal;

<P>always @ (clk)
<BR>&nbsp;&nbsp; another_signal &lt;= bidir_port;
<BR>&nbsp;

<P>I know this was a very simple example but I did not want to put too
much thought into it.

<P>There are other methods to creating bidir I/O such as instantiating
the I/O primitive or using LogiBLOX but both of those methods have their
obvious drawbacks.

<P>Please see the following design guide, <A HREF="ftp://ftp.xilinx.com/pub/documentation/interfaces/hdl_dg.pdf">ftp://ftp.xilinx.com/pub/documentation/interfaces/hdl_dg.pdf</A>
<BR>It will go into further detail about creating bi-directional I/O as
well as other HDL synthesis and simulation topics that may be of interest
to you.
<BR>&nbsp;

<P>--&nbsp; Brian Philofsky
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Xilinx Product Applications
<BR>&nbsp;
<BR>&nbsp;
<BR>&nbsp;

<P>Shin Woo Kyun wrote:
<BLOCKQUOTE TYPE=CITE>Hi...

<P>I'm a rookie on FPGA Express.

<P>It's a very simple device to implement using schematic. but I'd like

<P>&nbsp;to use verilog.

<P>My problem is how I can&nbsp; express the Bidirection PAD on XilinxFPGA

<P>like 74LS245&nbsp; using verilog..

<P>For example.......

<P>input MSEL;
<BR>inout A;
<BR>inout B;

<P>reg A;
<BR>reg B;

<P>always @(MSEL or A or B )
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if(MSEL) A = B;
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; else B = A;

<P>that is compiled well.&nbsp; But I can't&nbsp; implement it on Xilinx.</BLOCKQUOTE>
&nbsp;
<PRE>--&nbsp;
-------------------------------------------------------------------
&nbsp;/ 7\'7 Brian Philofsky&nbsp;&nbsp; (brian.philofsky@xilinx.com)
&nbsp;\ \ `&nbsp; Xilinx Applications Engineer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; hotline@xilinx.com
&nbsp;/ /&nbsp;&nbsp;&nbsp; 2100 Logic Drive&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-800-255-7778&nbsp;
&nbsp;\_\/.\ San Jose, California 95124-3450&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1-408-879-5199&nbsp;
-------------------------------------------------------------------</PRE>
&nbsp;</HTML>

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Article: 10816
Subject: Re: Getting into using FPGAs
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Mon, 22 Jun 1998 16:17:23 -0700
Links: << >>  << T >>  << A >>
Christopher Fairbairn wrote:

> Hi,
>
> I would like to get into using FPGAs but I havn't really been able to
> find a
> lot of good information about how to use them and what I need to
> program
> them etc.
>
> Could anyone suggest a web site etc that I could find out such
> information.
> This is primarly a hobby so I don't really want to be able to do
> anything
> flash and I cann't afford an expensive programmer etc.
>  

Christopher,
go to the Xilinx web site at
http://www.xilinx.com
and look for the data book, then read pages 13-5 and 13-6. That should
give you a good feel for the capabilities.  ( I wrote those pages ).

You can buy the design software  at
http://www.amazon.com
looking for Xilinx.
The price for book plus software on a CD is less than seventy US
dollars.

My slightly biased advice.

Peter Alfke, Xilinx Applications
 

Article: 10817
Subject: FYI: Motorola terminates FPGA efforts
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 23 Jun 1998 08:08:30 -0700
Links: << >>  << T >>  << A >>
Apparently, Motorola (http://design-net.com/fpga/) has decided to exit the
FPGA market.  EE Times has more information on the story available at
http://www.eet.com/news/98/1014news/fpga.html.

For other recent programmable logic news, be sure to visit The Programmable
Logic Jump Station at http://www.optimagic.com.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 10818
Subject: FPGA Verfication and Testing
From: Robert Peach <rpeach@gelac.mar.lmco.com>
Date: Tue, 23 Jun 1998 12:39:56 -0400
Links: << >>  << T >>  << A >>
I am researching using FPGAs in my designs as opposed to MPGAs in order
to save costs and development time.  The concern I have is being able to
adequately test and verify the FPGA device before and after it is
programmed.  I will be using the designs in airborne applications and
have to adhere to strict government regulations on making sure the
device is well tested.  I know I will pick a QML certified vendor.  Can
anybody tell me what kind of testing a good vendor should do on their
part before programming?  Also, what kind of tools and testing can I do
on the part after programing?  I know this depends somewhat on the logic
elements(i.e. SRAM, anti-fuse, EPROM, EEPROM, FLASH) of the device, but
I would appreciate as much information as possible from those of you who
are a lot more knowledgeable on this subject than me.  Thank you.

Robert Peach
Intelligent Systems Division
Lockheed Martin Aeronautical Systems
(770) 494-7587
rpeach@gelac.mar.lmco.com



Article: 10819
Subject: Re: Getting into using FPGAs
From: Ruth Mayeda <ruth.mayeda@xilinx.com>
Date: Tue, 23 Jun 1998 10:35:39 -0700
Links: << >>  << T >>  << A >>
You will not find Peter's Application Note under the
Xilinx Data Book on the web, although it is published in
the hardcopy Data Book.  You can find this app note at
http://www.xilinx.com/xapp/xapp097.pdf.  It is a brief
overview of what FPGAs are.

In addition to the Xilinx site, you may also want to
check out http://www.optimagic.com/faq.html, which explains
the basics of programmable logic and design flows.

-Ruth Mayeda
Xilinx Applications

Article: 10820
Subject: ANNOUNCE: hMETIS 1.5, A Circuit Partitioning Package
From: George Karypis <karypis@cs.umn.edu>
Date: Tue, 23 Jun 1998 15:29:16 -0500
Links: << >>  << T >>  << A >>
hMETIS: A Package for Partitioning Circuits & Hypergraphs
---------------------------------------------------------

We would like to announce the release of hMETIS (Ver. 1.5), a software
package that can be used for circuit and hypergraph partitioning.
hMETIS is a set of programs that implement various hypergraph
partitioning
algorithms that are based on the multilevel paradigm.
The multilevel hypergraph partitioning algorithms of hMETIS have been
shown
to produce high quality partitions in small amount of time.

Version 1.5 contains a number of enhancements and improvements. Here is
a list of the major changes:

  - Improved the quality of the k-way recursive bisection algorithm.

  - Improved support for hypergraphs with widely varying vertex weights.

  - Added support for partitioning with `fixed' vertices. The
partitioning
    algorithms can now force user-specified sets of vertices to be
placed
    to user-specified partitions.

  - Added a new k-way partitioning code that is based on the multilevel
    k-way partitioning paradigm. It supports more meaningful balancing
    constraints for large values of k.



Obtaining hMETIS
----------------

hMETIS is freely distributed. Information on how to get the package
is available on WWW at:

  URL: http://www.cs.umn.edu/~metis


hMETIS has been written by George Karypis, at the Computer Science
Department of the University of Minnesota. If you have any questions or
problems obtaining hMETIS, send email to metis@cs.umn.edu.

hMETIS is copyrighted by the Regents of the University of Minnesota.

------------------------------------------------------------

Article: 10821
Subject: Re: Control skew due to routing in Xilinx M1
From: "Simon Ramirez" <s_ramirez@email.msn.com>
Date: Tue, 23 Jun 1998 17:19:03 -0400
Links: << >>  << T >>  << A >>
Richard,
   I agree with Phil Hay in his response to your question below, i.e., the
best way to control the skew between several signals is to place the flip
flops in IOBs.  Then the clock to pad delay theoretically is the same and in
practice is as close to the same as you will ever achieve.
   You mentioned in your response to his response that there was some reason
that you didn't do this but you couldn't think about what it was.  Could it
be that you couldn't figure out a way to make the flip flops go to the IOBs?
If so, there are several constraints that you have to meet in order to have
them land at the IOBs.  These constraints are straightforward and available
on a Solution Record from the Xilinx web site.  To avoid wasting time, call
the Xilinx Hotline and ask one of their jocks to reference this Solution
Record for you.
   One example of why the flip flop is not mapped to an IOB is that you
might be trying to reset it asynchronously.  After all, all good designers
want their flip flops in known states at power on reset or whatever.  If you
look at Figure 17, p. 4-22, of the 1998 Xilinx data book, you will note that
the IOB flop does not have an asynchronous set or reset.  Therefore, if your
schematic or HDL tells the netlister to put an asynchronous reset or preset
on that flip flop, it will be mapped to a CLB.
  Of course, one can reset or preset a flip flop synchronously and it
becomes part of the input logic to the D input of the flip flop.  You just
have to wait a clock cycle for it to become effective.
   Your need for low skew at the output pads intrigues me.  If you don't
mind my asking, why in a simple nutshell, do you need low skew between the
signals?
-Simon Ramirez
 Contractor/Consultant
 s_ramirez@msn.com



Richard J Warburton wrote in message <358d0a44.261706@news.demon.co.uk>...
>
>Okay, I'm using a 4kXL device, and want a way to control the skew
>between a bunch of signals from FFS to PADS, all FFS are clocked from
>the same clock.  I don't care what the delay is, but the skew between
>the bunch of signals must be low (I want to specify).
>
>The only way I have found of doing it at the moment is to specify a
>TIMESPEC that the routing delay from FFS to PADS is kept v.small, but
>this places a needless constraint on the already struggling PAR.
>
>Any ideas?
>
>Richard.


Article: 10822
Subject: Re: books on vhdl
From: "Simon Ramirez" <s_ramirez@email.msn.com>
Date: Tue, 23 Jun 1998 17:38:49 -0400
Links: << >>  << T >>  << A >>
Samir,
   There are no VHDL books which will predict how many CLBs it will take to
implement a certain statement or set of statements.  The reason for this is
that CLBs are specific to Xilinx and its architecture, and VHDL is
non-specific to any vendor or any vendor architectures.
   There is a book on VHDL written by Kevin Skahill, which is very good.  It
starts out by explaining SPLDs, i.e., 22V10s and such, and progresses into
CPLDs, FPGAs, etc.  Since Skahill is a Cypress employee, the book does tend
to gravitate toward explaining VHDL from a Cypress point of view.  It is a
tribute to him, though, that he does a wonderful job of explaining VHDL in
an almost unbiased point of view.  Therefore, this is a book about VHDL that
is almost architecture dependent but not really.
   Determining how what gets registered and what does not get registered is
a vital part of bing a VHDL code writer and FPGA designer; otherwise, you
would not be able to determine if your design will really fit into an FPGA
or how big of an FPGA it takes.  I suggest that you do simple designs and
actually go to place and route and see the end results so that you can gauge
how many CLBs it takes to implement statements.  This ability is both simple
and complex, depending on how much logic it takes to define an input to a
flip flop.  The number of flip flops can be easily calculated, though, by
determining how many signals you are going to either latch or register or
output from a register.
   These methods are best learned from experience, and so I leave you to
experiment with your VHDL statements and your place and route tool.
   Good luck.
-Simon Ramirez
 Contractor/Consultant
 s_ramirez@msn.com



SAMIR KHERICHA wrote in message ...
>
> Are there any good books which would help in predicting how many CLB's a
>particular code in vhdl will take....I assume that's quite far is there
>book or means to determine how much logic a particular statement in vhdl
>will take and which is registered and which is non registered.
>
>samir
>
>------------------------------------------------------
>Samir Khericha
>Graduate Research Assistant
>Department Of Computer Engineering
>Residence:
>2383 duncan drive
>apt #8
>fairborn OH 45324
>PH No: 937-426-8076
>_______________________________________________________
>
>


Article: 10823
Subject: REVOLUTIONARY ZERO NRE ASICs-update
From: "kash" <kash@ix.netcom.com>
Date: 23 Jun 1998 22:33:55 GMT
Links: << >>  << T >>  << A >>
We have updated our web-site on our new ZERO NRE ASICS.

Check out the technology area- details on how we can build 64 seperate
designs at same time.

Also find out more on our design center plan, support.

Finally fill out our ASIC survey.

Web site is at www.macrotechsemi.com

All ze best,

Kash
Article: 10824
Subject: Re: Xilinx carry logic (XC4000)
From: Rickman <spamgoeshere2@yahoo.com>
Date: Tue, 23 Jun 1998 22:42:34 -0400
Links: << >>  << T >>  << A >>
gibsond@bournemouth.ac.uk wrote:
> 
> Hi,
> 
> I'm designing some fast arithmetic circuits with VHDL and I want to use the
> carry logic these devices have. Is it possible to infer the carry logic? Can
> it be instantiated?  The circuits so far are always mapped to CLB's.  The
> tools I'm using are Synopsys 3.4 and Xilinx 5.2.1.
> 
> Darrell Gibson.

I was told that if you are using the Xilinx Foundation tools then carry
logic is inferred. I have not verified this. But I have not found a way
to access the carry out signal. 

One sure way to use the fast carry, the carry out as well as the carry
in is to use Logiblox. I know that this is available with Orcad as well
as Xilinx Alliance and Foundation. Logiblox creates the files that the
Xilinx backend needs to make the carry logic as well as the VHDL files
that your front end tools need to access these modules. The Logiblox
object is treated as a component in your VHDL code. 


-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.


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