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Peter Alfke wrote in message <359154FC.1BF4DC89@xilinx.com>... >jaleco wrote: > >> I don't need exactly,double freq,a appromix freq is OK. > >In the digital world, that is really impossible. > >I will defend the internal "sliver generator" ( using an XOR ) as >described in previous issues of the Xilinx data book. It is adaptive, >creating a long pulse in a slow part, a short one in a fast part. >Obviously, some common sense is required. >Don't generate a 2 ns pulse and then run it all over the chip.... In what way will you defend it.. To me adaptive means that the circuit changes in a positive manner, long pulse for slow part v. short pulse or *no* pulse for fast part is not necessarily a good thing.. If I saw someone using one professionally I would lose all respect for that person. I can see no use in purposely designing in circuitry which is highly dependant on voltage, temperature and process. The only time I would use this technique would be if I was on an island and I only had a FPGA with no PLL ...... ;-) MattArticle: 10851
Wait once. Do you mean the xxx.bit file used to program the device or some other file that is not at all part of the programming but rather something you want the XC3030 to process? The first case is a simple procedure that I could explain. The second is a design issue that I have not yet attempted. Have Fun!! Nick Laurent Hugueville wrote: > How can I transfert a binary file from a PC (printer port) to a Xilinx > XC3030 in Slave Serial Mode? > Which software can I use? > > Regards, > > Laurent.Article: 10852
I miss-understood your "delay element" comment. I was under the assumption that you meant the # operator would infer that for you. Well, that's cleared that up. :-') Matthew Morris wrote: > Gareth Baron wrote in message <359129A5.9615DD68@eng.efi.com>... > >I woudn't have thought this would work as the # operator is not a > >synthesized construct. It is used in behavioural modelling. > > I know # is not a synthesizable construct. That is why the comment mentions > implementation of delay via *precision* delay elements available within an > FPGA aka lotsa inverters. > > I hope what the original poster figures out is that, with the exception of > the PLL, there is no good solution for uprating clocks in a FPGA. > > Matt > > > >I think the only way to really get a clock double is by drawing the exact > >schematic you want and getting the FPGA tools to implement it. You will > >probably have to put constraints on the nets so that the logic fitter > >doesn't minimise the logic out for you. > > > >Matthew Morris wrote: > > > >> here is a *terrible* way to uprate in an fpga clk > >> > >> module up_clk(clk_in, clk_out, _reset); > >> > >> input clk_in; > >> output clk_out; > >> > >> wire clk_out ; > >> wire clk_in_delayed > >> > >> // This will work for sample of one, as long as the temperature doesn't > >> change or the voltage. > >> // otherwise buy a $2 pll and have piece of mind. > >> assign clk_in_delayed = #CLK_IN_PERIOD_DIV_4 clk_in; // delay is via > >> *precision* delay elements in FPGA > >> > >> // aka lotsa inverters.. > >> assign clk_out = clk_in ^ clk_in_delayed; > >> // ^ is xor > >> > >> end module; > >> > >> jaleco wrote in message <6mqabm$13g$1@news.seed.net.tw>... > >> > > >> > > >> >>Buy a FPGA with an internal PLL. > >> >> > >> >>Don't try to make a combinitorial freq. doubler via sliver generator. > >> >> > >> >I don't need exactly,double freq,a appromix freq is OK. > >> > > >> > > >> > > > > > > > > >-- > > > > > > > >------------ > >Gareth Baron > > > > -- ------------ Gareth BaronArticle: 10853
One good reference is the Altera AHDL book. The copy that I have is dated July 1994 and I'm not sure if it is still in print from Altera. There is also a book called "VHDL and AHDL Digital System Implementation" by Frank Scarpino (http://www.optimagic.com/books.html#AHDL). ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- ali Benkhalil wrote in message <3592A5FB.A4146280@bradford.ac.uk>... >Hi, > >I am using the Altera HDL to perform a real-time motion detection >algorithms (Background Subtraction) for FLEX 10k device. Dose any one >have or know any AHDL code done simeler thing or is there any good >references, books, or papers on AHDL code. > >Thanks all, > >Khalil >e-mail: akbenkha@bradford.ac.uk >Article: 10854
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Hello Darrell,
If you are using Synopsys 3.4(b hopefully) and XACT 5.2.1, carry logic
will be inferred for incrementors, decrementors (i.e.. counters), comparators,
adders and subtractors if the Designware libraries (XBLOX) are referred to in
your library setup. The two lines to add to your .synopsys_dc.setupt file (if
they are not already in there) are:
define_design_lib xblox_4000 -path \
<path_to_XACT>/synopsys/libraries/dw/lib/fpga/xc4000
synthetic_library = {xblox_4000.sldb standard.sldb}
The standard synthesis libraries will also need to be included as well. Run
the utility "synlibs" to make sure you have your libraries specified properly.
A couple of other things to be aware of with the XBLOX Designware library is
that the modules all have fixed widths (6, 8, 10, 12, 14, 16, 20, 24, 28, 32,
48, 64) so if an intermediate bounded module is declared, the next largest size
will be inferred and the upper bits are left unconnected. If a 4-bit or less
function is defined, it will be constructed out of standard gates and carry
logic will not be used.
Also the Designware libraries must be analyzed for your version of Synopsys
before using them (this is a one-time compilation). If this has If this was
not already done, see http://www.xilinx.com/techdocs/1189.htm for details on
how to do this.
These and other XBLOX modules may also be instantiated. A utility called
xbloxgen, http://www.xilinx.com/techdocs/1201.htm, that can create custom
modules to instantiate into your code. Another good book that better explains
this and other Synopsys related topics for the XACT-days is the XACT HDL
Synthesis Design Guide,
ftp://ftp.xilinx.com/pub/documentation/xactstep6/hdlsynth.pdf
One last thing to note is that some of this information I provided is
out-of-date. The current version of Xilinx software is M1.4 which has a
slightly different methodology and library set for Synopsys synthesis. Many of
the ideas here have not changed but some of the program names (like XBLOXGEN
now equals LogiBLOX), libraries and available target devices have changed.
Hope this helps.
-- Brian Philofsky
Xilinx Applications Engineer
gibsond@bournemouth.ac.uk wrote:
> Hi,
>
> I'm designing some fast arithmetic circuits with VHDL and I want to use the
> carry logic these devices have. Is it possible to infer the carry logic? Can
> it be instantiated? The circuits so far are always mapped to CLB's. The
> tools I'm using are Synopsys 3.4 and Xilinx 5.2.1.
>
> Darrell Gibson.
>
> ------------------------------------
> Darrell Gibson
> Bournemouth University,
> P309b Poole House,
> Talbot Campus,
> POOLE. (UK)
>
> Tel: (01202) 595535
> Fax: (01202) 595559
> email: gibsond@bournemouth.ac.uk
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/ Now offering spam-free web-based newsreading
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
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<P>Hello Darrell,
<P> If you are using Synopsys 3.4(b hopefully)
and XACT 5.2.1, carry logic will be inferred for incrementors, decrementors
(i.e.. counters), comparators, adders and subtractors if the Designware
libraries (XBLOX) are referred to in your library setup. The two
lines to add to your .synopsys_dc.setupt file (if they are not already
in there) are:
<P>define_design_lib xblox_4000 -path \
<BR> <path_to_XACT>/synopsys/libraries/dw/lib/fpga/xc4000
<P>synthetic_library = {xblox_4000.sldb standard.sldb}
<P>The standard synthesis libraries will also need to be included as well.
Run the utility "synlibs" to make sure you have your libraries specified
properly.
<P>A couple of other things to be aware of with the XBLOX Designware library
is that the modules all have fixed widths (6, 8, 10, 12, 14, 16, 20, 24,
28, 32, 48, 64) so if an intermediate bounded module is declared, the next
largest size will be inferred and the upper bits are left unconnected.
If a 4-bit or less function is defined, it will be constructed out of standard
gates and carry logic will not be used.
<P>Also the Designware libraries must be analyzed for your version of Synopsys
before using them (this is a one-time compilation). If this has If
this was not already done, see <A HREF="http://www.xilinx.com/techdocs/1189.htm">http://www.xilinx.com/techdocs/1189.htm</A>
for details on how to do this.
<P>These and other XBLOX modules may also be instantiated. A utility
called xbloxgen, <A HREF="http://www.xilinx.com/techdocs/1201.htm">http://www.xilinx.com/techdocs/1201.htm</A>, that can create
custom modules to instantiate into your code. Another good book that
better explains this and other Synopsys related topics for the XACT-days
is the XACT HDL Synthesis Design Guide, <A HREF="ftp://ftp.xilinx.com/pub/documentation/xactstep6/hdlsynth.pdf">ftp://ftp.xilinx.com/pub/documentation/xactstep6/hdlsynth.pdf</A>
<P>One last thing to note is that some of this information I provided is
out-of-date. The current version of Xilinx software is M1.4 which
has a slightly different methodology and library set for Synopsys synthesis.
Many of the ideas here have not changed but some of the program names (like
XBLOXGEN now equals LogiBLOX), libraries and available target devices have
changed.
<P>Hope this helps.
<BR>
<P>-- Brian Philofsky
<BR> Xilinx Applications Engineer
<BR>
<BR>
<BR>
<P>gibsond@bournemouth.ac.uk wrote:
<BLOCKQUOTE TYPE=CITE>Hi,
<P>I'm designing some fast arithmetic circuits with VHDL and I want to
use the
<BR>carry logic these devices have. Is it possible to infer the carry logic?
Can
<BR>it be instantiated? The circuits so far are always mapped to
CLB's. The
<BR>tools I'm using are Synopsys 3.4 and Xilinx 5.2.1.
<P>Darrell Gibson.
<P>------------------------------------
<BR>Darrell Gibson
<BR>Bournemouth University,
<BR>P309b Poole House,
<BR>Talbot Campus,
<BR>POOLE. (UK)
<P>Tel: (01202) 595535
<BR>Fax: (01202) 595559
<BR>email: gibsond@bournemouth.ac.uk
<P>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
<BR><A HREF="http://www.dejanews.com/">http://www.dejanews.com/</A>
Now offering spam-free web-based newsreading</BLOCKQUOTE>
<PRE>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</PRE>
</HTML>
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Article: 10855
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This will generally make a suitable 2X clock,
with a high period > Tcko
+----O<|-------+
| |
| ________ |
+-----------+--| D Q |--+
| ___ | |
+--\\ \ | |
|| >--+--|> |
clkin>-------//___/ | |________|
|
+--->clkout
Matthew Morris wrote:
> Peter Alfke wrote in message <359154FC.1BF4DC89@xilinx.com>...
> >jaleco wrote:
> >
> >> I don't need exactly,double freq,a appromix freq is OK.
> >
> >In the digital world, that is really impossible.
> >
> >I will defend the internal "sliver generator" ( using an XOR ) as
> >described in previous issues of the Xilinx data book. It is adaptive,
> >creating a long pulse in a slow part, a short one in a fast part.
> >Obviously, some common sense is required.
> >Don't generate a 2 ns pulse and then run it all over the chip....
>
> In what way will you defend it..
>
> To me adaptive means that the circuit changes in a positive manner, long
> pulse for slow part v. short pulse or *no* pulse for fast part is not
> necessarily a good thing..
>
> If I saw someone using one professionally I would lose all respect for that
> person.
> I can see no use in purposely designing in circuitry which is highly
> dependant on voltage, temperature and process.
> The only time I would use this technique would be if I was on an island and
> I only had a FPGA with no PLL ...... ;-)
>
> Matt
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<TT></TT>
<P><TT>This will generally make a suitable 2X clock,</TT>
<BR><TT>with a high period > Tcko</TT><TT></TT>
<P><TT>
+----O<|-------+</TT>
<BR><TT>
|
|</TT>
<BR><TT>
| ________ |</TT>
<BR><TT> +-----------+--|
D Q |--+</TT>
<BR><TT> |
___ |
|</TT>
<BR><TT> +--\\
\ |
|</TT>
<BR><TT>
|| >--+--|> |</TT>
<BR><TT>clkin>-------//___/ | |________|</TT>
<BR><TT>
|</TT>
<BR><TT>
+--->clkout</TT>
<BR>
<P>Matthew Morris wrote:
<BLOCKQUOTE TYPE=CITE>Peter Alfke wrote in message <359154FC.1BF4DC89@xilinx.com>...
<BR>>jaleco wrote:
<BR>>
<BR>>> I don't need exactly,double freq,a appromix freq is OK.
<BR>>
<BR>>In the digital world, that is really impossible.
<BR>>
<BR>>I will defend the internal "sliver generator" ( using an XOR ) as
<BR>>described in previous issues of the Xilinx data book. It is adaptive,
<BR>>creating a long pulse in a slow part, a short one in a fast part.
<BR>>Obviously, some common sense is required.
<BR>>Don't generate a 2 ns pulse and then run it all over the chip....
<P>In what way will you defend it..
<P>To me adaptive means that the circuit changes in a positive manner,
long
<BR>pulse for slow part v. short pulse or *no* pulse for fast part is not
<BR>necessarily a good thing..
<P>If I saw someone using one professionally I would lose all respect for
that
<BR>person.
<BR>I can see no use in purposely designing in circuitry which is highly
<BR>dependant on voltage, temperature and process.
<BR>The only time I would use this technique would be if I was on an island
and
<BR>I only had a FPGA with no PLL ...... ;-)
<P>Matt</BLOCKQUOTE>
</HTML>
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Article: 10856Hi, I am using the Altera HDL to perform a real-time motion detection algorithms (Background Subtraction) for FLEX 10k device. Dose any one have or know any AHDL code done simeler thing or is there any good references, books, or papers on AHDL code. Thanks all, Khalil e-mail: akbenkha@bradford.ac.ukArticle: 10857
My AHDL manual is dated November 1995, and like Steve says, its very good.
Another resource that goes deeper than that manual in some areas are the
tutorials on the freecore website (http://193.215.128.3/freecore/). Also look
in the AHDL function libraries that altera supply with Maxplus.
AVOID the book & disk that altera advertise on their website for about 70 USD.
"Digital Systems Design and Prototyping Using Field Programmable Logic" from
Kluwer Academic Publishers by Salcic and Smailagic
The disk & software is fine, the book is rubbish. Basically a copy of altera's
datasheets, with some poor diagrams and in some cases wrong examples. It seems
to think that you can still assign pin and other chip resources in AHDL; you
don't, you do it in the ACF file, and the book fails entirely to mention what
you can do with parameritised functions and altera's LPM function library.
In article <6mttlv$3sg@dfw-ixnews8.ix.netcom.com>
sknapp@optimagic.com "Steven K. Knapp" writes:
> One good reference is the Altera AHDL book. The copy that I have is dated
> July 1994 and I'm not sure if it is still in print from Altera.
>
> There is also a book called "VHDL and AHDL Digital System Implementation" by
> Frank Scarpino (http://www.optimagic.com/books.html#AHDL).
>
>>SNIP<<
>
> ali Benkhalil wrote in message <3592A5FB.A4146280@bradford.ac.uk>...
> >Hi,
> >
> >I am using the Altera HDL to perform a real-time motion detection
> >algorithms (Background Subtraction) for FLEX 10k device. Dose any one
> >have or know any AHDL code done simeler thing or is there any good
> >references, books, or papers on AHDL code.
> >
> >Thanks all,
> >
> >Khalil
> >e-mail: akbenkha@bradford.ac.uk
>
--
Steve Dewey
Steve@s-deweynospam.demon.co.uk
Too boring to have an interesting or witty .sig file.
Article: 10858I'm having a problem with a timing simulation on an XC4013E-1, using the Foundation F1.4 simulator. Part of the device has a temperature-dependent timing problem, but the affected circuitry simulates ok. Has anyone else seen anything like this? The -1 timing in my databook is preliminary, but I guess (hope) that the simulator is better informed. Thanks Evan (ems@nospam.riverside-machines.com)Article: 10859
Evan: Rarely is the timing analyzer wrong. One thing you might check is the occurrence of asynchronous events moving through one another due to your temperature variances. Are you using only one clock? Is is using one of the primary global buffers? ..... Are your sure? Are you using both edges of any of the clocks? If so, have you constrained the timing accordingly? Double check to see if ANY ff that gets its clock signal from anything other than the output net of the global buffer (simple inverters excepted as they will be absorbed into the CLB and IOB ffs). If so, it is operating asynchronously to the others and you would see variances due to temperature. FYI, to check the number of discrete clocks in your design, start timing analyzer and select VIEW-->CLOCKS. Note: the use of rising and falling edges of the same clock are ignored by this step. (As you'd probably want them to be) Sorry I can't elaborate more completely... kind of in a hurry! -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 ems wrote: > > I'm having a problem with a timing simulation on an XC4013E-1, > using the Foundation F1.4 simulator. Part of the device has a > temperature-dependent timing problem, but the affected circuitry > simulates ok. > > Has anyone else seen anything like this? The -1 timing in my > databook is preliminary, but I guess (hope) that the simulator > is better informed. > > Thanks > > Evan (ems@nospam.riverside-machines.com)Article: 10860
HI I have COREGen but there is no PCI2.1 source. I need it now. ShinArticle: 10861
Year 2000 And Information Warfare News Briefs Get all the latest Year 2000 and Information Warfare news delivered free, directly to your email account with no advertising by subscribing to the iWarfare News Briefs. What are the Year 2000 and Information News Briefs The Year 2000 and Information Warfare News Briefs are designed to keep you up to date with the all the latest news stories and issues from around the world. We monitor over 2000 news sources daily and have agents in over 80% of the worlds countries giving us unique access to the latest events as they happen.These News Briefs are free and delivered directly to you email box To subscribe, go to: http://iwarfare.com/news.htm Angela Bowers News Briefs Team iWarfare.comArticle: 10862
See www.vchips.com and get a PCI 2.2 compliant core with power management. Shin Woo Kyun wrote in message <3592f2e4.1396579@news.hitel.net>... >HI > >I have COREGen but there is no PCI2.1 source. > >I need it now. > > > Shin >Article: 10863
I'm work with the test-simulator HILO and synthesis
on FPGA with FPGAExpress from Xilinx.(a case studies , it's free)
After synthesis, the netlist contain some unknown macro definition
like 'CY4'... and i can't convert it in GHDL (genrad) because i don't know
what they do ?.
I suppose it's a common problem for others vhdl entry !
My work is just for educational, it's to develop a methodologie
on vector generation from high level description. (VHDL)
Is there a solution ?
Thanks
Alain.
-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10864There's nothing async here. The design is correct, and the implementation also appears to be correct (I've checked the relevant paths with the timing analyser). A number of timings are on the limit, but they all pass. A previous route worked without problems, but a small change in another part of the device, and a subsequent route, introduced this timing problem. My main concern, as I thought I implied, is that the simulator may be using incorrect values for the -1 part, given that the 7/97 databook marks the timings as preliminary. I know for a fact that at least one timing parameter differs between the timing file and the data book (but this is on an output register clk->out, and I think this may be the case for all devices). Does anyone have any experience with this? Thanks EvanArticle: 10865
. A number of timings are on the limit, >but they all pass. A previous route worked without problems, but a >small change in another part of the device, and a subsequent route, >introduced this timing problem. Have you tried using the design that worked as a guide file for making the changes? This might help. Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://cdl.uta.edu/cpm MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpmArticle: 10866
ems wrote in message <3592c836.306943060@news.dial.pipex.com>... >I'm having a problem with a timing simulation on an XC4013E-1, >using the Foundation F1.4 simulator. The simulator is very buggy. We have had numerous problems with the simulator showing things that work, but the part doesn't work in the lab. We would then find some problem with our VHDL, rerun simulations (which still work), and the part works in the lab also. What specifically is the problem? Are you using schematics, HDL, or a combination? ScottArticle: 10867
Hunter Int. wrote: > > Hi, > > We have an opportunity for an individual who has done some complex Circuit > Board/FPGA design to work at a place where cutting edge technology is the > norm, and one of the very best design staffs in the country awaits. > > This position is for someone who has between 3-10 years of high performance > custom circuit design under his/her belt. You will be working on some of > the "neatest" projects you've ever seen, and will become a stellar hardware > designer for your efforts. > > Some of the "buzz": We are looking for High Speed Digital Designers, > having some experience with PLD's, FPGA's (ASICS), complex designs (nothing > simple at this place), understands timings, etc... Not a person who still > needs a lot of instruction, we are hoping to find an individual who can > stand alone and bring a project in from scratch to production. > > This is a great company! Our guarantee is this: If you go in and chat > with these people, you WILL want to work there, especially if you can do > this type of work. > > They are located on the North side of Chicago, near Skokie or Evanston, > just off the Kennedy. Salary will be very nice, they're not cheap, as > they're looking for the best we can bring in. > Dave... This posting has been appearing here periodically for a very long time. Either the salaries are not all that great, the company/work is not as advertised, or they are being very very picky on who they will bring in to chat with (I rather doubt the 3rd unless they are not seriously looking to hire). Perhaps it is time they seek a consultant? There are several consultants who post here regularly who are well regarded experts in digital design, and especially with FPGA design. Even more can be found by referring to Gale's or to the IEEE directory of consultants ( http://www.ieee.org/consultants ) Hiring a consultant has the advantage of obtaining expertise you may not otherwise have access to. When the job is complete, you are not left with the burden of paying for expertise you are not using. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10868
Alain.Chauche@esisar.inpg.fr wrote: > After synthesis, the netlist contain some unknown macro definition > like 'CY4'... and i can't convert it in GHDL (genrad) because i don't know > what they do ?. The CY4 and CY4xxx instances are the Xilinx carry primitives used to invoke the carry chain. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10869
On Fri, 26 Jun 1998 12:07:51 GMT, timolmst@cyberramp.net wrote: >Have you tried using the design that worked as a guide file for making >the changes? This might help. good idea - except that i've never managed a successful guided design on a 4KE with foundation. the normal problem is a crash, but i seem to remember that there's a second problem as well. i think that there's now a patch for the crash; i'll give this a go if everything else fails. thanks evanArticle: 10870
ems wrote: > > I'm having a problem with a timing simulation on an XC4013E-1, > using the Foundation F1.4 simulator. Part of the device has a > temperature-dependent timing problem, but the affected circuitry > simulates ok. > > Has anyone else seen anything like this? The -1 timing in my > databook is preliminary, but I guess (hope) that the simulator > is better informed. > > Thanks > > Evan (ems@nospam.riverside-machines.com) I am not a big fan of doing timing analysis by simulation for this very reason. It is too easy to miss something critical by not supplying the correct timing in the simulation vectors or by not adequately simulating all the min/max, min/min and max/max situations. I advocate a thorough static timing analysis instead (another good reason to keep the design synchronous). The timing tools are accurate; The reports can be trusted to be correct. Xilinx does periodically update the timing files, but I believe all the updates are to improve the timing numbers (allow for faster operation) based on the die test experience. You might check the web site anyway to make sure you have the latest timing files. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10871
On Fri, 26 Jun 1998 08:18:53 -0500, "Scott Frazer" <scott.frazer@ericsson.com> wrote: >ems wrote in message <3592c836.306943060@news.dial.pipex.com>... >>I'm having a problem with a timing simulation on an XC4013E-1, >>using the Foundation F1.4 simulator. > >The simulator is very buggy. We have had numerous problems >with the simulator showing things that work, but the part doesn't >work in the lab. We would then find some problem with our VHDL, >rerun simulations (which still work), and the part works in the lab >also. What specifically is the problem? Are you using schematics, >HDL, or a combination? > >Scott very interesting. i've never noticed a problem with the foundation/ aldec simulator before, but this is precisely the sort of problem that could be easily glossed over and not noticed. i had been suspecting the delay data, rather than the simulator itself. this particular design is all VHDL (metamor synthesiser). currently, i've only simulated at gate level with foundation, using viewsim-type command files. i could also run a VHDL timing simulation with modelsim, but i hadn't been planning to do this. this would be *very* interesting - did you try comparing your failed simulations with any other simulator? unfortunately, i can't be very specific about the problem. two pipelines are getting out of sync, and it looks like it may be incorrect timing on one of a number of clock enables, although they're reported as being ok. the device works when frozen, but fails after a couple of minutes at room temperature. thanks evanArticle: 10872
We are developing a test system and one of the component we found that
fulfils our requirement is an Altera FPGA (FLEX10K70RC240-4) based PMC
card. In order to program this component, we need Altera Max Plus
software. Before we go any further, we need to have an idea of the
price of such a package to see if it is worth investing in it or if we
should try to find another solution.
Any information is welcomed.
Kind regards
---
David Guyard
_______________________________________________________________
David Guyard Philips Consumer Communications
Tel.: +33/(0)2 43 41 19 11 Route d'Angers
Fax.: +33/(0)2 43 41 11 26 F-72081 Le Mans
E-Mail: david.guyard@pcc.philips.com France
_______________________________________________________________
Article: 10873ems wrote: > I'm having a problem with a timing simulation on an XC4013E-1, > using the Foundation F1.4 simulator. Part of the device has a > temperature-dependent timing problem, but the affected circuitry > simulates ok. > I do not understand the "temperature-dependent timing problem". The simulator knows nothing about temperature, it just manipulates the worst case ( i.e. hot and low-Vcc) speeds-file numbers. So, are you saying it simulates ok, but the silicon does not work properly ? At room temperature and nominal Vcc, or at hot and low Vcc ? Peter Alfke, Xilinx ApplicationsArticle: 10874
On Fri, 26 Jun 1998 10:36:52 -0400, Ray Andraka <no_spam_randraka@ids.net> wrote: >I am not a big fan of doing timing analysis by simulation for this very >reason. It is too easy to miss something critical by not supplying the >correct timing in the simulation vectors true enough, but a static analysis doesn't get around this. > or by not adequately simulating all the min/max, min/min and max/max > situations. ditto above. the other problem, of course, is that xilinx only supplies one number, which makes sophisticated analysis rather difficult. >I advocate a thorough >static timing analysis instead (another good reason to keep the design >synchronous). i personally prefer timing by constraint. however, since this doesn't work well (particularly in multiple-clock devices), i also have to do a simulation to find out what the constraints actually did, or didn't do. the problems with static analysis include multiple clocks, clock enables, and signals which cross clock boundaries. this device has a main clock of 64MHz. it's a fairly large device, and some of the logic wont cycle at 15ns, so i generate lower-frequency clocks, which are also used as clock enables on the high frequency. the enable timing is a function of the logic, and a static analysis wont be able to deduce this. it'll simply assume that a block that's clocked at 15ns is meant to cycle at 15ns when, in fact, it's meant to cycle at 2*15ns, 3*15ns, or whatever. >The timing tools are accurate; The reports can be trusted >to be correct. i wish i believed this! i've checked the speed files, and there doesn't seem to be anything later than the ones which came with F1.4. i'm afraid that i'm (slowly) coming to the conclusion that the tools simply aren't up to coping with multiple-clock devices. thanks evan
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