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Messages from 16800

Article: 16800
Subject: Free IP library?????
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Wed, 09 Jun 1999 11:55:06 +0100
Links: << >>  << T >>  << A >>
I am interested in finding and/or setting-up a GNU-style library
of free synthesisable IP cores.  It seems to me that the GNU GPL
licensing model (free source, do what you want with it but you 
must acknowledge it and keep it complete) has some potential benefits
particularly for small businesses using FPGAs.  One good aspect
of GNU GPL is that it doesn't prevent people from making money
out of consultancy and support activities around the free material.
Another is that it might make available some cores that are too small
to be of interest to serious IP companies.

And yes, I do know about ACTgen and Xilinx's core generator, which
are fine, but don't cover everyone's needs.

If such a thing exists already, can anyone point me at it please?
And if it doesn't, I would be willing to put some work in to
setting it up and hosting it - anyone interested?

I even have an acronym already: ELK (Electronics Library of
Kernels) - it is of course inappropriate to have a recursive
acronym like GNU because all hardware designs must be statically
elaborated :-)

Jonathan Bromley
Article: 16801
Subject: Re: Free IP library?????
From: Stephen Smith <stephens@ensigma.com>
Date: Wed, 09 Jun 1999 12:09:28 +0100
Links: << >>  << T >>  << A >>
Try

http://www.cmosexod.com/

http://circu.its.tudelft.nl/

http://www.scsise.wmin.ac.uk/~seamang/freehardware.html

http://www.scrap.de/html/openip.htm

http://www.geocities.com/SiliconValley/Chip/5014/ 

http://www.vhdl.org/vi/fmf/

http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html

Post any more you find...

Have Fun

  Stephen Smith


Jonathan Bromley wrote:
> 
> I am interested in finding and/or setting-up a GNU-style library
> of free synthesisable IP cores.  It seems to me that the GNU GPL
> licensing model (free source, do what you want with it but you
> must acknowledge it and keep it complete) has some potential benefits
> particularly for small businesses using FPGAs.  One good aspect
> of GNU GPL is that it doesn't prevent people from making money
> out of consultancy and support activities around the free material.
> Another is that it might make available some cores that are too small
> to be of interest to serious IP companies.
> 
> And yes, I do know about ACTgen and Xilinx's core generator, which
> are fine, but don't cover everyone's needs.
> 
> If such a thing exists already, can anyone point me at it please?
> And if it doesn't, I would be willing to put some work in to
> setting it up and hosting it - anyone interested?
> 
> I even have an acronym already: ELK (Electronics Library of
> Kernels) - it is of course inappropriate to have a recursive
> acronym like GNU because all hardware designs must be statically
> elaborated :-)
> 
> Jonathan Bromley
Article: 16802
Subject: Re: LINE DELAYS USING RAMS
From: Ray Andraka <randraka@ids.net>
Date: Wed, 09 Jun 1999 08:31:59 -0400
Links: << >>  << T >>  << A >>


That works too, and you can use common rw controls if you write two words in one
cycle and read two in the next.  It costs a pair of alignment registers in the FPGA,
but frees up a few pins.

Lasse Langwadt Christensen wrote:

> how about two ram chips, connect the addresses but "swap" read and write
> on the two chips, then you can read from chip 1 at the same time as you
> write
> to chip 2, once you've got to the length of the buffer you start reading
> from 2
> and writing to 1 ?  you'll need twice as many data io pins and twice as
> much mem
> but it'll only have to run at single speed
>
> --L2C
> --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_----
> Lasse Langwadt Christensen, MSEE (to be, june 30th 1999)
> Aalborg University, Department of communication tech.
> Applied Signal Processing and Implementation (ASPI)
> http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.org



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 16803
Subject: Simultaneous switching outputs in Xilinx Spartan XL
From: Terry Fraser <fraser@appliedmicro.ns.ca>
Date: Wed, 09 Jun 1999 11:01:25 -0300
Links: << >>  << T >>  << A >>
Has anyone come across any guidelines for how many simultaneous
switching outputs
the Spartan XL's can tolerate ? They published an app note about the
Virtex, but there does not appear to be anything on the Spartans.

Some of Xilinx's CPLD parts had a "programmable ground" feature that
drives unused I/Os low to act as pseudo-ground pins. Anyone ever try
this
on an FPGA to see if it reduces switching noise ?

--
-----
Terry Fraser
Hardware Designer
Applied Microelectronics Inc
Halifax, NS
Phone: (902) 421-1250 ext 269
FAX:   (902) 429-9983
mailto:fraser@appliedmicro.ns.ca
http://www.appliedmicro.ns.ca


Article: 16804
Subject: Last chance to register: Workshop on Design Reuse, June 16-17-18, San Jose, CA
From: mikeh@qualis.qualis.com (Michael T. Horne)
Date: 9 Jun 1999 16:29:44 GMT
Links: << >>  << T >>  << A >>

The Qualis special workshop on Design Reuse is only a week away!
With attendance nearly full, you have only a few more days to reserve
your seat at this enlightening event.  The details follow, but call
or register online soon!


                   Designing with Reuse in Mind 

                     A Special 3-day Workshop
                       June 16-17-18 1999
                      San Jose, California

Qualis Design is hosting a special workshop on design reuse this
June 16-17-18 in San Jose, California.  This intense workshop will be led by
Janick Bergeron, Vice President of Technical Wisdom at Qualis.  Janick
will work closely with the attendees of this stimulating workshop,
covering all of the critical areas of design reuse. As a recognized expert
in reuse methodologies and large system design, Janick deeply understands
the reuse issues designers face.  In this interactive workshop, you will
learn how to set up a reuse-friendly design environment, how to architect,
implement, and verify a reusable component and SoC design, and how to
package it for future reuse.  Join other top engineers for this unique
opportunity to network and discuss today's reuse challenges and solutions. 

Find detailed information about this seminar on our website at:

  http://www.qualis.com/cgi-bin/qualis/session.pl?event=reuse_990616.html

or call Michael McDowell at 888-214-4224 (or +1-503-968-8550) to secure
your seat. 

Michael


Article: 16805
Subject: Re: Evolutionary computation
From: Tim Tyler <tt@cryogen.com>
Date: Wed, 9 Jun 1999 19:01:31 GMT
Links: << >>  << T >>  << A >>
Hal Murray <murray@pa.dec.com> wrote (quoting me):

:> Say I am implementing a lattice-gas automata in order to simulate
:> turbulent fluid flow through a confined space.  What earthy use are
:> counters or addition and subtraction primitives to me?  None whatsoever.
:> 
:> If I want to retain the flexibility to run more than one type of
:> lattice-gas simulation, FPGAs are the best type of target hardware.

: How much money to you have?

As always, not /quite/ as much as I'd like ;-)

: Have you considered making an ASIC that was a big array of FPGA
: type cells optomized for your problem?

Yes, though I don't feel able to draw any firm conclusions at this stage.

In fact I have several "target problems": one involves a very simple
automata capable of universal computation (in fact /almost/ identical to
Margolus's implementation of Fredkin's "billiard-ball machine":
http://www.alife.co.uk/ca/bbm/2d/) - and the other is an unusual and
complex automata which supports self-reproduction: http://www.alife.co.uk/hal/
This model is not yet at all fixed; and may require ongoing modifications.

It seems to me that if I *can* afford lots of silicon, then prototyping
a circuit on an FPGA, allowing my model to settle down, and then making
my own chips consisting of hardware devoted to running my automata - may
well wind up being cheaper.

If I *can't* afford lots of silicon, then I'm best off getting the biggest
and bestest FPGA that I can afford; as it's all I'm going to get.
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

When I gave her the ring, she gave me the finger.

Article: 16806
Subject: Re: Q: Spartan XL pull-ups
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 09 Jun 1999 14:06:29 -0700
Links: << >>  << T >>  << A >>


Peter Alfke wrote

>
> The pull-up "resistor", which of course is a p-channel transistor, is active
> even for voltages above Vcc. So you should count on a "resistor" to the Vcc
> terminal of about 50 kilohm. It's not "leakage", but rather a  non-linear
> resistance.
>

I have been corrected by the circuit designer:

Once the pin voltage is one threshold above Vcc, the pull-up "resistor" is
actually turned off, so the current disppears (down to the microamp or below
level).

Trying to be honest.

Peter Alfke, Xilinx Applications

Article: 16807
Subject: Re: LINE DELAYS USING RAMS
From: bob elkind <eteam@aracnet.com>
Date: Wed, 09 Jun 1999 15:52:16 -0700
Links: << >>  << T >>  << A >>
NEC and others make video line delay RAMs.  If (1-3 line) video line delay is what you want,
this is an inexpensive and off-the-shelf solution.  Inherent in this approach is that there
is no random access; once you pop the next data word out of the FIFO, the previous word is
gone (unless you've cached it on the FPGA in a small local pixel buffer).

-- Bob Elkind

khalid wrote:
> 
> Hi All,
> 
> I want to implement a line delay using off-chip RAM (necessary for Image
> Convolution). On the FPGA, this is done using Synchronous RAM which has a
> input data line and an output data one, which makes things easy. The line
> delay I want to implement is big (800 pixels) and cannot be implemented on
> the FPGA chip. How could I use the off-chip RAM to do that (One line for
> both input and output) ?.
> 
> I hope I'll have a reply soon.
> 
> Thanks in advance.
Article: 16808
Subject: Re: LINE DELAYS USING RAMS
From: bob elkind <eteam@aracnet.com>
Date: Wed, 09 Jun 1999 15:55:20 -0700
Links: << >>  << T >>  << A >>
NEC and others make video line delay RAMs.  If (1-3 line) video line delay is what you want,
this is an inexpensive and off-the-shelf solution.  Inherent in this approach is that there
is no random access; once you pop the next data word out of the FIFO, the previous word is
gone (unless you've cached it on the FPGA in a small local pixel buffer).

-- Bob Elkind

khalid wrote:
> 
> Hi All,
> 
> I want to implement a line delay using off-chip RAM (necessary for Image
> Convolution). On the FPGA, this is done using Synchronous RAM which has a
> input data line and an output data one, which makes things easy. The line
> delay I want to implement is big (800 pixels) and cannot be implemented on
> the FPGA chip. How could I use the off-chip RAM to do that (One line for
> both input and output) ?.
> 
> I hope I'll have a reply soon.
> 
> Thanks in advance.
Article: 16809
Subject: Looking for Xilinx Virtex devices
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 09 Jun 1999 16:37:48 -0700
Links: << >>  << T >>  << A >>
Dear all,

sorry for the off-topic posting but we are desperately looking for
some Xilinx XCV300 in the PQ240 package. The faster the better, but
any speed grade will do. The current lead time from the distributors
is more than 10 weeks, so we would be very glad if anyone could sell
us some of these parts.

Thanks,

-Arrigo
--
Dr. Arrigo Benedetti      o         e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	 < >			phone: (626) 395-3695
Pasadena, CA 91125	 / \			fax:   (626) 795-8649
Article: 16810
Subject: Free Sex Links!! 9209
From: mmobcl@hotmail.com
Date: Thu, 10 Jun 1999 07:19:32 GMT
Links: << >>  << T >>  << A >>
For Nasty Sex links visit:

http://website.lineone.net/~simonsi/sexlinks.htm
cgxrpvdjtxiuryjktzmrocvbkylngclxfrfbylflmxxzbuuiqutqg

Article: 16811
Subject: Free Sex Links 7070
From: ewngkj@hotmail.com
Date: Thu, 10 Jun 1999 11:47:08 GMT
Links: << >>  << T >>  << A >>
For Nasty Sex links visit:

http://website.lineone.net/~simonsi/sexlinks.htm
lrpvmcioypvohcoggskypdwlmtlwhgqssfboekfegttbpcuxbtwrwsqrmuftzephpelstgtctinzpgupbnmhxj

Article: 16812
Subject: Re: Q: Spartan XL pull-ups
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Thu, 10 Jun 1999 09:08:15 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> I have been corrected by the circuit designer:
> 
> Once the pin voltage is one threshold above Vcc, the pull-up "resistor" is
> actually turned off, so the current disppears (down to the microamp or below
> level).
> 

For the process technology that the Spartan series is made with, what is
Vt for the P channel devices?

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 16813
Subject: Configuring AlteraFlex10k with maxII
From: Thomas Rathgen <trathgen@gmx.de>
Date: Thu, 10 Jun 1999 15:30:59 +0200
Links: << >>  << T >>  << A >>
Hi folks,

does anyone out there have information how to configure io-pads with
maxII. I'm wondering how to enable/disable output-ff - for example. 
Is there any information on the web about the available settings in
maxII - the online help doesn't really help on this.

Much thanks


	Tom
Article: 16814
Subject: Re: Q: Spartan XL pull-ups
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 10 Jun 1999 13:34:16 -0700
Links: << >>  << T >>  << A >>


Brian Boorman wrote:

> Peter Alfke wrote:
>
> > Once the pin voltage is one threshold above Vcc, the pull-up "resistor" is
> > actually turned off, so the current disppears (down to the microamp or below
> > level).
> >
>
> For the process technology that the Spartan series is made with, what is
> Vt for the P channel devices?
>

Vt is ~700 mV

Peter Alfke

Article: 16815
Subject: Virtex Boards
From: david braendler <dbraendler@swin.edu.au>
Date: Fri, 11 Jun 1999 11:34:03 +1000
Links: << >>  << T >>  << A >>
I'm looking at buying  a Virtex board (preferably with a PCI interface)
and I'd be interested to here what people think of the Virtex boards
that they have used.


Cheers
--
---------------------------------------------------------------------------------------------

David Braendler     http://gene.bsee.swin.edu.au/daveb/index.htm
Centre for Intelligent Systems
Swinburne University of Technology
--------------------------------------------------------------------------------------------



Article: 16816
Subject: test 6651
From: nomad@vagabond.com
Date: Fri, 11 Jun 1999 03:07:29 GMT
Links: << >>  << T >>  << A >>
test
kfyfeshvoxyhcxdkequmdovdcgfuqtjoyjzqeqwystfepwbobywvzxtgtqkbuuoyrgzkpldftjkkjhtoqie

Article: 16817
Subject: Re: Q: Spartan XL pull-ups
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Fri, 11 Jun 1999 04:00:47 GMT
Links: << >>  << T >>  << A >>
On Wed, 09 Jun 1999 14:06:29 -0700, Peter Alfke <peter@xilinx.com>
wrote:

>> The pull-up "resistor", which of course is a p-channel transistor, is active
>> even for voltages above Vcc. So you should count on a "resistor" to the Vcc
>> terminal of about 50 kilohm. It's not "leakage", but rather a  non-linear
>> resistance.
>
>I have been corrected by the circuit designer:
>
>Once the pin voltage is one threshold above Vcc, the pull-up "resistor" is
>actually turned off, so the current disppears (down to the microamp or below
>level).

Thanks Peter.

Do you mean that the circuit actually has a negative resistance
region?

Does the following curve represent what really happens?
If so, do you know the maximum current into the device?

^I
|
|
|          /|
|         / |
+--------+--+--+------>V
|       /3  4  5
|      /
|    /
|  /
|-
|

(The weak "hold" circuits on 74LVC logic also exhibit this effect, see
http://www-us.semiconductors.philips.com/acrobat/applicationnotes/AN2022.pdf
(figures 4 and 5, ignoring the pull-down component) for an example.

BTW, I assume that this shape also applies to the strong p channel
pull-ups.

Regards,
Allan.
Article: 16818
Subject: Re: Configuring AlteraFlex10k with maxII
From: Markus Michel <mmichel@kius.ch>
Date: Fri, 11 Jun 1999 10:35:45 +0200
Links: << >>  << T >>  << A >>
1. Select the I/O pin.
2. Assign.Logic Options.Individual Logic Options.Fast I/O (on/off)

Hope this helps
Markus

Thomas Rathgen wrote:

> Hi folks,
>
> does anyone out there have information how to configure io-pads with
> maxII. I'm wondering how to enable/disable output-ff - for example.
> Is there any information on the web about the available settings in
> maxII - the online help doesn't really help on this.
>
> Much thanks
>
>         Tom



Article: 16819
Subject: Place & Route Xilinx F1.5 Student ed.
From: gibsond@bournemouth.ac.uk
Date: Fri, 11 Jun 1999 10:18:36 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm trying to use the student edition of Xilinx F1.5. When I place and
route, if I've locked all the pin in the design to specific locations
the flow engine hangs when it gets to the constructive placer. If I
leave at least one pin un-located there is no problem.  Is this a
limitation of the student edition or a known problem. Has anyone else
come across this?  Is there a work around other that not locating all
the pins.  It is a bit of a pain not being able to specify all
locations.

Thanks,

Darrell Gibson.



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Article: 16820
Subject: Re: Place & Route Xilinx F1.5 Student ed.
From: Reinoud <dus@casema.net>
Date: Fri, 11 Jun 1999 13:18:02 +0200
Links: << >>  << T >>  << A >>
gibsond@bournemouth.ac.uk wrote:
> I'm trying to use the student edition of Xilinx F1.5. When I place and
> route, if I've locked all the pin in the design to specific locations
> the flow engine hangs when it gets to the constructive placer. If I
> leave at least one pin un-located there is no problem.  Is this a
> limitation of the student edition or a known problem. Has anyone else
> come across this?  Is there a work around other that not locating all
> the pins.  It is a bit of a pain not being able to specify all
> locations.

Duh.  I think I can figure out where that single remaining I/O would
be placed, given that only one pin isn't locked.

- Reinoud
Article: 16821
Subject: www.edy.net/jnonia
From: "EDYNet Web Design & More" <info@gg.it>
Date: Fri, 11 Jun 1999 14:20:36 +0200
Links: << >>  << T >>  << A >>
www.edy.net/jnonia



Article: 16822
Subject: Re: Place & Route Xilinx F1.5 Student ed.
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Fri, 11 Jun 1999 09:08:58 -0400
Links: << >>  << T >>  << A >>
Reinoud wrote:
> 
> gibsond@bournemouth.ac.uk wrote:
> > I'm trying to use the student edition of Xilinx F1.5. When I place and
> > route, if I've locked all the pin in the design to specific locations
> > the flow engine hangs when it gets to the constructive placer. If I
> > leave at least one pin un-located there is no problem.  Is this a
<snip>
> Duh.  I think I can figure out where that single remaining I/O would
> be placed, given that only one pin isn't locked.
> 
> - Reinoud

I think you assume too much. He may not be using all the pins of the
device, so leaving it unlocked would allow the placer to put it on
whatever unused pin it felt like using. Another work-around is to create
a dummy signal pin that does something trivial and let that pin that you
don't care about be the "floater".

I would try searching the online support section at www.xilinx.com and
failing that call the tech support line and pose it to them. Xilinx is
one of the best in terms of technical support (IMHO).
-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
Article: 16823
Subject: Re: Place & Route Xilinx F1.5 Student ed.
From: gibsond@bournemouth.ac.uk
Date: Fri, 11 Jun 1999 13:34:39 GMT
Links: << >>  << T >>  << A >>
In article <3760F06A.E0E039FE@casema.net>,
  Reinoud <dus@casema.net> wrote:
> gibsond@bournemouth.ac.uk wrote:
> > I'm trying to use the student edition of Xilinx F1.5. When I place
and
> > route, if I've locked all the pin in the design to specific
locations
> > the flow engine hangs when it gets to the constructive placer. If I
> > leave at least one pin un-located there is no problem.  Is this a
> > limitation of the student edition or a known problem. Has anyone
else
> > come across this?  Is there a work around other that not locating
all
> > the pins.  It is a bit of a pain not being able to specify all
> > locations.
>
> Duh.  I think I can figure out where that single remaining I/O would
> be placed, given that only one pin isn't locked.
>
> - Reinoud
>

Duh, I'm not using all the pins on the device. If you have a method
of guessing the location of pin assignments that tool makes I'd love to
hear about
it.

Darrell Gibson


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Article: 16824
Subject: Re: Place & Route Xilinx F1.5 Student ed.
From: gibsond@bournemouth.ac.uk
Date: Fri, 11 Jun 1999 13:34:46 GMT
Links: << >>  << T >>  << A >>
In article <3760F06A.E0E039FE@casema.net>,
  Reinoud <dus@casema.net> wrote:
> gibsond@bournemouth.ac.uk wrote:
> > I'm trying to use the student edition of Xilinx F1.5. When I place
and
> > route, if I've locked all the pin in the design to specific
locations
> > the flow engine hangs when it gets to the constructive placer. If I
> > leave at least one pin un-located there is no problem.  Is this a
> > limitation of the student edition or a known problem. Has anyone
else
> > come across this?  Is there a work around other that not locating
all
> > the pins.  It is a bit of a pain not being able to specify all
> > locations.
>
> Duh.  I think I can figure out where that single remaining I/O would
> be placed, given that only one pin isn't locked.
>
> - Reinoud
>

Duh, I'm not using all the pins on the device. If you have a method
of guessing the location of pin assignments that tool makes I'd love to
hear about
it.

Darrell Gibson


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