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Messages from 11150

Article: 11150
Subject: Re: Partial reprogramming
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 21 Jul 1998 07:28:35 -0700
Links: << >>  << T >>  << A >>
[snip]

>> > I heard about programme/family chip called "Raphael" from Xilinx. Where
>> > can I find any info about it?
>
>Not from me - I've not heard of it - Xilinx's search engine hasn't either.
>
Actually, "Raphael" is a project name for an upcoming product family from
Altera (see http://www.altera.com/html/mktg/raphael.html).  I don't know
whether it's partial programmable or not.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 11151
Subject: Re: Partial reprogramming
From: Pasquale Corsonello <pascor@XYnwdeis1.unical.it>
Date: Tue, 21 Jul 1998 17:39:23 +0200
Links: << >>  << T >>  << A >>
Tim Tyler wrote:

> 
> Reconfigurability is supposed to be on the list of features of the Xilinx
> 'Virtex' series due in the not-too-distant.  It is not clear to me whether
> these chips will supercede the 6200 immediately, or whether the 6200 will
> remain the preferred Xilinx chip for applications which require partial
> reconfiguration for some time.
> --

XILINX has stopped development work on its XC6200 line of partially
reconfigurable
field-programmable gate arrays on May 98.
See http://www.eet.com/news/98/1008news/wraps.html

regards,
Pasquale Corsonello

remove the XY to mail me
Article: 11152
Subject: Re: problems in SDF files from foundation 1.4?
From: adyer@MCS.COM (Andrew Dyer)
Date: 21 Jul 1998 10:44:29 -0500
Links: << >>  << T >>  << A >>
It turns out that loading the latest version of the patches from the 
Xilinx web site fixed this problem :-) Now I only have to fix my bugs :-)


-- 
| Andrew Dyer                       <adyer@midway.com> or <adyer@mcs.net>     |
| Sr. Design Engineer               (773) 961-1751                            |
| Midway Games, Inc.                (773) 961-1890 (fax)                      |
| 2727 W. Roscoe Ave., Chicago, IL 60618                                      |
Article: 11153
Subject: problems with xilinx foundation
From: mlankenau@yahoo.com (Marcus Lankenau)
Date: Tue, 21 Jul 1998 17:43:14 GMT
Links: << >>  << T >>  << A >>
Hi!


Afte a few changes on my (very simple) design I got this errors in the
Log-File:

Reading NGD file "../spartan.ngd"...
Using target part "s05pc84-4".
MAP spartan directives:
   Partname="xcs05-4-pc84".
   No Guide File specified.
   No Guide Mode specified.
   Covermode="area".
   Coverlutsize=4.
   Coverfgsize=4.
   Perform logic replication.
   Pack CLBs to 97%.
Processing logical timing constraints...
Running general design DRC...
ERROR:basnu:93 - logical block "H6" of type "FD_16" is unexpanded.
<----
ERROR:basnu:93 - logical block "H5/H6" of type "FD_16" is unexpanded.
<----
WARNING:basnu:113 - logical net "$I40/CEO" has no load
Errors detected in general drc.


The Block H6 for example is a 16-bit register. The data-input comes
from a IBUF16 and the clock comes from a IBUFGP-block. I can't realize
what this errors messages are for. I'm using a XCS05 (Spartan).



Marcus

Article: 11154
Subject: XC6200DS doubt/problem
From: Flavio Miana de Paula <miana@dcc.ufmg.br>
Date: Tue, 21 Jul 1998 15:56:37 -0300
Links: << >>  << T >>  << A >>
I'm having the following problem:

When generating a .cal file from an edn. file via (Xact Step Series 6000
v1.0.1) without any placement constraints (loc/rloc) I get a success bus
width configuration.  On the other hand, if I set some placement
constraints I fail.

I've already tested many combinations seeking for the problem, but I
couldn't figured out.

Please, I would appreciate if anyone could help me.

Sincerely,


Flavio Miana
Computer Engineering Master Student
Computer Engineering Laboratory (LECOM -UFMG - Brazil)


Article: 11155
Subject: Symbol Generation from FPGA Compiler Reports
From: mbitzko@my-dejanews.com
Date: Tue, 21 Jul 1998 19:21:08 GMT
Links: << >>  << T >>  << A >>
  Schematic symbol generation is an tedious error prone task.  SymBuilder(tm)
automates the creation of schematic symbols directly from the popular FPGA
compiler reports, from spread sheets, and through cut and pasting from
content provided in PDF data sheets.  Heterogeneous schematic symbol sets can
now be created in a fraction of the time versus the manual entry process. 
Export interfaces to the popular EDA Systems include OrCAD, Protel, and McCAD
for SymBuilder Personal, and Cadence, Mentor Graphics, and Viewlogic for
SymBuilder Enterprise.	For additional information, please refer to the web
page at http://www.ccaes.com.



-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11156
Subject: Schematic Symbol Generation
From: mbitzko@my-dejanews.com
Date: Tue, 21 Jul 1998 19:40:19 GMT
Links: << >>  << T >>  << A >>
  Schematic symbol creation is a error prone time consuming effort.
SymBuilder(tm) automates the creation of heterogeneous schematic symbol sets
from fpga compiler reports, from spread sheets, and the content provided in
pdf data sheets.  Export interfaces include OrCAD, Protel, and McCAD for
SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
SymBuilder Enterprise. For additional information, refer to
http://www.ccaes.com.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11157
Subject: Re: Shift Invarient Bit Transform
From: "Daniel Lang" <dblx@hydra0.caltech.edu>
Date: 21 Jul 1998 19:53:47 GMT
Links: << >>  << T >>  << A >>
Rickman <spamgoeshere4@yahoo.com> wrote in article
<35B2BE96.70C14709@yahoo.com>...
> 
> My guesstimate of compression comes from the number of "shift invariant
> equivalence" (SIE) groups vs. the number of possible bit patterns for a
> given number of bits. Obviously there are 2**n number of bit patterns.
> Any given SIE group can be created by picking a starting pattern and
> shifting through all the possible patterns until you have shifted by n
> where the original pattern is guaranteed to repeat. Therefor, the
> largest number of members of any given SIE group will be n, while many
> will be less. The number of SIE groups will then be no less than 2**n/n. 
> 
> To find the amount of compression this will produce, consider the number
> of bits to represent the compressed data; n vs. log2((2**n)/n) or
> log2(2**n) - log2(n) or n - log2(n). This gives a relative savings of
> log2(n)/n. If n is 32, then log2(n) is 5 and 5/32 is about 15%. And
> remember that this is an upper limit which will never be reached! 15%
> compression is not very big, and it is only useful if you don't care
> about distinguishing between SIE group members. What would be the
> application where this would apply?
> 

You are making the assumption that all possible bit patterns are
equally probable (random data).  In addition, some sort of prefix must
be added to indicate how many places the original string has been
shifted.  When you work this out, you will find that the data is
expanded, not compressed, for random data.

I have worked out a lossless compression scheme for image data that
gives compression ratios of 1.5 to 3.0 for typical image data
(12-bits, 40-Mhz, using an Altera Flex 10K20-3).  As for the
complexity of the logic, the 16 bit priority encode to find the MSB
took 3 levels of 4-input LUTs.  The prefix was also computed and
the combined string fed into a barrel shifter and appended to an
output register.

Daniel Lang  dblx@anemos.caltech.edu  (but remove the x)
Article: 11158
Subject: Re: Partial reprogramming
From: Tim Tyler <tim@uma.sublime.org>
Date: Tue, 21 Jul 1998 21:19:30 +0100
Links: << >>  << T >>  << A >>
On Tue, 21 Jul 1998, Pasquale Corsonello wrote:
> Tim Tyler wrote:
> 
> > Reconfigurability is supposed to be on the list of features of the Xilinx
> > 'Virtex' series due in the not-too-distant.  It is not clear to me whether
> > these chips will supercede the 6200 immediately, or whether the 6200 will
> > remain the preferred Xilinx chip for applications which require partial
> > reconfiguration for some time.
> 
> XILINX has stopped development work on its XC6200 line of partially
> reconfigurable field-programmable gate arrays on May 98.
> See http://www.eet.com/news/98/1008news/wraps.html

I'm aware of that.

In the article you refer to, after discussing which members of the
devlopment team left, and the Virtex chips, Roland Triffaux, of Xilinx,
Europe is quoted as saying that the 6200 series would 'continue to be
available to academic and commercial research groups'.

From this I was not sure whether to conclude that he was referring to the
period until Virtex chips started coming off production lines, or after
that point - which would imply that some application areas would remain
where the XC6200 was better suited than Xilinx alternative offerings.

Partial reconfigurability is only one of the 6200s attractive features -
the runtime random access, processor interface, publicly available
programming format and 'safety' are also often mentioned.

Xilinx has some excellent web pages about Virtex, but I'm not sure if
XC6200 customers will feel completely reassured by them.
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

Article: 11159
Subject: Re: Wanted: CPLD Primer
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 21 Jul 1998 21:39:00 GMT
Links: << >>  << T >>  << A >>
> I'm jumping in with both feet and my eyes closed...
>
> Any primer/newbie links to CPLD and/or programmable logic in general
> needed please.

John:

I wrote a set of lab tutorials for doing FPGA and CPLD logic design
that's published by Prentice-Hall.  It's "The Practical Xilinx Designer"
with ISBN of 0-13-095502-7.  You can purchase it from Amazon.com or from
www.xess.com/FPGA.  There is also a package they sell that includes a
student version of the Xilinx M1 software for $87.  Its ISBN is
0-13-671629-6.  You can find a link to the Prentice-Hall page about these
items at www.xess.com/FPGA/links.html.

> It's been years since I "mapped" a PAL.  Now I need a PLD interface
> for our micro and external circuits.  Using Lattice isp-Synario.
> Looking it over, I see I have a lot of catching up to do.  Tutorials,
> app notes and general technique primers needed.

XESS also makes a board that incorporates an 8051 microcontroller with an
interface to a Xilinx XC4000 FPGA or XC9500 CPLD.  We keep the schematic
and some design examples on our web site.  These might help jump-start
you.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


Article: 11160
Subject: Re: Dataio Chipwriter won't burn Altera EPC1 generated with Maxplus2 8.2 or greater???
From: tmitools@aol.com (TMItools)
Date: 21 Jul 1998 22:24:49 GMT
Links: << >>  << T >>  << A >>
Dear Eric,

I just saw your email post about the Altera EPC1 programming problem. I work in
sales and tech. support at Tribal Microsystems. Our ALL-11 programmer features
a Windows 95/3.1 compatible user interface and supports the Altera, Xilinx, and
Atmel serial configuration PROMs. The ALL-11 is available from stock and is $
1095.

As far as I know we do not have any problems with Altera EPC1 files from any
compilers.( At least no customers have reported this problem to me.) If you
want you can email me a test POF file and I can have one of our engineers burn
it to an EPC 1 just to make sure. 

If you are interested please contact me and I can get you some more
information.

Best Regards,

Rob Kruger
sales@tribalmicro.com

Tribal Microsystems, Inc.
44388 S. Grimmer Blvd.
Fremont, CA 94538, USA
Tel: 510 623 8859
Fax: 510 623 9925
Article: 11161
Subject: Re: Shift Invarient Bit Transform
From: jure@ssl.berkeley.edu (Jorge (Jure) Zaninovich)
Date: Tue, 21 Jul 1998 15:16:52 -0800
Links: << >>  << T >>  << A >>
I would suggest that you investigate the Walsh/Hadamard transforms,
which may be what you need to solve this problem.
Jure Z.

-- 
jure@ssl.berkeley.edu
Article: 11162
Subject: Re: How to write a VHDL counter of up & down
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 21 Jul 1998 19:46:15 -0400
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Rickman wrote:
> 
> > The "how would you design this in hardware" argument doesn't apply this
> > time. This is exactly how a standard TTL device works, the 74LS193. It
> > has an up clock and a down clock. Of course it is up to the user to
> > actuate only one at a time. But then all logic has the caveat of proper
> > usage.
> >
> 
> Just because this was done in a device designed a quarter century ago
> doesn't make it good design practice.  Many of the early TTL counters are
> also ripple counters (each stage clocked by the output of the previous
> stage).  Yes you can do this in VHDL (you need to combine and decode the
> clocks, look at the schematic given in an old TTL databook for the '193),
> but it is not synchronous design. Asynchronous logic should be avoided in
> FPGA designs, especially in those that will later be ported to an ASIC.
> Asynchronous design is possible in an FPGA, but it is loaded with pitfalls,
> is difficult to verify over the range of operating conditions and makes for
> an expensive translation to ASIC.  Don't do it where you don't absolutely
> have to, you'll just make more headaches for everyone involved.


The definition of good programming practice was not the point of this
post. I expect that the original requester is trying to design a circuit
that is part of a poorly designed circuit. The point was that he was
trying to do something that can be done in hardware, he was simply
programming it wrong. 

This would indeed be a dificult circuit to get to work correctly. But if
there were a compelling reason to do it, then sometimes pure synchronous
design is not the best way to go. I do make all of my designs purely
synchronous however. I just don't have the patience to deal with the
difficulties of anything else. 

-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 11163
Subject: Re: How to write a VHDL counter of up & down
From: "Paul J. Menchini" <mench@mench.mench.com>
Date: 22 Jul 1998 00:15:44 GMT
Links: << >>  << T >>  << A >>
ems <ems@see_sig.com> wrote:
: On Mon, 20 Jul 1998 07:54:15 GMT, leslie.yip@asmpt.com wrote:

:> elsif UP='1' and UP'event and ENABLE = '1' then
:> <snip>
:> elsif DN='1' and DN'event and ENABLE = '1' then

: you can't do this - you can't have two clocks in the same process.

Actually, you can have multiple clocks.  You just can't synthesize
the model with any existing, commercial synthesis tools.

Paul

-- 
Paul Menchini          | mench@mench.com | "Se tu sarai solo,
Menchini & Associates  | www.mench.com   |  tu sarai tutto tuo."
P.O. Box 71767         | 919-479-1670[v] |   -- Leonardo Da Vinci
Durham, NC  27722-1767 | 919-479-1671[f] |
Article: 11164
Subject: Aldec's Active-VHDL Behavorial Simulator-Thanx
From: "MHB" <mhb@anv.net>
Date: Tue, 21 Jul 1998 19:01:06 -0700
Links: << >>  << T >>  << A >>
Thank you all who responded to my posting of last week asking opinions of
Active-VHDL.  My original suspicions were confirmed with overwhelming
enthusiasm, it is a great behavioral simulator with a very intuitive user
interface.  The hdl editor and State Diag. Editor are a nice touch, this was
important to me especially when I evaluated Model Tech's Model Sim and
couldn't believe they don't give you any way to enter text and have the
nerve to charge $4600, the kicker that I loved about the Aldec tool, was the
automatic Test Bench generator.....Great feature!!!!!! (there technical
people were also very helpful).

I never bothered looking at Orcad as my understanding is they have very good
layout tools but their simulator basically doesn't work well.  Apparently
there are some compliancy issues: I.e.. there vhdl simulator is not IEEE
compliant and I am hearing nightmares or problems simulating its
code....I'll pass on that eval.

Well I am a happy camper, I just ordered Active-VHDL and recommend it to
all.  There demo can be obtained from there web site www.aldec.com  and they
also sent me two books which I found informative.






Article: 11165
Subject: Re:Add info-How to write a VHDL counter of up & down
From: leslie.yip@asmpt.com
Date: Wed, 22 Jul 1998 02:13:33 GMT
Links: << >>  << T >>  << A >>
Thanks for help a lot.

Usually, the two signals Ch1_A and Ch1_B are of phase difference = 90░. These
two signals coming from an encoder is decoded as signals of pulses of 'UP' if
CHA (i.e. Ch1_A) leads CHB by 90░. Pulses of 'DN' occur if CHA lags CHB by
90░.

Figure 3(d)	With phase difference=90░, timing shows ChA leads ChB and the
counter counts up.

ChA and ChB from an optical encoder of a motor
              __________            __________
ChA    ______|          |__________|          |________

                    __________            __________
ChB    ____________|          |__________|          |________

Decoder decode the ChA and ChB to count the position and sends the counter
value to Motion controller. UP (Up pulses to counter)  _  _  _	_  _  _  _  _
UP  _______| |__| |__| |___| |___| |__| |__| |___| |______


Whenever Ch1_A leads Ch1_B, it generates four pulses of signal UP (the pin as
shown in figure 1) in one cycle of Ch1_A and the counter increments. If Ch1_A
lags Ch1_B, four pulses of DN (down) produces in one cycle, decrementing the
counter. The timing of the waveform is shown in figure 3(b) and figure 3(c).
The generated pulses lag the edges of signal input by 2 clock cycles.

Reference: National - Motion Controller LM628, with App Note AN-706
(http://www.national.com) Datasheet in pdf format

                    __________            __________
ChA    ____________|          |__________|          |________

              __________            __________
ChB    ______|          |__________|          |________
              _     _    _     _    _     _    _     _
DN     ______| |___| |__| |___| |__| |___| |__| |___| |______

DN (Down pulses to counter, i.e. counter counts down)

Fig. ChA lags ChB and it generates four pulses of DN in one cycle and counters
counts down by 4.


With these pulses, the counter counts up whenever there are pulses of 'UP'
and counts down whenever there are pulses of 'DN'. It also gives pulses of
CARRY when overflow. So one 16-bit counter can be obtained from four 4-bit
counters by connecting the 'CARRY' signal of lower 4-bit counter to 'UP'
signal of the higher 4-bit counter. (and by connecting the 'BORROW' signal of
lower 4-bit counter to 'DN' signal of the higher 4-bit counter



In article <35B467D2.ADD69978@hardi.se>,
  Jonas Nilsson <jonas@hardi.se> wrote:
> leslie.yip@asmpt.com wrote:
> > I don't know how to implement my previous ASIC-design counter with 2
> > edge triggers -- up and down (up => increment the counter by 1; down
> > [i.e. dn] => decrement the counter by 1) I used logic gates to
> > implement this function but it seems difficult to describe this with
> > VHDL. I know that another writing of up-down counter is to use a pin
> > to control up/down and another is just a clock for incrementing /
> > decrementing the counter.
> >
> > My 4-bit counter, however, uses four 4-bit counter to connect
> > together by: Carry => UP ('Carry' of lower-bit counter connected to
> > 'UP' of another counter) Borrow => DN
> >
> > Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit
> > counter.
>
> The description is probably not entirely correct, since it decribes
> a priority between the different clocks. The UP edge has precedence
> over the DN edge. Even if there was such a thing as a dual-clock
> flip-flop in the target device, the synthesis tool probably couldn't
> guarantee this behaviour.
>
> Synthesizable processes only have one clock, but because registers
> in the device architectures seldom have more than one clock input
> this never poses a problem. Your logic gate design probably gated
> the two clocks together, and used the current values of UP and DN
> (probably latched in some way to prevent metastability and other
> asynchronous problems) to choose between the up and down modes.
> (This is how the venerable 'LS193 that rickman mentioned works)
>
> Look at your original gate design, separate the combinational logic
> from the registers, and describe them in separate processes. You
> would perhaps have to use a third process for the 'latch' function.
> If you can't make it, send me a brief description of your logic gate
> design, and I'll try to fix it for you.
>
> Just remember that asynchronous designs like this are subject to
> lots of problems. I'd strongly recommend that you use a synchronous
> design instead, with a common clock for all your four-bit stages
> and a synchronous UP/DN input. Why do you want the ripple clock?
> Power issues?
>
> Regards,
> Jonas
> --
> +---------------------------------------------------------------+
> | Jonas Nilsson                                                 |
> | HARDI Electronics AB      Phone : +46-40-59 29 00             |
> | Derbyvagen 6B             Fax   : +46-40-59 29 19             |
> | SE-212 35 MALMO           E-mail: jonas@hardi.se              |
> | SWEDEN                    WWW:    http://www.hardi.se         |
> +---------------------------------------------------------------+
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 11166
Subject: Re:Add info-How to write a VHDL counter of up & down
From: leslie.yip@asmpt.com
Date: Wed, 22 Jul 1998 02:16:33 GMT
Links: << >>  << T >>  << A >>
Thanks for help a lot.

Usually, the two signals Ch1_A and Ch1_B are of phase difference = 90░. These
two signals coming from an encoder is decoded as signals of pulses of 'UP' if
CHA (i.e. Ch1_A) leads CHB by 90░. Pulses of 'DN' occur if CHA lags CHB by
90░.

Figure 3(d)	With phase difference=90░, timing shows ChA leads ChB and the
counter counts up.

ChA and ChB from an optical encoder of a motor
              __________            __________
ChA    ______|          |__________|          |________

                    __________            __________
ChB    ____________|          |__________|          |________

Decoder decode the ChA and ChB to count the position and sends the counter
value to Motion controller. UP (Up pulses to counter)  _  _  _	_  _  _  _  _
UP  _______| |__| |__| |___| |___| |__| |__| |___| |______


Whenever Ch1_A leads Ch1_B, it generates four pulses of signal UP (the pin as
shown in figure 1) in one cycle of Ch1_A and the counter increments. If Ch1_A
lags Ch1_B, four pulses of DN (down) produces in one cycle, decrementing the
counter. The timing of the waveform is shown in figure 3(b) and figure 3(c).
The generated pulses lag the edges of signal input by 2 clock cycles.

Reference: National - Motion Controller LM628, with App Note AN-706
(http://www.national.com) Datasheet in pdf format

                    __________            __________
ChA    ____________|          |__________|          |________

              __________            __________
ChB    ______|          |__________|          |________
              _     _    _     _    _     _    _     _
DN     ______| |___| |__| |___| |__| |___| |__| |___| |______

DN (Down pulses to counter, i.e. counter counts down)

Fig. ChA lags ChB and it generates four pulses of DN in one cycle and counters
counts down by 4.


With these pulses, the counter counts up whenever there are pulses of 'UP'
and counts down whenever there are pulses of 'DN'. It also gives pulses of
CARRY when overflow. So one 16-bit counter can be obtained from four 4-bit
counters by connecting the 'CARRY' signal of lower 4-bit counter to 'UP'
signal of the higher 4-bit counter. (and by connecting the 'BORROW' signal of
lower 4-bit counter to 'DN' signal of the higher 4-bit counter



In article <35B467D2.ADD69978@hardi.se>,
  Jonas Nilsson <jonas@hardi.se> wrote:
> leslie.yip@asmpt.com wrote:
> > I don't know how to implement my previous ASIC-design counter with 2
> > edge triggers -- up and down (up => increment the counter by 1; down
> > [i.e. dn] => decrement the counter by 1) I used logic gates to
> > implement this function but it seems difficult to describe this with
> > VHDL. I know that another writing of up-down counter is to use a pin
> > to control up/down and another is just a clock for incrementing /
> > decrementing the counter.
> >
> > My 4-bit counter, however, uses four 4-bit counter to connect
> > together by: Carry => UP ('Carry' of lower-bit counter connected to
> > 'UP' of another counter) Borrow => DN
> >
> > Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit
> > counter.
>
> The description is probably not entirely correct, since it decribes
> a priority between the different clocks. The UP edge has precedence
> over the DN edge. Even if there was such a thing as a dual-clock
> flip-flop in the target device, the synthesis tool probably couldn't
> guarantee this behaviour.
>
> Synthesizable processes only have one clock, but because registers
> in the device architectures seldom have more than one clock input
> this never poses a problem. Your logic gate design probably gated
> the two clocks together, and used the current values of UP and DN
> (probably latched in some way to prevent metastability and other
> asynchronous problems) to choose between the up and down modes.
> (This is how the venerable 'LS193 that rickman mentioned works)
>
> Look at your original gate design, separate the combinational logic
> from the registers, and describe them in separate processes. You
> would perhaps have to use a third process for the 'latch' function.
> If you can't make it, send me a brief description of your logic gate
> design, and I'll try to fix it for you.
>
> Just remember that asynchronous designs like this are subject to
> lots of problems. I'd strongly recommend that you use a synchronous
> design instead, with a common clock for all your four-bit stages
> and a synchronous UP/DN input. Why do you want the ripple clock?
> Power issues?
>
> Regards,
> Jonas
> --
> +---------------------------------------------------------------+
> | Jonas Nilsson                                                 |
> | HARDI Electronics AB      Phone : +46-40-59 29 00             |
> | Derbyvagen 6B             Fax   : +46-40-59 29 19             |
> | SE-212 35 MALMO           E-mail: jonas@hardi.se              |
> | SWEDEN                    WWW:    http://www.hardi.se         |
> +---------------------------------------------------------------+
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11167
Subject: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 21 Jul 1998 22:55:51 -0700
Links: << >>  << T >>  << A >>
I hate to say this, but without a signature line and from the way that your
posting is worded, this _could_ be a disguised advertisement written by a
marketing guy.

I haven't tried the product and it may be _just_ that good but until then,
if you are a marketing guy, please don't try to kid the kidders.

Color me cynical.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

MHB wrote in message <6p3gs9$2e3$1@supernews.com>...
>Thank you all who responded to my posting of last week asking opinions of
>Active-VHDL.  My original suspicions were confirmed with overwhelming
>enthusiasm, it is a great behavioral simulator with a very intuitive user
>interface.  The hdl editor and State Diag. Editor are a nice touch, this
was
>important to me especially when I evaluated Model Tech's Model Sim and
>couldn't believe they don't give you any way to enter text and have the
>nerve to charge $4600, the kicker that I loved about the Aldec tool, was
the
>automatic Test Bench generator.....Great feature!!!!!! (there technical
>people were also very helpful).
>
>I never bothered looking at Orcad as my understanding is they have very
good
>layout tools but their simulator basically doesn't work well.  Apparently
>there are some compliancy issues: I.e.. there vhdl simulator is not IEEE
>compliant and I am hearing nightmares or problems simulating its
>code....I'll pass on that eval.
>
>Well I am a happy camper, I just ordered Active-VHDL and recommend it to
>all.  There demo can be obtained from there web site www.aldec.com  and
they
>also sent me two books which I found informative.
>
>
>
>
>
>




Article: 11168
Subject: unknown speedgrade question
From: Erik Lins <Erik.Lins@exp2.physik.uni-giessen.de>
Date: Wed, 22 Jul 1998 11:46:38 +0200
Links: << >>  << T >>  << A >>
Hello,

I have three XC4020E FPGAs and I don't know the speedgrade. They seem to
be not correctly marked.
The full text on top is:
XC4020E(TM)
HQ208CKM9701
A0321A
some mm below there is a 2C written.

Any ideas ?

Thanx,
ER!K
Article: 11169
Subject: Re: Too much advertising in this news group?
From: Jamie Lokier <spamfilter.july1998@tantalophile.demon.co.uk>
Date: 22 Jul 1998 12:10:31 +0100
Links: << >>  << T >>  << A >>
"Greenwood Systems" <greenwoodsys@yahoo.com> writes:
> Having recently posted and item this news group with respect to the interest
> there would be in a contract VHDL/FPGA startup company, I assume I am partly
> responsible for all this thread.
> 
> I never intended any upset and apologise for any caused.
> 
> My belief was that this newsgroup covered all aspects of FPGA technology and
> development and that my post was not inappropriate

Of course your posting is appropriate, don't assume they're talking
about you.  Where else would you ask about interest in FPGA contracts?
Well I consider your question relevant and welcome anyway.

I suspect the repeated postings by certain agencies/headhunters has a
lot more to do with this thread.

-- Jamie


Article: 11170
Subject: Re: How to write a VHDL counter of up & down
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 22 Jul 1998 09:29:51 -0400
Links: << >>  << T >>  << A >>


Paul J. Menchini wrote:

> ems <ems@see_sig.com> wrote:
> : On Mon, 20 Jul 1998 07:54:15 GMT, leslie.yip@asmpt.com wrote:
>
> :> elsif UP='1' and UP'event and ENABLE = '1' then
> :> <snip>
> :> elsif DN='1' and DN'event and ENABLE = '1' then
>
> : you can't do this - you can't have two clocks in the same process.
>
> Actually, you can have multiple clocks.  You just can't synthesize
> the model with any existing, commercial synthesis tools.

Well, the tool won't synthesize it, but you can instantiate to make it
happen.  Like I said earlier though, it is not a good idea for FPGAs in
most cases.  There are times when an asynch or multi-clock circuit is
needed, and in those times it helps to know how to do it right.--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11171
Subject: Re: unknown speedgrade question
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 22 Jul 1998 09:43:38 -0400
Links: << >>  << T >>  << A >>


Erik Lins wrote:

> Hello,
>
> I have three XC4020E FPGAs and I don't know the speedgrade. They seem to
> be not correctly marked.
> The full text on top is:
> XC4020E(TM)
> HQ208CKM9701
> A0321A
> some mm below there is a 2C written.
>
> Any ideas ?
>
> Thanx,
> ER!K

XC4020E-2HQ208C,  9701 is the date code

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11172
Subject: Re: unknown speedgrade question
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 22 Jul 1998 09:44:10 -0400
Links: << >>  << T >>  << A >>


Erik Lins wrote:

> Hello,
>
> I have three XC4020E FPGAs and I don't know the speedgrade. They seem to
> be not correctly marked.
> The full text on top is:
> XC4020E(TM)
> HQ208CKM9701
> A0321A
> some mm below there is a 2C written.
>
> Any ideas ?
>
> Thanx,
> ER!K

XC4020E-2HQ208C,  9701 is the date code.  The 2C is the grade

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 11173
Subject: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
From: pipjockey@my-dejanews.com
Date: Wed, 22 Jul 1998 14:27:09 GMT
Links: << >>  << T >>  << A >>
Dear Aldec,

Do you think we're that stupid?

You must.

Rob Weinstein
Memec Design Services
rob_weinstein@memecdesignDOTcom


In article <6p3gs9$2e3$1@supernews.com>,
  "MHB" <mhb@anv.net> wrote:
> Thank you all who responded to my posting of last week asking opinions of
> Active-VHDL.  My original suspicions were confirmed with overwhelming
> enthusiasm, it is a great behavioral simulator with a very intuitive user
> interface.  The hdl editor and State Diag. Editor are a nice touch, this was
> important to me especially when I evaluated Model Tech's Model Sim and
> couldn't believe they don't give you any way to enter text and have the
> nerve to charge $4600, the kicker that I loved about the Aldec tool, was the
> automatic Test Bench generator.....Great feature!!!!!! (there technical
> people were also very helpful).
>
> I never bothered looking at Orcad as my understanding is they have very good
> layout tools but their simulator basically doesn't work well.  Apparently
> there are some compliancy issues: I.e.. there vhdl simulator is not IEEE
> compliant and I am hearing nightmares or problems simulating its
> code....I'll pass on that eval.
>
> Well I am a happy camper, I just ordered Active-VHDL and recommend it to
> all.  There demo can be obtained from there web site www.aldec.com  and they
> also sent me two books which I found informative.
>
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11174
Subject: FFT in Xilinx FPGA
From: thor@sm.luth.se_nospam (Jonas Thor)
Date: Wed, 22 Jul 1998 15:46:56 GMT
Links: << >>  << T >>  << A >>
Hello,

I'm have an application where I need to perform a 8192 point FFT. The
input is only 2 bits (possibly 3 bits). Another option is to implement
a 5000 point FFT, but since this is not a power of two I guess the
implementation will be tricky.  Now I am considering to implement the
FFT in a XC4000 (or a XC6200).

Has anyone done this before, or do you know of any suitable
references?

Jonas Thor
Luleň Technical University


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