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Messages from 11200

Article: 11200
Subject: Re: Xilinx Dynatext and NTFS ?
From: Terry Fraser <noone@dont.bother.com>
Date: Fri, 24 Jul 1998 14:49:26 -0300
Links: << >>  << T >>  << A >>


George Pontis wrote:

> Has anyone got Foundation M1.4 DynaText Browser working with Windows NT
> 4.0 (SP3). I am using NTFS, which may not be a tested configuration. All
> looks good until I try to open something. For example, Libraries Guide"
> under "Xilinx Books CD". The CDROM spins for a second, and then I get the
> message "Cannot open book ...". The same thing happens for all books
> whether on CD or disk.
>
> I have checked (and corrected) the paths in dynatext.ini, and they all
> make sense. With some very quick system file monitoring I see that
> DynaText is playing fast and loose with file and directory names. For
> example, it creates a directory using mixed upper/lower case names, and
> then accesses it using a different combination of upper and lower case.
> Not that this shouldn't work, but it is the type of thing that makes me
> suspect a problem when run under NTFS.
>
> It may be worth mentioning that Dynatext worked OK on this system in
> M1.3.
> --
> George Pontis
>
> (Replies to geo at z9 dot com.)

 I have had this problem with Alliance M1.4. It seems the registry was not
setup properly. For instance, if the software was installed on a network
drive
using one PC, then you tried to run it from a different PC, the registry
entries for Dynatext were missing, and it gave the "Could not open..." error.

The solution was easy - there should be a file called 'ebtcom.reg' in the
bin\nt directory. Double clicking it loads the registry entries, and the
browser
works from then on.


--
-----
Terry Fraser
Hardware Designer
Applied Microelectronics Inc
Halifax, NS
(902) 421-1250 ext 269
fraser@appliedmicro.ns.ca

"I think it was Heisenberg, but I can't be certain"


Article: 11201
Subject: CPLD vs. FPGA
From: jamil.khatib@pemail.net (J. Khatib)
Date: Fri, 24 Jul 1998 20:03:15 GMT
Links: << >>  << T >>  << A >>
Please what is the difference between the CPLDs and the FPGAs in terms
of ( internal Arch. , logic density, speed & when can I use each one
of them) 

Thank you in advance
Article: 11202
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Sat, 25 Jul 1998 08:48:36 +1200
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> 
> Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article
> <6p8nqs$2ij$1@news1.tc.umn.edu>...
> > Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA
> > available.  The processor is compatible with the industry standard
> > 'PIC' processors.  For more information see <www.silicore.net>.
> 
> $10,000 for a PIC processor that takes up 80% of an OR2CA15-4 FPGA?  It
> would seem more prudent to buy a far less expensive exteral PIC processor
> and a smaller/cheaper FPGA to do the same job.
> 
> Does anyone else think this is a real step backwards?
> 
> Austin Franklin
> darkroom@ix.netcom.com

 This is typical of FPGA uC solutions tho. If you were moving to ASIC,
or had some real pressing reason to squeeze into one die ( and you have
to include the
ROM, or little is gained), then maybe the big hit on the $$ is a
tradeoff.
 
 Cheaper, and more powerful than a PIC, as an external procesor is the 
80C32 - these are well under $2.
 You also solve a big chunk of Testing, and Debug is a snip.

 RISC 8051s IP are now appx 10K gates, or only slightly more than the
8-9K of a
std C51.

- jg

-- 
======= Manufacturers of Serious Design Tools for uC and PLD  =========
= Specialists in Development tools for C51 cored controllers
= Leaders in Rapid Application Development SW for C51 uC
= Ask for our Controller & Tools selector Guides
= mailto:DesignTools@xtra.co.nz  Subject : Selc51Tools

Article: 11203
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Fri, 24 Jul 1998 20:49:06 GMT
Links: << >>  << T >>  << A >>
"Austin Franklin" <darkroo5m@ix.netcom.com> wrote:

>Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article
><6p8nqs$2ij$1@news1.tc.umn.edu>...
>> Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA
>> available.  The processor is compatible with the industry standard
>> 'PIC' processors.  For more information see <www.silicore.net>.

>$10,000 for a PIC processor that takes up 80% of an OR2CA15-4 FPGA?  It
>would seem more prudent to buy a far less expensive exteral PIC processor
>and a smaller/cheaper FPGA to do the same job.

>Does anyone else think this is a real step backwards?

>Austin Franklin
>darkroom@ix.netcom.com

I think I would agree with your general observation.  However, it does
make sense in specialized applications.  The product was originally
designed for sensor electronics, with very small board sizes.  For
example, the original design was done to measure pressure inside of
Pratt & Whitney jet aircraft engines.  The printed circuit board is
about the size of a large US Postage stamp, and there wasn't enough
room in their for another package.

If you have plenty of board space, then I think you're right.
However, in many sensor, medical and military applications there just
isn't enough room.

In another application, we're looking at military electronics.  Full
mil-spec parts are getting very hard to find, are expensive, and are
difficult to insure deliveries over a 10-12 year product life cycle.
However, the FPGA microcontroller solves a lot of these problems.
It's quick and easy to do, it's fully mil-spec complient, and it's
portable so that the design can be upgraded as technology advances.

Also, the FPGA design runs faster than the original PIC parts.  The
evaluation kit shown on our web page runs at the same speed as the
fastest PIC processor.  That's on a medium speed FPGA.  The design
simulates just fine at twice the speed using more state-of-the-art
parts.

Wade Peterson, Silicore Corporation
www.silicore.net  e-mail: peter299@maroon.tc.umn.edu


Article: 11204
Subject: CALL FOR PAPERS - INDUSTRY DSP FORUM AT ICASSP -99
From: "A. Spanias" <spanias@asu.edu>
Date: Fri, 24 Jul 1998 16:24:12 -0700
Links: << >>  << T >>  << A >>
      Industry DSP Technology Forum in ICASSP-99

    1999 IEEE International Conference on Acoustics, Speech,

                and Signal Processing (ICASSP)

    March 15-19, 1999,  Civic Plaza - Phoenix, Arizona, USA


ICASSP-99 is the largest and most prestigious conference in signal
processing, bringing together engineers and scientists from industry,
government, and academia. In addition to the traditional technical
program, ICASSP-99 will feature a new industrial forum highlighting
industrial aspects and applications of signal processing. We
anticipate that this forum will add a fresh dimension to ICASSP that
will hold particular appeal to industry professionals. The program
committee for the Industry DSP Technology Forum consists of industry
professionals representing many aspects of signal processing. This
committee will give strong preference to industrial submissions
describing innovative product implementations and solutions.

Papers in this forum will cover both hardware and software issues in
signal processing.  The following topics are specifically encouraged:

- DSP Chips and Architectures,
- DSP Tools and Rapid Prototyping,
- Communication Technologies,
- Adaptive Interference Cancellation,
- Automotive Applications,
- Emerging DSP Applications,
- Other (specify).

ICASSP-99 will also feature exhibits of the latest DSP hardware and
software products, plenary speakers from industry, and tutorials in
emerging signal and image processing technologies.

Submission of camera-ready papers to be received by September 14, 1998

Notification of acceptance to be mailed December 14, 1998 Early

Registration Deadline January 15, 1999

For more details on the ICASSP-99 program, tutorials, exhibits, and
detailed paper submission procedures visit: http://icassp99.asu.edu
e-mail: icassp99@asu.edu


Conference Co-Chairs:    Andreas Spanias and Douglas Cochran
                             Arizona State University


Industry DSP Technology Forum:  Bruce Fette, Motorola Inc.
                                Tom Gardos, Intel Corp.


Industry Liaison:   Will Strauss, Forward Concepts


Conference Manager:    Billene Mercer, CMS,  Phone: (409) 693-6000








Article: 11205
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Sat, 25 Jul 1998 00:26:55 GMT
Links: << >>  << T >>  << A >>
Anyone wishing to wing it with a homebrew synthesizable PIC, try mine
at:
    www.mindspring.com/~tcoonan

I'm sure their's is more polished and may have more tools, but mine
is free as long as you have the energy to verify and modify it.  Let
me know if anyone uses it, or needs help applying it.

tom coonan
Scientific Atlanta
tcoonan@mindspring.com

>Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article
><6p8nqs$2ij$1@news1.tc.umn.edu>...
>> Silicore Corporation now has a VHDL 8-bit RISC uC core for FPGA
>> available.  The processor is compatible with the industry standard
>> 'PIC' processors.  For more information see <www.silicore.net>.
>
>$10,000 for a PIC processor that takes up 80% of an OR2CA15-4 FPGA?  It
>would seem more prudent to buy a far less expensive exteral PIC processor
>and a smaller/cheaper FPGA to do the same job.
>
>Does anyone else think this is a real step backwards?
>
>Austin Franklin
>darkroom@ix.netcom.com
>

Article: 11206
Subject: Re: Schematic Symbol Generation
From: "Austin Franklin" <darkr2oom@ix.netcom.com>
Date: 25 Jul 1998 01:01:06 GMT
Links: << >>  << T >>  << A >>


Austin Franklin <darkroo5m@ix.netcom.com> wrote in article
<01bdb70d$3d65edf0$67c220cc@drt3>...
> 
> 
> mbitzko@my-dejanews.com wrote in article
> <6p2qr3$67p$1@nnrp1.dejanews.com>...
> >   Schematic symbol creation is a error prone time consuming effort.
> > SymBuilder(tm) automates the creation of heterogeneous schematic symbol
> sets
> > from fpga compiler reports, from spread sheets, and the content
provided
> in
> > pdf data sheets.  Export interfaces include OrCAD, Protel, and McCAD
for
> > SymBuilder Personal and Cadence, Mentor Graphics, and Viewlogic for
> > SymBuilder Enterprise. For additional information, refer to
> > http://www.ccaes.com.
> 
> Along with being sort-of-SPAM, isn't it funny how so many EDA companies
> fail to post pricing...either in posts or even on their web sites.  I
> really don't want to talk to some sales person (who usually just wants to
> get all my particulars and add me to some SPAM data base so they can
call,
> mail or e-mail me) before they will give me any pricing information.  All
I
> just want to know if the product is economically feasable.  It really
> amazes me.

Well, I looked into pricing (which actually only took two e-mails ;-), and
they offer an NT Viewlogic version for $399 (though their web site doesn't
say that....yet).  That's not unreasonable at all...it may be worth
checking out ;-)

Austin

Article: 11207
Subject: Cheap FPGA...
From: Dogma <nienhuis@csis.gvsu.edu>
Date: Fri, 24 Jul 1998 22:14:46 -0400
Links: << >>  << T >>  << A >>
I'm looking for a cheap FPGA setup.  I'd like to be able to have a device
that's programable at ~100k useable gates.  Also I'd like it if it didn't
need special HW to program it.  I'm looking at just whiping together a
programmer with a serial port and a microcontroller.  I'd want to use it
to test out one CPU ideas I've been mucking about so I'm considering a
XILINX solution.

							-Rich N

Article: 11208
Subject: Caluclation of gates in FPGA
From: satish@my-dejanews.com
Date: Sat, 25 Jul 1998 06:00:27 GMT
Links: << >>  << T >>  << A >>
Hello Sir
 I am having a simple C code
 # include <stdio.h>
 main()
 {
 unsigned char a=9,b=23,c;

  c= a+b;  } The same can be converted into VHDL by declaring the bit vector
of size 8 bits to each variable. Now my problem is how to caluclate the
number of gates it is going to take for execution in Xlinx XC4004EX series.
Even let it be at any series, I want to have the number of gates required to
execute the above simple program Let any body help me Thanks in advance
Please reply to my email address:satish_me@hotmail.com

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11209
Subject: Delay Element for async design.
From: Eddie Ng <ngeddie@tor.shaw.wave.ca>
Date: Sun, 26 Jul 1998 02:10:51 GMT
Links: << >>  << T >>  << A >>
Dear All,
    I'm using Altera FLEX 10K series FPGA right now and I need to
implement an delay element that would do ideally pure delay or
not-too-bad inertial delay.  Much like a series of even-numbered
inverters in series to introduce propagation delay but with accurate
delay time, preferrably "programmable" or "parameterizable".
    I'm using it to implement an asynchronous micropipeline structure in
which delay is added on the control signals to match/exceed the delay on
the bundled data lines to meet the bundled contrains.
    Thanks for any ideas and help.

Eddie
--
===========================
Eddie Ng
ngeddie@ecf.toronto.edu

Class 9T8+PEY
Electrical Option,
Engineering Science
University of Toronto
===========================


Article: 11210
Subject: Re: Delay Element for async design.
From: YetAnotherLurker - Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 26 Jul 1998 00:26:54 -0400
Links: << >>  << T >>  << A >>
Eddie Ng wrote:
> 
> Dear All,
>     I'm using Altera FLEX 10K series FPGA right now and I need to
> implement an delay element that would do ideally pure delay or
> not-too-bad inertial delay.  Much like a series of even-numbered
> inverters in series to introduce propagation delay but with accurate
> delay time, preferrably "programmable" or "parameterizable".
>     I'm using it to implement an asynchronous micropipeline structure in
> which delay is added on the control signals to match/exceed the delay on
> the bundled data lines to meet the bundled contrains.
>     Thanks for any ideas and help.
> 
> Eddie

Eddie,

You can do this if you keep in mind the limitations of the hardware you
are working with. When you ask for "accurate" delay time, you are trying
to do something that the hardware will not support. Although the data
book gives you nice solid numbers, the delay through any given element
is not a constant. It varies over temperature, supply voltage and
process variations. The chip manufacturer will even ship you parts
marked for a given speed grade, but may well qualify for a much faster
grade. So you will have very little control over the actual delay in the
elements on the chip. I have seen parts that were redesigned for
manufacturability where some sections of the chip were greatly
accelerated, while other sections weren't. This was not an FPGA, but the
point is that vendors change their designs and are only "required" to
meet the worse case specs, not typical. 

If you just need to generate a splinter pulse, there are ways to do
that. But if you need a calibrated delay line, then you should use a
calibrated delay line. I am not totally clear on what you are trying to
do, but it doesn't sound like something that will be pratical in most
hardware.
Article: 11211
Subject: Re: Schematic Symbol Generation
From: hamish@moffatt.nu (Hamish Moffatt)
Date: 26 Jul 1998 11:13:15 GMT
Links: << >>  << T >>  << A >>
Austin Franklin <darkroo5m@ix.netcom.com> wrote:
> Along with being sort-of-SPAM, isn't it funny how so many EDA companies
> fail to post pricing...either in posts or even on their web sites.  I
> really don't want to talk to some sales person (who usually just wants to
> get all my particulars and add me to some SPAM data base so they can call,
> mail or e-mail me) before they will give me any pricing information.  All I
> just want to know if the product is economically feasable.  It really
> amazes me.

Excellent point. As a student, I want to know whether a product is
shall we say "enterprise-priced" or whether it is in the reach of
students. I recently went through the whole email + phone call from sales
rep etc just to get a quote on an X Windows server, only to find out
that it was over $1000 (still a good product, mind you).

Hamish
-- 
Hamish Moffatt, StudIEAust              hamish@debian.org, hamish@moffatt.nu
Student, computer science & computer systems engineering.    4th year, RMIT.
http://hamish.home.ml.org/ (PGP key here)             CPOM: [*******   ] 70%
Matter cannot be created or destroyed, nor returned without a receipt.
Article: 11212
Subject: Re: C- interface
From: APS <resp@associatedpro.com>
Date: Sun, 26 Jul 1998 10:44:37 -0400
Links: << >>  << T >>  << A >>
Check out the solutions at http://www.associatedpro.com

bonics@my-dejanews.com wrote:

> Hello ,
> I am working on the connection of a hardware prototyping board to the Leapfrog
> VHDL simulator of Cadence.
>
> I have found some interfaces on the market ,e.g. logic modeler, by Synopsys
> ,but would like to hear any other possible solution from you.
>
> I also tried to integrate some C functions on the simulator ,following the
> help manual ,but it does not work. Any solutuions ? Thank you very much in
> andvanced . Benjamin
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 11213
Subject: Re: Delay Element for async design.
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Sun, 26 Jul 1998 15:42:55 GMT
Links: << >>  << T >>  << A >>
Eddie Ng <ngeddie@tor.shaw.wave.ca> wrote:

>Dear All,
>    I'm using Altera FLEX 10K series FPGA right now and I need to
>implement an delay element that would do ideally pure delay or
>not-too-bad inertial delay.  Much like a series of even-numbered
>inverters in series to introduce propagation delay but with accurate
>delay time, preferrably "programmable" or "parameterizable".

The only thing you can really do is add a delay-counter type of
circuit.  If you need fairly repeatable delays, it's best to add a
delay line outside of the package.  These are available from several
manufacturers, and really work great.  The only bad thing is that you
have to add a part outside of the FPGA or ASIC.

Wade Peterson
Silicore Corporation


Article: 11214
Subject: Re: Delay Element for async design.
From: Eddie Ng <ngeddie@tor.shaw.wave.ca>
Date: Sun, 26 Jul 1998 17:48:46 GMT
Links: << >>  << T >>  << A >>
>

Rickman,

> You can do this if you keep in mind the limitations of the hardware you
> are working with. When you ask for "accurate" delay time, you are trying
> to do something that the hardware will not support. Although the data
> book gives you nice solid numbers, the delay through any given element
> is not a constant. It varies over temperature, supply voltage and
> process variations. The chip manufacturer will even ship you parts
> marked for a given speed grade, but may well qualify for a much faster
> grade. So you will have very little control over the actual delay in the
> elements on the chip. I have seen parts that were redesigned for
> manufacturability where some sections of the chip were greatly
> accelerated, while other sections weren't. This was not an FPGA, but the
> point is that vendors change their designs and are only "required" to
> meet the worse case specs, not typical.
>
> If you just need to generate a splinter pulse, there are ways to do
> that. But if you need a calibrated delay line, then you should use a
> calibrated delay line. I am not totally clear on what you are trying to
> do, but it doesn't sound like something that will be pratical in most
> hardware.


Thanks for you reply.  I realize that propagation delay in FPGA depends on
other factors that you've mentioned.  So I think what I need is to implement
an delay element that would guarrantee the minimum propagation delay.
Here is where I'm gonna use it :
In an asynchronous micropipeline structure, data lines are bundled together
(much like a databus) and the flow of data through each stage of the pipeline
is controlled by the 2-phase (NRZ) req and ack protocol (dislike the use of a
global clock in a synchronous pipeline).  However, one timing restriction in
this model is, the bundled data lines has to be stable (as seen by the next
stage in the pipeline) before the req line gets there.  The speed of the data
lines will be restricted by the propagation delays of the logic block in that
stage.  Therefore, an delay element is needed on the req line to ensure the
req line gets to the next stage after the data lines do (bundled contrains).
i.e. MIN(delay in req) > MAX(logics delay in data).  Given I can calculate the
max logics delay in data, all I need is to implement the delay in req with a
guarranteed min.  And I'm restricted to Altera FLEX10K series.
    I hope that would give you an insight as to what I'm trying to do here.
    Thank you very much.

Eddie

Article: 11215
Subject: Re: Caluclation of gates in FPGA
From: yhirbawi@my-dejanews.com
Date: Sun, 26 Jul 1998 18:16:47 GMT
Links: << >>  << T >>  << A >>
In article <6pbs9s$q4j$1@nnrp1.dejanews.com>,
  satish@my-dejanews.com wrote:
> Hello Sir
>  I am having a simple C code
>  # include <stdio.h>
>  main()
>  {
>  unsigned char a=9,b=23,c;
>
>   c= a+b;  } The same can be converted into VHDL by declaring the bit vector
> of size 8 bits to each variable. Now my problem is how to caluclate the
> number of gates it is going to take for execution in Xlinx XC4004EX series.
> Even let it be at any series, I want to have the number of gates required to
> execute the above simple program Let any body help me Thanks in advance
> Please reply to my email address:satish_me@hotmail.com

Xilinx used to have a design note on how to do these estimates. You should be
able to track that down at their website. The rules of thumb to keep in mind
are something like this :

  for an n-bit adder :
        10*n gates (average between ripple and carry-look-ahead)
  for a parallel multiplier (n-bits by m-bits):
        10*n*(m+1) gates

Jacob Hirbawi

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/rg_mkgrp.xp   Create Your Own Free Member Forum
Article: 11216
Subject: Re: CPLD vs. FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sun, 26 Jul 1998 17:29:23 -0700
Links: << >>  << T >>  << A >>
Though basic and slightly out of date, there's a comparison table at
http://www.optimagic.com/comparison.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

J. Khatib wrote in message <35b9e5ec.784228@news.planet.edu>...
>Please what is the difference between the CPLDs and the FPGAs in terms
>of ( internal Arch. , logic density, speed & when can I use each one
>of them)
>
>Thank you in advance


Article: 11217
Subject: When did You last give Your wife a romantic holiday?
From: by_the_lake@jboat.com
Date: 27 Jul 98 02:10:05 GMT
Links: << >>  << T >>  << A >>

Hi! I posted this using an unregistered copy of Newsgroup AutoPoster PRO!
You can download your own copy for FREE from: http://www.autoposter.cc
or just click this line: http://www.autoposter.cc/files/newspro1.exe
---
 When did You last give Your wife a romantic holiday?
 This is the chance for You to show her what she really means to You.
 Come to Sweden and live in a nice cottage on the countryside without lots of people.
 Let us serve You so You two don't have to do anything else than just relax.
 How about some romantic trips to different famous places in the south of Sweden?
 Or just late evenings in front of an open fire in the cottage?, maybe eating the fish that You caught earlier during the day.
 Do You two like adventures? Then try on water-skiing or flying helicopter.
 Give Your wife a special memory which will last for her whole life.
 Take this chance and relax from all work and stress and let us do the work instead.
 To get more information, go to our website and find out what's the best for Your romantic holiday.
 Visit  <URL:http:// www.by_the_lake.jboat.com/>   .

Article: 11218
Subject: FloorPlanning with some examples
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 27 Jul 1998 07:56:21 GMT
Links: << >>  << T >>  << A >>
Recently there was a thread on this news group about floorplanning.

It has taken me awhile to put my comments together.

Questions were asked about how to do it, and whether it was worth doing
for the newer devices with lots of routing.

So I could post my answer here, but it is about 60K of text, and 
then there is about another 100K of GIF images. That would be a little
too much binary in a non binary group.

So instead, I have put it on my web site, and if you are interested, you 
can go look at it.

But first, some warnings. The material is adapted from the manual for a
commercial product I am developing, and so it has references to that
product in it (FLIB). Second it is a work in progress, so it does not have
all the info that I want to write on the topic. Third, although it
contains more text than the manual (while adapting it for the web, I
improved it a lot), it only contains the chip views for 1 of 8 sets of
data presented (just to save download time). Lastly, if you aren't working
with one of the Xilinx XC4000 families, it isn't going to be very relevent
to you. 

On the bright side, it has data for both PPR and PAR, working on XC4005E,
XC4010E, XC4010XL, with 7 iterations of floorplanning strategy, and 
documents placement time, routing time, and design performance for a 
total of 56 different combinations of the tools, chips, and strategies.

Graphic floorplans are included for PAR on XC4010XL, for 7 different 
strategies.

Note also, that this is my first attempt at doing a reasonable web page,
and the underlying structure was developped for me by OptiMagic.

	http://www.fliptronics.com/fp1.html

Please let me know if this was worth the effort.

Philip Freidin
philip@fliptronics.com
Article: 11219
Subject: ANNOUNCE: Design Entry Workshop
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Mon, 27 Jul 1998 15:29:00 +0100
Links: << >>  << T >>  << A >>
Educational ECAD User Group Workshop
University of Sussex
9th - 10th September 1998

The 22nd EEUG Workshop will be held at the University of Sussex
at Brighton on the 9th and 10th of September 1998.  The topic
for the workshop is "Design Entry - HDLs vs. Schematics" and
it will discuss the relative merits of the two approaches for
teaching and research.

In addition to the presentations noted in the programme below, the
workshop will include the usual EEUG update sessions on EDEC,
RAL and Liaison committee business.

The cost for overnight attendees will be 66UKpounds, which includes
dinner and accommodation on the 9th and breakfast, lunch, tea
and coffee on the 10th.  The cost for attending only for the
day on the 10th will be 30UKpounds, which includes lunch, tea and
coffee.

Please circulate this information to your colleagues.

----------------------------------------------------------

Programme

Weds 9 September
7.00 pm     Dinner
8.30 pm     Lecture and demonstration of Synplicity
            by Darren May of ALT Technologies Ltd
Bar

Thurs 10 September
      8.45 a.m.   Registration
      9.15 a.m.   Chairman's Welcome - Mike English (Sussex)
      9.20 a.m.   HDLs in an Electronics degree course -
                  a systematic progression
                  Tim Forcer (University of Southampton)
      9.45 a.m.   Learning from the Softies
                  Jonathan Bromley (Oxford Brookes University)
      10.10 a.m.  Introducing VHDL design case studies
                  in EE degree programmes
                  David Holding (Aston University)

      10.35 a.m.  Coffee and RAL Roadshow

      11.05 a.m.  Design Entry vs. Resourse Utilisation
                  in Altera Max+ plus
                  Jim Proudfoot (University of Wales, Swansea)
      11.30 a.m.  VHDL design flow for computer graphics
                  ASICs & FPGAs
                  Iakovos Stamoulis, (University of Sussex)
      11.55 a.m.  EDEC Update
                  Peter Hicks (UMIST)

      12.20 p.m.  RAL Roadshow &
                  Lunch

      2.15 p.m.   RAL Software Support update
                  Dr John McLean (RAL)
      2.40 p.m.   Liaison Committee Report
      3.00 p.m.   Tea & Close

----------------------------------------------------------

For Registration and other details, including email and fax versions of
the registration form, please contact
Dr S. Harrold s.harrold@umist.ac.uk or
Dr M.J. English m.j.english@sussex.ac.uk

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
The University of Southampton, UK

The University is not responsible for my opinions
Article: 11220
Subject: [Q] motor control onto an FPGA
From: Paul Oh <paul@moray.cs.columbia.edu>
Date: Mon, 27 Jul 1998 12:52:22 -0400
Links: << >>  << T >>  << A >>

Hello to all in comp.arch.fpga

I am newbie to FPGA.  I am looking into programming my own silicon.  Can
any one give pointers (books, websites) into developing motion control
IC's?

Specifially: PID (proportional-integral-derivative) control
Trapezoidal motion profiles

Thanks very much.  

PS: I have *never* programmed FPGA's before (I am a mechie).  I have a
high-level understanding of the design process: Essentially you burn an
FPGA just like an EPROM right using schematic CAD or C-like programming
languages right? I intend to use Xilinx's development
board/tools.  I do have a good grasp on logic, digital design, control
systems, programming and embedded micros though.


----------------------------------------------------------------------------
Paul Oh                 
PhD Candidate
Columbia University
Dept of Mechanical Engineering
Center for Research in Intelligent Systems
http://www.cs.columbia.edu/~paul
----------------------------------------------------------------------------



Article: 11221
Subject: Re: How to write a VHDL counter of up & down
From: "Mark Purcell" <map@NOSPAM_transtech-DSP.com>
Date: 27 Jul 1998 17:05:24 GMT
Links: << >>  << T >>  << A >>
If you have loads of gates to spare:

Define two independent counters and make them both gray coded. 
These are the 'up' and 'down' counters, but both count in the same
direction.
To read the difference between the two, sample them both with another clock
(both counters will at worst be in transition in one bit, sampling either
value 
is valid). Use a gray subtractor circuit to measure the difference of the
samples.
Both 'up' and 'down' clocks can then be totally asynchronous to each other.

A VHDL description of that shouldn't be too difficult (three clocked
processes 
and a combinatorial process). A little thirsty on gates maybe...

Mark P  :-)

P.S. remove NOSPAM_ from email address.

leslie.yip@asmpt.com wrote in article <6out36$l0j$1@nnrp1.dejanews.com>...
> Hello Everybody
>
> I don't know how to implement my previous ASIC-design counter with 2 edge
> triggers -- up and down (up => increment the counter by 1; down [i.e. dn]
=>
> decrement the counter by 1) I used logic gates to implement this function
but
> it seems difficult to describe this with VHDL. I know that another
writing of
> up-down counter is to use a pin to control up/down and another is just a
> clock for incrementing / decrementing the counter.
> 
> My 4-bit counter, however, uses four 4-bit counter to connect together
by:
> Carry => UP
> ('Carry' of lower-bit counter connected to 'UP' of another counter)
> Borrow => DN
> 
> Below is a correct but unsynthesizable (by ViewLogic) code of 16-bit
counter.
> Could anyone tell me any idea?
> Thanks a lot in advance.
> 
<snip> 

Article: 11222
Subject: Re: Shift Invarient Bit Transform
From: Thor Arne Johansen <thorj@ibas.no>
Date: Mon, 27 Jul 1998 21:43:16 +0200
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> 
> I need a hardware implementation to find a unique number for a bit pattern
> that is shifted.
> Below is a four bit example although our requirements are for something
> larger:
> Input  > Transform
> 0000 > 0000
> 0001 > 1000
> 0010 > 1000
> 0011 > 1100
> 0100 > 1000
> 0101 > 1010
> 0110 > 1100
> 0111 > 1110
> 1000 > 1000
> 1001 > 1001
> 1010 > 1010
> 1011 > 1011
> 1100 > 1100
> 1101 > 1101
> 1110 > 1110
> 1111 > 1111
> Obvisously, all I did here was to shift the input pattern until it
> maximised.  The output of the transform is shift invarient, ie. 0001 maps to
> the same number as 0100. We are considering doing this,shifting and testing
> for max, however, it takes a lot of clock cycles. I would rather have a
> logic gate solution. A look-up-table approach is too costly for the input
> width we have in mind.  The transform can also compress data, for example,
> the 4 bit example above has 16 input vectors and maps to only 10 outputs.
> Thanks in Advance,
> Brad Smallridge
> www.sightech.com

Isn't this similar to matched filter signal detection?

What is your actual requirements?
What is the width of your input vectors?
What are the allowed input patterns, and all patterns equiprobable?
Can you tolerate latency?



-- 
Thor Arne Johansen
Ibas Laboratories, Norway              
http://www.ibas.no

Article: 11223
Subject: Re: Delay Element for async design.
From: husby@fnal.gov (Don Husby)
Date: Mon, 27 Jul 1998 20:21:52 GMT
Links: << >>  << T >>  << A >>
ngeddie@ecf.toronto.edu wrote:
>     I'm using Altera FLEX 10K series FPGA right now and I need to
> implement an delay element that would do ideally pure delay or
> not-too-bad inertial delay.  Much like a series of even-numbered
> inverters in series to introduce propagation delay but with accurate
> delay time, preferrably "programmable" or "parameterizable".

With Xilinx or Orca chips, you can route a signal through an unbonded
(or bonded) pad.  The inputs buffers have a delay element that is fairly
predictable.

I've often wondered how well a gray-code delay line would work.
If you implement a 4-bit gray-code incrementer with its output fed
back to its input, would it provide a predictable delay or would
it oscillate and melt down the chip?

Something like this timing diagram: 
IN   000 1 1 1 1 1 1 1 1 1 1111 0 0 0 0 0 0 0 0 0 000000
G0   000 0 1 1 0 0 1 1 0 0 0000 0 1 1 0 0 1 1 0 0 000000
G1   000 0 0 1 1 1 1 0 0 0 0000 0 0 1 1 1 1 0 0 0 000000
G2   111 1 1 1 1 0 0 0 0 0 0000 0 0 0 0 1 1 1 1 1 111111
OUT  000 0 0 0 0 0 0 0 0 1 1111 1 1 1 1 1 1 1 1 0 000000

Where:

G0 = In^G2^G1
G1 = /(In^G2)*G0 + G1*/G0
G2 = /In* G1*/G0 + G2 * /(G1*/G0)
Out= /(In* (G1+G0) + G2 * /(G1+G0))

Article: 11224
Subject: Re: [Q] motor control onto an FPGA
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Tue, 28 Jul 1998 02:34:02 GMT
Links: << >>  << T >>  << A >>
>
>Hello to all in comp.arch.fpga
>
>I am newbie to FPGA.  I am looking into programming my own silicon.  Can
>any one give pointers (books, websites) into developing motion control
>IC's?
I'll just throw out some random thoughts..
So, sounds like you can express your PID in terms of Ts, Kp, Ki, and
Kd.  Any simplification in terms of ranges of coefficients can help -
multipliers can be expensive in hardware.  Think about clocks - how
your system clock will relate to your Ts.  Keep everything
synchronous!  Anything you can simulate up-front in C/Matlab will save
you many tedious HDL simulations.  Use your C/Matlab to refine what Ts
is and what number ranges are satisfactory (do you need 8-bit
variables or 16-bit quantities, is Ts=1KHz OK or do you need 1MHz?)
To save on hardware resources, you *might* want to explore Distributed
Arithmetic (serializing math) approaches.  But then, if you can afford
the silicon, a straight parallel approach is much more straight
forward and you are new at this.  I think you want to refine your
control system design, and then re-implement it in Verilog or VHDL and
make sure your step responses, etc. match one another.  I think you
need to get access to a general purpose Verilog or VHDL simulation
environment since you're doing some subtle control loop stuff.  Be
careful in that some FPGA tools offer HDL, but sometimes the
simulators are highly constrained and would be unable to really
simulate your plant and system (e.g. WARP used to be that way - I
haven't seen their stuff in years, though).  Beyond that, implementing
a Verilog/VHDL synchronous design in an FPGA is a more general
question.  I believe I've seen App notes by either Cypress or ACTEL on
PID control.

This is a fun topic to me, contact by email if you'd like.

tom coonan
scientific atlanta
tcoonan@subasic.sciatl.com
>
>Specifially: PID (proportional-integral-derivative) control
>Trapezoidal motion profiles
>
>Thanks very much.  
>
>PS: I have *never* programmed FPGA's before (I am a mechie).  I have a
>high-level understanding of the design process: Essentially you burn an
>FPGA just like an EPROM right using schematic CAD or C-like programming
>languages right? I intend to use Xilinx's development
>board/tools.  I do have a good grasp on logic, digital design, control
>systems, programming and embedded micros though.
>
>
>----------------------------------------------------------------------------
>Paul Oh                 
>PhD Candidate
>Columbia University
>Dept of Mechanical Engineering
>Center for Research in Intelligent Systems
>http://www.cs.columbia.edu/~paul
>----------------------------------------------------------------------------
>
>
>



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