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Messages from 13600

Article: 13600
Subject: Re: HELP, Tool selection
From: David Pashley <David@edasource.com>
Date: Fri, 11 Dec 1998 12:33:01 +0000
Links: << >>  << T >>  << A >>
In article <36704290.879245@nntp.netcruiser>, Stuart Clubb
<s_clubb@NOSPAMnetcomuk.co.uk> writes
<snip>
>On Tue, 8 Dec 1998 10:00:03 +0000, David Pashley <David@edasource.com>
>wrote:
>>5 years ago, if, as an EE, you knew VHDL, then you were a prized
>>specimen. If I'm right, before long, designers who can work at the gate
>>level and drive schematic editors will be the rare and sought-after
>>commodity.
>
>I used to draw P and N wells and shove polygons of "active area",
>metal and polysilicon around and then connect them up with little
>black crosses. I haven't seen too much demand for that recently.
>
Never much call for that with FPGAs (the subject here)! Many of the most
talented and productive designers of FPGAs small and large still use
schematics for good reasons that are frequently discussed here. I don't
think that they are about to trash Viewdraw and go to synthesis only
when they can have the best of both worlds. Neither are they going to
use Renoir ($20k? $30k?) to do block diagrams and schematics instead of
Viewdraw ($2k or less).

<snip>

>Without wishing to appear rude, do you know what Renoir is, and does?

Let me see. It's a very expensive tool, only affordable to high-end ASIC
designers, that takes block diagrams and graphical state machines and so
on and turns them into thousands of lines of nasty machine-generated
VHDL ;-)

Whereas Viewdraw is a low-cost tool that provides schematic design at
both gate-level (for creating high performance low-level stuff) and high
level (block diagrams, like Renoir), giving FPGA users the best of both
worlds.

The whole design is then presented to FPGA Express for synthesis, which
accepts both VHDL/Verilog and EDIF blocks from Viewdraw within a single
design. The whole process is managed by Intelliflow.

I would say, in conclusion, that many of your comments are more
appropriate to ASIC design than FPGA. 

David

-- 
David Pashley                    <
 ---------------------------  <  <  <  --- mailto:david@edasource.com
| Direct Insight Ltd       <  <  <  <  >   Tel: +44 1280 700262      |
| http://www.edasource.com    <  <  <      Fax: +44 1280 700577      |
 ------------------------------  <  ---------------------------------

Article: 13601
Subject: Re: HELP, Tool selection
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 11 Dec 1998 09:24:56 -0500
Links: << >>  << T >>  << A >>
Stuart,
can you create relatively placed macros with this tool flow, or are you
forced to put placement info in the flat constraints file (either by hand or
through attributes in the VHDL)?  The problem with instantiating components
like the CY4 is that you NEED to put RLOCs on it for the PAR tool to be able
to use them...they need to be placed in specific locations relative to one
another.  So far, the HDL tools I've looked at don't make this easy.

Stuart Clubb wrote:

> On Tue, 8 Dec 1998 10:00:03 +0000, David Pashley <David@edasource.com>
> wrote:
>
> >In the "olden days" of digital design, we used to talk about
> >hierarchichal and top-down design (now called "re-use"). At the bottom
> >level of these designs would be gate-level schematics, very efficiently
> >designed with the target architecture in mind. Because we would put the
> >bottom-level modules in a library and re-use them either directly, or
> >modified, the trick was to make them as fast and small as possible.
>
> The trick was also that we didn't have a 100K gate FPGA to fill and
> get out in the same time as the 25K gate one we did the year before.
> Hence why I advocate that designers do as much in HDL as possible to
> keep independent, and then only do the things they really have to do
> by hand (schematics, or structural HDL).
>
> >Hand drawn schematics are often many times more efficient than what a
> >synthesis tool can produce. Of course you can't start out on a 200,000k
>
> <CHEAP_SHOT ON>
> Many times? If you talk about FPGA Express, maybe :-)
> <CHEAP_SHOT OFF>
>
> >gate design with just a schematic editor. But a mixed approach, with
> >highly efficient, schematic-drawn reusable elements alongside
> >synthesized modules at the bottom level, and perhaps with a block
> >schematic at the top does make sense. And this approach is more widely
> >used than you may think.
>
> Oh, I would agree. The block diagram is an improvement on a log-book
> or the back of an envelope, but this is just some of what Renoir is
> about.
>
> >5 years ago, if, as an EE, you knew VHDL, then you were a prized
> >specimen. If I'm right, before long, designers who can work at the gate
> >level and drive schematic editors will be the rare and sought-after
> >commodity.
>
> I used to draw P and N wells and shove polygons of "active area",
> metal and polysilicon around and then connect them up with little
> black crosses. I haven't seen too much demand for that recently.
>
> >The portability and productivity of HDL-based design are of undoubted
> >benefit, but there is no reason to abandon the performance advantages of
>
> Agree. The best flow is the one that gets a working product out the
> door, to spec, and under budget.
>
> >designing with schematics, while we can do both together. Given the
> >right tools, of course. ;-)
>
> Whoa! I just have to respond to that (good natured, I'm sure) swipe.
> (With apologies to all for what might appear to be an infomercial)
>
> Without wishing to appear rude, do you know what Renoir is, and does?
>
> I can create a top level "schematic" block diagram. I can then push
> down into these blocks and create:
>
> Another block diagram
> A State machine
> A Truth Table
> A Flow Chart
> My own HDL
>
> I can create my own packages and libraries. I can have multiple
> implementations of components defining which is to be the default
> *view* used in a particular build. HDL to Graphics imports HDL files
> and turns them, where possible, into graphics. Useful for working back
> from old designs, or understanding customer designs quickly), or
> documentation and maintenance. It's also OLE compliant, so
> documentation becomes a little easier.
>
> With libraries, I can even directly use FPGA gate-level components,
> such as from Xilinx, right down to AND2B1 and all those little CY4
> elements if I need them. I can instantiate anything I like (design
> re-use?) and stick designs in libraries for later. I just plonk them
> on a schematic sheet, and wire them up as needed. (but they are all
> VHDL or Verilog, not a proprietary netlist format)
>
> I can even have a top level VHDL Entity that calls a Verilog previous
> library core, which instantiates a VHDL Entity as a module, which
> instantiates some 'gates', no problem, ad nauseum. No fighting to
> co-ordinate three separate simulation kernels. All done in one kernel
> - ModelSim, and all running quite happilly on a laptop. Plus many
> orders of magnitude faster at functional simulation than a gate level
> schematic sim (I would imagine?).
>
> I've got Renoir source cross-probing to either Spectrum or Turbo
> Writer. I can even click a transition in a state machine diagram and
> go right to the code that it generated.
>
> An important point with this HDL-centric flow is that the whole design
> output is HDL text files (VHDL or Verilog). This helps to maintain
> vendor independence of the design as much as possible. Not only in
> terms of target technology, but also in terms of simulator, synthesis
> and other downstream tools post design entry. I'm not sure I could run
> a code-coverage tool on your proprietary gate-level schematic and
> block diagram mixed with written VHDL and a state machine from
> State-Cad, could I?
>
> At the end of the day, you can even walk away with your whole Renoir
> design (ie. all your intellectual property) as a bunch of plain text
> HDL and go simulate it and synthesise it however and wherever you
> like. I think that the absence of a proprietary format has some appeal
> for the longevity and maintenance of old designs.
>
> If you want to call Renoir "schematics", I guess you can, as it does
> indeed involve drawing diagrams. However, keeping with HDL brings all
> the benefits, plus those of a far more productive environment than
> just symbols, nets and 'gates'. (IMHO)
>
> That's it.
>
> Cheers
> Stuart
>
> An employee of Saros Technology, The HDL Solutions Company:
> Renoir
> Model Technology
> Exemplar Logic
> TransEDA
> www.saros.co.uk
> (I sell these products, so paint me biased)



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13602
Subject: Re: Need basic info on FPGA!
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 11 Dec 1998 09:34:14 -0500
Links: << >>  << T >>  << A >>
My goodness!
Get on line and look in the xilinx data book (www.xilinx.com.  There is
detailed information in there about the structure of the CLB's and IOBs.
Macros of course, are just mini-designs for the FPGA that you can use as
building blocks for a larger design to speed up you design (you wouldn't want
to design a processor using at the gate level).

TNT wrote:

> Hi
>
> We are engineering sudents working on a projekt that involves basic
> knowledge on FPGA.
> Our main purpose is to implement by C++,  the intension though is to end up
> with programming a Xilinx XC 4010 XL.
> What we need at this point is an introduction to the following:
>
>     - CLB
>     - LUT
>     - Macro's
>     - The basic's of gate arrays
>
> The only documentation on the subjekt we have so far is the "The practical
> Xilinx designer lab book".
>
> Thank you for any contribution what so ever.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13603
Subject: Re: HELP, Tool selection
From: David Pashley <David@edasource.com>
Date: Fri, 11 Dec 1998 14:40:20 +0000
Links: << >>  << T >>  << A >>
In article <36731bf1.252389827@news.netcomuk.co.uk>, Peter <z80@ds2.com>
writes
>
>>Also, I note that the most vehement and ill-informed complainers are the
>>anonymous ones such as yourself (and e.g. the initiator of the "Will
>>Xilinx survive" thread"), who are willing to put their Usenet
>>reputation, but *not* their personal or professional reputation on the
>>line.
>
>You must be confusing *me* with someone else.
>
>Note also, that for non-UK readers (which is about 95% of the net)
>your signature (Direct Insight Ltd) might as well be anonymous too.
>Only a small selection of UK engineers will recognise it as a vendor
>of high-end EDA software.

None of that is correct. But anyway, by definition, it's those who *do*
know me whose opinion matters. I therefore check my facts and try to
talk sense.
>
>I am not sure what you want. Everyone in usenet to register a PGP
>public key with some 3rd party, and PGP-sign all their posts? Nothing
>short of that will mean anything - IF you are to allow people to post
>their *private* opinions at all.
>
Just use your real name and organization. Or tell us why you won't.

>>My company has declined to respond to your own past untrue criticisms
>>for these reasons, 
>
>Please produce examples if you can where something **I** said was "ill
>informed" or was an "untrue criticism".
>
OK. For example: 

In article <35de28bf.941553702@news.netcomuk.co.uk>, Peter <z80@ds1.com>
wrote:
...
> could rant on for hours about this s****y
>company and their software support policies...
>
>The Chiplab-48 is now well obsolete (it was obsolete, in the sense of
>there being no new device development for it, for 1-2 years while it
>was still being sold
< a lot more ranting snipped>

For your information, the product you are denigrating - which we sell
and support in UK - is not only not obsolete, but new device support
development has never stopped, and is continuing today and into the
future.

David
-- 
David Pashley                    <
 ---------------------------  <  <  <  --- mailto:david@edasource.com
| Direct Insight Ltd       <  <  <  <  >   Tel: +44 1280 700262      |
| http://www.edasource.com    <  <  <      Fax: +44 1280 700577      |
 ------------------------------  <  ---------------------------------

Article: 13604
Subject: Re: Synthesis with Actel
From: rich katz <rich.katz@gsfc.nasa.gov>
Date: Fri, 11 Dec 1998 10:37:51 -0500
Links: << >>  << T >>  << A >>
hint (having gotten the code, modified it, and gotten it to synthesize):

w/ actmap, the array names do not make unique entities; they are concatenated
with the index to make an internal name.  so, if you have an array:

    h : std_logic_vector ( 15 downto 0 )

    and a signal h1 you will be, well, in trouble.

   or, if you have two vectors, "h" and "h1", both from 15 downto 0,

        h(15) and h1(5) will make a mess.

same thing with naming busses in viewdraw, iirc (but old, can't remember if
that's fixed or not, just avoid it both in schematics and vhdl, can remember the
pain though :-)

rk

================================================

Hans wrote:

> Renzo,
>
> Which version of ACTMAP are you using? The current version which is R3-1998.
>
> Hans.
>
> In article <367001aa.0@lps.tina.agr.st.com>, renzo.arce@st.com says...
> >
> >Hi,
> >somebody know what mean the communication error during the
> >synthesis with ActMap of Actel Designer Series.
> >
> >ERROR:(VHDL-1769) Cannot split signal 'n15'
> >
> >I am using the family Actel 3200DX for synthesis an 64-bits
> >multiplier.
> >
> >Thank you
> >
> >Renzo Arce
> >renzo.arce@st.com



Article: 13605
Subject: Tech Note Article
From: "mdisman" <mdisman@ix.netcom.com>
Date: 11 Dec 1998 16:41:19 GMT
Links: << >>  << T >>  << A >>
This week's Tech Note on the PLD Design Center is a paper from Lucent
Technologies on implementing a Fibre Channel Multimedia Adapter with a PCI
Interface.  It is lsited as Today's Feature at http://www.edtn.com/pld

Murray Disman
Editor
Pld Design Center

Article: 13606
Subject: Re: Need basic info on FPGA!
From: mushh@jps.net (David Decker)
Date: Fri, 11 Dec 1998 16:42:09 GMT
Links: << >>  << T >>  << A >>
Read everthing on:
http://www.optimagic.com/
espically the PAM-Blox URL found under the Free S/W heading.

Dave Decker

"TNT" <tim-cam@email.dk> wrote:

>Hi
>
>We are engineering sudents working on a projekt that involves basic
>knowledge on FPGA.
>Our main purpose is to implement by C++,  the intension though is to end up
>with programming a Xilinx XC 4010 XL.
>What we need at this point is an introduction to the following:
>
>    - CLB
>    - LUT
>    - Macro's
>    - The basic's of gate arrays
>
>The only documentation on the subjekt we have so far is the "The practical
>Xilinx designer lab book".
>
>Thank you for any contribution what so ever.
>
>
>
>

Dave Decker
Diablo Research Co. LLC

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House

Article: 13607
Subject: Re: HELP, Tool selection
From: z80@ds2.com (Peter)
Date: Fri, 11 Dec 1998 18:17:41 GMT
Links: << >>  << T >>  << A >>

Not what your man told me about a year or two ago.

The last software I (eventually) got was dated 1995, and this is a
windows 3.x version. This was dated about a year or two before the
date it was supplied, and I was told this is all there is. Are you
saying there is a software update for the Chiplab which is more
recent?

I know Data I/O still sell a programmer in the same shape box, but it
isn't called Chiplab. Maybe the software for *that* works with the
Chiplab?

>>The Chiplab-48 is now well obsolete (it was obsolete, in the sense of
>>there being no new device development for it, for 1-2 years while it
>>was still being sold
>< a lot more ranting snipped>
>
>For your information, the product you are denigrating - which we sell
>and support in UK - is not only not obsolete, but new device support
>development has never stopped, and is continuing today and into the
>future.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13608
Subject: Re: Lattice Pin Drive Capability
From: Gary Milliorn <rxcr80@email.sps.mot.com>
Date: Fri, 11 Dec 1998 15:35:43 -0600
Links: << >>  << T >>  << A >>
Hmmm, the 2064 IOL = 8mA, IOH = -4ma, the 2096 is probably the same.
Neither is what I'd call "plenty".  

  A typical PC SuperI/O supplies +/- 14mA on the PD(0:7) pins, though
only +/-2mA on control signals.  It might depend on your environment.
For example, how long is your printer cable?  What's on the other
end?  See if it works any better if you short out the series resistors.

John Chambers wrote:
> 
> I'm using a Lattice ispLSI2096-80 (PQFP package) to implement an EPP
> Printer Port peripheral.  I connected the pins of the CPLD straight to
> the printer cable through 30R resistors.  Does anyone have any
> experience of the current drive capacity of these parts as I seem to be
> getting unreliable data transfer and need to know whether to revise my
> state machine or prototype a new board with bus drivers.  The manual
> seems to indicate that there is plenty of current drive availavle.  Any
> help appriciated
> 
>         John
> 
> johnc@ihr.mrc.ac.uk

--                                                                      --
Gary Milliorn                     Yellowknife | PowerPMC Reference Designs    
                        
Motorola RISC Apps                   at www.mot.com/SPS/PowerPC/teksupport

Article: 13609
Subject: XESS FPGA Board?
From: gt0085b@acmex.gatech.edu (Shane Tow)
Date: 11 Dec 1998 22:31:04 GMT
Links: << >>  << T >>  << A >>
I am considering purchasing an XESS XS40 FPGA board.  I am a student that
would like to get more experience with FPGA and microcontroller design.
Has anyone had any experience with these boards and have some comments
that they would like to share.  Also, can anyone recommend another board
in the same price range that I should consider?

Thanks,

------------------------------------------------------------------------------
Shane Tow                           
Undergraduate: Computer Engineering 
Georgia Institute of Technology     
gt0085b@prism.gatech.edu            
------------------------------------------------------------------------------

Article: 13610
Subject: Re: XESS FPGA Board?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Sat, 12 Dec 1998 09:18:59 -0500
Links: << >>  << T >>  << A >>
look at www.optimagic.com for a list of boards.  I've personally used ones from
VCC and annapolis microsystems.  They are both good.

Shane Tow wrote:

> I am considering purchasing an XESS XS40 FPGA board.  I am a student that
> would like to get more experience with FPGA and microcontroller design.
> Has anyone had any experience with these boards and have some comments
> that they would like to share.  Also, can anyone recommend another board
> in the same price range that I should consider?
>
> Thanks,
>
> ------------------------------------------------------------------------------
> Shane Tow
> Undergraduate: Computer Engineering
> Georgia Institute of Technology
> gt0085b@prism.gatech.edu
> ------------------------------------------------------------------------------



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13611
Subject: 4000 series EDIF routing property
From: "Khaled Benkrid" <k.benkrid@qub.ac.uk>
Date: 12 Dec 1998 22:12:16 GMT
Links: << >>  << T >>  << A >>
Does any body knows the EDIF routing property for the 4000 series?
Where aould I get this information?


Please help!



Article: 13612
Subject: FPGA Data compression
From: "EKC" <alpha3.1@ix.netcom.com>
Date: Sat, 12 Dec 1998 20:17:26 -0500
Links: << >>  << T >>  << A >>
I am interested in implementing a data compression algorithm in an FPGA. I
would appreciate any information from people who have done work on this
topic or any pointers to literature or web sites.

Thanks in advance,
-EKC


Article: 13613
Subject: Re: FPGA Data compression
From: Sam@cady.paik.webnexus.com (Samuel Paik)
Date: 13 Dec 1998 08:07:39 GMT
Links: << >>  << T >>  << A >>
In article <74v4ik$al1@dfw-ixnews8.ix.netcom.com>, EKC <alpha3.1@ix.netcom.com> wrote:
>I am interested in implementing a data compression algorithm in an FPGA.

A major problem is that most lossless compression techniques require
significant amounts of memory.  Lossy signal compression isn't usually
as memory intensive, but can be.

Books on compression:

  _Text Compression_, Bell, Cleary, Witten, Prentice-Hall, 1990
    Lossless data compression, ad hoc, entropy coders, dictionary coders,
    and data modeling, slightly dated, moderately theoretical

  _The Data Compression Book_, Nelson, Gailly, IDG Books, 1995
    Mostly about lossless data compression, covers similar material
    as above, but in a more practical manner (as you would expect
    from IDG).

  _Vector Quantization and Signal Compression_, Grey, Gersho, Kluwer, 1992
    Scalar and vector quantization--important for lossy compression.
    I've heard that VQ is or was popular in satellite data compression

I'm not sure what to suggest for transform techniques, they
should be covered in any reasonable image processing book.
I have a specialized one on DCT that is very relevent for modern
image and video compression

  _Discrete Cosine Transform: Algorithms, Advantages, and Applications_,
    Academic Press, 1990

New additions are things like block sorting compressors (lossless),
wavelet and fractal transforms (lossless and lossy).  I don't think
block sorters are in any books, so you'll need to go see a paper,
there are several on the net.  There have been a bunch of books
on wavelet transforms and some on fractals, I don't know enough
about them to suggest any particular book.

Also, go see the comp.compression FAQ.

Compression pointers
  http://www.internz.com/compression-pointers.html

Ross's Compression Crypt
  http://www.ross.net/compression/

Compression and Physics from Charles Bloom
  http://www.its.caltech.edu/~bloom/index.html

Sam
who hasn't done much with data compression in some years
-- 
        Samuel S. Paik / paik@webnexus.com / Speak only for self
         Duct tape is a girl's best field. - Ariauna Albright

Article: 13614
Subject: Re: Magazine IEEE for FPGA ???
From: Spiros Lakkos <S.Lakkos@city.ac.uk>
Date: Sun, 13 Dec 1998 17:36:36 +0200
Links: << >>  << T >>  << A >>


renzo.arce@st.com wrote:

> Hi,
> some body know which IEEE magazine contains articles about FPGA
> design and development.
>
> Thank you !
>
> Renzo Arce

  I am not aware of any IEEE magazine regarding this subject, however a
few months ago
I had seen a copy of 'Journal of VLSI Signal Processing Systems for
Signal, Image and Video
Technology' , Kluwer Academic Publishers, Ed in Chief S Y Kung.

There were quite a few articles regarding FPGAs in this magazine.

Regards

Spiros Lakkos
City University - Centre for Information Engineering
S.Lakkos@city.ac.uk

Article: 13615
Subject: Re: Documention AHDL?
From: Vincenzo Liguori <enzo@nospam.com>
Date: Mon, 14 Dec 1998 05:03:14 +1100
Links: << >>  << T >>  << A >>
> Hi,
>
> is there a good documentation about AHDL available on the net? I need to
> understand written AHDL code. I searched with Altavista but  had no
> success (only for "AHDL - Animal Health Database Library" or so).

There's an excellent site that helps particularly with poorly
documentedAHDL's features :

http://193.215.128.3/freecore/

It also has some free cores.

> Thanks for any help,
>
> Lars

As usual, my real email is in my web page.

Enzo

-------------------------------------------------------------------------------

Vincenzo Liguori
Ocean Logic Pty Ltd
PO BOX 768
Manly NSW 2100
Australia

Ph : +61-2-99054152
Fax : +61-2-99050921
WWW : http://www.bigfoot.com/~oceanlogic





Article: 13616
Subject: Re: Magazine IEEE for FPGA ???
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Sun, 13 Dec 1998 21:21:15 -0000
Links: << >>  << T >>  << A >>
Design and test of Computers had some stuff on FPGA's a couple of issues
ago. I'm sure there's also an on-line bibliography at computer.org

Craig Slorach

renzo.arce@st.com wrote in message <366fdd79.0@lps.tina.agr.st.com>...
>Hi,
>some body know which IEEE magazine contains articles about FPGA
>design and development.
>
>Thank you !
>
>Renzo Arce


Article: 13617
Subject: Re: xilink Parallel cable III
From: Bo Bjerre <Bo@Bjerre-Technology.dk>
Date: Sun, 13 Dec 1998 23:00:24 +0100
Links: << >>  << T >>  << A >>
saffary wrote:
> 
> Somone know where i can find this cable.
> 
> Thanks.
-

--read the JTAG programmers manual that comes with the M1.5 software,
There is a schematic, telling what to do..

Article: 13618
Subject: Re: XESS FPGA Board?
From: Dave Vanden Bout <devb@xess.com>
Date: Sun, 13 Dec 1998 20:21:57 -0500
Links: << >>  << T >>  << A >>
Shane:

You might get more info on the XS40 if you post to the xsboard-users mail list.
These people can give you specific positives and negatives for this board.  Go to
www.xess.com/FPGA/list_reg.html to subscribe.

You can also get the schematic for the XS40 from our web site if you want to roll
your own.

You can check the optimagic web site for a lengthy list of boards, many of which
are expensive and geared to more experienced users.  Associated Professional
Systems (www.associatedpro.com) makes a flexible, low-cost board with a Xilinx
XC4000 FPGA that fits in a PC ISA slot.  No micro on the board, but you can
probably use the PC stand in for it.  It's worth a look.

If you still want an XS40 board after all your looking, I suggest waiting until
the end of January when our price reductions kick in.

Shane Tow wrote:

> I am considering purchasing an XESS XS40 FPGA board.  I am a student that
> would like to get more experience with FPGA and microcontroller design.
> Has anyone had any experience with these boards and have some comments
> that they would like to share.  Also, can anyone recommend another board
> in the same price range that I should consider?
>
> Thanks,
>
> ------------------------------------------------------------------------------
> Shane Tow
> Undergraduate: Computer Engineering
> Georgia Institute of Technology
> gt0085b@prism.gatech.edu
> ------------------------------------------------------------------------------



--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


Article: 13619
Subject: Atmel's PLD
From: "sam" <cong_sp@willnet.co.jp>
Date: Mon, 14 Dec 1998 13:31:05 +0900
Links: << >>  << T >>  << A >>
Does anyone have trouble when use Atmel's PLD ?
I will never use Atmel's PLD . It's too bad .

Article: 13620
Subject: CFP: Ninth International Workshop on Field Programmable Logic and Applications
From: "Patrick Lysaght" <p.lysaght@eee.strath.ac.uk>
Date: 14 Dec 1998 14:39:05 GMT
Links: << >>  << T >>  << A >>
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
_|                                                                  _|
_|                                                                  _|
_|        _|_|_|_|  _|_|_|_|  _|       _|  _|_|_|_|  _|_|_|_|       _|
_|        _|        _|    _|  _|       _|  _|    _|  _|    _|       _|
_|        _|        _|    _|  _|           _|    _|  _|    _|       _|
_|        _|_|_|    _|_|_|_|  _|           _|_|_|_|  _|_|_|_|       _|
_|        _|        _|        _|                 _|        _|       _|
_|        _|        _|        _|                 _|        _|       _|
_|        _|        _|        _|_|_|_|     _|_|_|_|  _|_|_|_|       _|
_|                                                                  _|
_|                                                                  _|
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
 
 
 
                              F P L '99
 
        N I N T H  I N T E R N A T I O N A L  W O R K S H O P 
                                 on 
                FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
 
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
_|                                                                  _|
_|       August 30 - September 1, 1999  (Monday - Wednesday)        _|
_|                                                                  _|
_|        University of Strathclyde, Glasgow, Scotland, UK          _|
_|                                                                  _|
_|                  http://FPL99.eee.strath.ac.uk                   _|
_|                                                                  _|
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
 

 
                     C A L L  F O R  P A P E R S
 
 
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
_|                                                                  _|
_|                    Paper Deadline March 12, 1999                 _|
_|                                                                  _|
_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
 
 
 
THEME: ON THE EVE OF THE THIRD MILLENIUM: A TIME FOR REVIEW AND FOR
CONSIDERING THE FUTURE OF PROGRAMMABLE LOGIC
 
FPL'99 is likely to be the last major workshop on Field Programmable Logic
before the new millenium.  It presents the participants with an opportunity
to review the work of the last decade and to look forward to what we can
expect in the coming decade.  The most obvious changes relate to device
size and speed, where device capacities exceeding one million gates and
speeds of 1GHz are technically feasible now.  The biggest challenges are
arguably in the domain of software and design tools in general.  Areas such
as intellectual property cores, system-on-chip design, and reconfigurable
systems technology, in all its forms, will undoubtedly become more
significant in the future.
 
 
CALL FOR CONTRIBUTIONS
 
Contributions are invited for regular presentation, poster and discussion
sessions.  Prospective authors are invited to submit an abstract of at
least 500 words or a full paper of about 10 pages by 12 March 1999 to the
Program Chairman. Please send also your full correspondence address,
including e-mail, and fax, and a list of (at most) 5 one-line statements
that best encapsulate the essence of your proposed contribution. 
Submissions by e-mail to: FPL99@eee.strath.ac.uk in ghostscript-compatible,
postscript format or PDF are highly encouraged.  Notification of acceptance
will be posted by 28 May 1999 and final papers must be received by 18 June
1999 to guarantee distribution at the workshop.  The workshop proceedings
will be published by Springer.  For the publication of accepted papers, an
electronic as well as a camera-ready version of the paper and the
registration of at least one author will be required.   The official
conference language will be English.
 
 
SCOPE
 
Workshop topics include, but are not restricted to:
 
* Novel device, machine and system architectures
* New software and hardware development tools
* Reconfigurable and partially reconfigurable designs 
* Dynamically reconfigurable logic and systems
* High-level design and compilation research
* Industrial applications and experiences
* Trade-offs between devices, architectures and technologies
* Reconfigurable custom computing machines
* Hardware/software co-design for field programmable logic
* Microprocessor/FPGA hybrid devices
* ASIC emulators, hardware modellers and compiled accelerators 
* Fault modelling, testability methods and reliability issues
* Educational experiences and opportunities
* Reconfigurable accelerators and their applications
* Speed-up effects - survey and analysis
* Testing of reconfigurable circuits 
* Benchmarking and profiling
* Applications from a wide variety of areas 
* Evolvable and adaptable systems 
 
GENERAL CHAIRMAN
Patrick Lysaght
Dept. of Electronic and Electrical Engineering.
University of Strathclyde, 204 George Street,
Glasgow G1 1XW, Scotland, United Kingdom
Phone:  +44 141 548 2249 Fax:    +44 141 552 4968
email:  p.lysaght@eee.strath.ac.uk 

PROGRAM CHAIRMAN
Prof. Reiner W. Hartenstein
University of Kaiserslautern
P.O. Box 3049  
D-67653 Kaiserslautern, Germany 
Phone:  +49 631 205-2606 Fax:    +49 631 205-2640
email:  hartenst@rhrk.uni-kl.de

PROGRAM COMMITTEE
Peter Athanas, Virginia Tech, USA
Samary Baranov, Ben Gurion U. Negev,Israel
Stephen Brown, U. of Toronto, Canada
Klaus Buchenrieder, Siemens AG, FRG
Steven Casselman, VCC, USA
Bernard Courtois, INPG, Grenoble, France 
Carl Ebeling, U. of Washington, USA
Norbert Fristacky, Slovak Technical U., SK Manfred Glesner, TH Darmstadt,
FRG
John Gray, Xilinx, UK
Herbert Gruenbacher, Vienna U., Austria
Reiner Hartenstein, U. of Kaiserslautern, FRG
Brad Hutchings, Brigham Young U., UAS
Udo Kebschull, U. of Tuebingen, FRG
Andres Keevallik, Tallinn Technical U., Estonia
Wayne Luk, Imperial College, UK
Patrick Lysaght, U. of  Strathclyde, Scotland
Toshiaki Miyazaki, NTT Laboratories, Japan
Will Moore, Oxford U., UK
Wolfgang Nebel, U. of Oldenburg, FRG
Paolo Prinetto, Politecnico di Torino, Italy
Jonathan Rose, U. of Toronto, Canada
Zoran Salcic, U. of Auckland, New Zealand
Eduardo B. Scalvinoni, U. Autnoma de Madrid, Spain
Hartmut Schmeck, U. of Karlsruhe, FRG
Marc Shand, Digital Systems Research Center, USA
Stephen Smith, Altera, USA
Steve Trimberger, Xilinx, USA
 
 
IMPORTANT DATES AND FURTHER INFORMATION 
 
Deadline for paper submission:			12 March 1999
Notification of acceptance of papers:		28 May 1999
Deadline for receipt of final papers:		18 June 1999

For further details, see the workshop website at
http://FPL99.eee.strath.ac.uk


Article: 13621
Subject: Re: FPGA Data compression
From: Steve Nordhauser <nords@intersci.com>
Date: Mon, 14 Dec 1998 10:01:39 -0500
Links: << >>  << T >>  << A >>
Most of the work I am doing is in image and video compression.  The SPIE
has some excellent references.  A few representative titles are:
Vol 2668 Digital Video Compression: Algorithms and Technologies 1996
Vol. 2186 Image and Video Compression
Digital Image Compression Techniques

and FPGA-Specific journals like:
Vol 2914 High-Speed Computing, Digital Signal Processing, and Filtering Using
     Reconfigurable Logic

There are many more.  You might want to try FPL also.  For video, proceedings
provide the most current information on implementations and research.
The books are good for an understanding of algorithms and concepts.

EKC wrote:

> I am interested in implementing a data compression algorithm in an FPGA. I
> would appreciate any information from people who have done work on this
> topic or any pointers to literature or web sites.
>
> Thanks in advance,
> -EKC



--
Steve Nordhauser
Embedded Systems Manager   Phone: (518) 283-7500
InterScience, Inc.         Fax:   (518) 283-7502
105 Jordan Road            email: nords@intersci.com
Troy, NY 12180             web: http://www.intersci.com

   "Any sufficiently advanced technology is
        indistinguishable from magic."
             - Arthur C. Clarke


Article: 13622
Subject: FAQ Address Please
From: "Ing. Cristiano Golin" <alq@witcom.com>
Date: Mon, 14 Dec 1998 19:29:57 +0100
Links: << >>  << T >>  << A >>
Please send me the FAQ repository address.
Regards,
	C. Golin

Article: 13623
Subject: Dedicated pin in ALTERA 10K familly
From: "Hubert Gagnon" <hgagnon@absolu.com>
Date: Mon, 14 Dec 1998 16:50:07 -0500
Links: << >>  << T >>  << A >>
What should I do with all dedicated pins in a 10k20 device? I'm talking
about nce, nceo, tdi, tdo etc. There is no documentation regarding those
pins on the data book. I use the bit blaster to program the part.

Thanks
Hubert Gagnon


Article: 13624
Subject: Parallel Port Pass Through Specs?
From: "Arnold Beland" <acbel@worldnet.att.net>
Date: 14 Dec 1998 21:51:59 GMT
Links: << >>  << T >>  << A >>
I am designing a device that will be driven  in EPP mode from the Printer
Port of an existing PC.  These PC's will usually have a printer using this
port.  I don't want my customers to have to install another parallel port. I
notice that the Zip Drives have a pass-through capability.  Could anyone
give me a clue as to how this is accomplished?  Thanks in advance.

Arnold Beland





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