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I find the issue with schematics vs VHDL is readability and control over the design. Structural HDL coding (instantiating everything) helps with the control issue, but is still awkward when creating RPMs (alot of the stuff I do uses the carry chains). For synthesized state machines, you need to be careful about recovery from illegal states, especially in decoded state machines (eg one hot types). From what I've seen, the synthesized state machines usually do not have recovery logic unless you specifically call it out. Schematic readability really depends on your style. First, the design has to be hierarchical to make it readable. Each level should be restricted to one page, and the symbol graphic should reflect the function of the underlying schematic. I've seen awful schematics and awful HDL code, and I've seen good examples of both too. The way I see it, the real advantages of HDLs are the enhanced simulation capability (especially using behavioral models) and the ability to retrieve an archived design using a simple text editor instead of the schematic editor used to create it. Weighing in favor of schematics are enhanced readability (assuming the schematics are done right) and the ease of control over the design implementation and placement. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12401
> > For my designs, your above is absolutely incorrect. Every design I do runs > > at 33+ MHz, and as such, requires a lot of mapping and placement. ALSO, > > yes, I can buy the FASTEST MOST EXPENSIVE parts and use VHDL and hope and > > pray it works...OR I can use schematics, and ASSURE my design success in a > > finite amount of time, with cheaper silicone. > > I find that 33 Mhz is very easy in VHDL with little or no optimization. > I just completed a XC4010XL-1 design with about 80% VHDL. Hum, and I run 33MHz in -3 parts.....thanks for proving my point ;-) > How large of a design have you done in schematics? How long did it take > from design start to get through simulation? I have only a little > experience to base my schedule estimates on so I would appreciate the > info. Over the years I developed a library of basic by n symbols, registers, TBUFs, counters, muxes, IOs etc. I can modify these in minutes if I don't have what I want. They are also, for the most part, architecturally independant...ie you only need to make the lowest level symbol, such as a 1 bit register, in order to use this library with any new technology. Why this is good is that I can do a very large data path design in very short time. Control logic is more 'work' (read as thought time, as opposed to entry time) and whether I do it in schematic or HDL is not really an issue, but I do prefer HDLs for control logic....when they work ;-) I've done over 50k gates in schematic. .... > Most of the time (other than > learning how to do good VHDL) was in designing, debugging and fixing my > control logic. This is an area where VHDL clearly excells over schematic > (at least in terms of development speed). I disagree here. Whether VHDL or schematic, I believe the design is about the same, and in some instances, one is better than the other....and in VHDL you can end up fussing with the compiler to make it to what you want. Simulation with schematics is as easy as with VHDL. And again, some things may be easier to fix in VHDL than in schematic and vice versa. Hey! This wasn't supposed to be VHDL v schematics! > > P.S. I don't know about you, but I find it really hard to look at a stack > > of textual pages and know at a glance what the data flow and functionality > > of a design is.... May be I need to take that speed reading course again > > ;-) > > Funny, I find a 30 page schematic hard to read. At least if I wasn't the > one to enter it. I've never met a designer yet that produced a clear > schematic for a complex design that didn't take some getting used to. In my opinion, a 30 page schematic is a badly done schematic. My current design is 4 pages, yes 4. Now, understand that each page has hierarchical symbols, with additional pages underneath...but you don't need to know what's in there to understand the design flow. If you NEED to go into one of those blocks, then you can, but the basic design is in 4 pages. AustinArticle: 12402
Rich Katz was kind enough to email me the permission to post the paper, so it is now posted on my website. The paper title is "An FPGA based processor yields a real time high fidelity radar environment simulator " Ray Andraka wrote: > If they can ship live Maine Lobsters to California, why can't you ship the > hamburgers/ice cream? ;-) Most of us would probably prefer a beer anyway. > > I've got some papers that touch on aspects of DSP in FPGAs on my website (I'll > hopefully be adding one discussing a radar simulator soon--(if it is OK with > Rich Katz)). You might also check the xilinx website (http://www. > xilinx.com). There are a number of white papers there. Look for a set of > presentation slides by Bruce Newgard. Those slides had a few examples from > xilinx customers (that had a satellite modem in it). None have the actual > FPGA bit streams or the complete set of schematics, as these belong to > customers (same is true of my papers), but it should give you an idea what is > possible. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12403
ok, here's a thrown together schematic exported to structural vhdl using expt1076 w/
viewlogic.
1. this s/w does keep the reference designators.
2. it also kept my signal names, mostly. for the output, it was left intact. but since
the output of this simple circuit also fed back into the circuit, it added an internal
signal, same name as the original, but with '_Buffer' appended to the signal name.
3. i'd rather read a schematic - and i was nice, told it to used named rather than
positional notation.
4. i'd rather draw a schematic than write top-level code like this.
5. this structural vhdl is easier to read than the edif version, also included. point =>
vhdl.
r "geezer" k
_________________________________________________________________
Use WORK.gsigdecl.all;
entity EXPORTTEST is
port(CLK: IN bit;
GOTIT: IN bit;
GOTIT_PULSE: OUT bit);
end EXPORTTEST;
architecture archEXPORTTEST of EXPORTTEST is
signal GOTIT_PULSE_Buffer: bit;
signal GOTITL: bit;
signal GOTITS1: bit;
component DF1
generic(TF: string := "DF1.TIM");
port(CLK: IN bit;
D: IN bit;
Q: OUT bit);
end component;
for all: DF1
use entity ACTELCELLS.DF1(archDF1);
component DFC1
generic(IMPL: string := "CS");
port(CLK: IN bit;
CLR: IN bit;
D: IN bit;
Q: OUT bit);
end component;
for all: DFC1
use entity ACTELCELLS.DFC1(archDFC1);
begin
GOTIT_PULSE <= GOTIT_PULSE_Buffer;
FF3: DF1
generic map(TF => OPEN)
port map(CLK => CLK,
D => GOTITS1,
Q => GOTIT_PULSE_Buffer);
FF2: DFC1
generic map(IMPL => OPEN)
port map(CLK => CLK,
CLR => GOTIT_PULSE_Buffer,
D => GOTITL,
Q => GOTITS1);
FF1: DFC1
generic map(IMPL => OPEN)
port map(CLK => GOTIT,
CLR => GOTIT_PULSE_Buffer,
D => VDD,
Q => GOTITL);
end archEXPORTTEST;
______________________________________________________
(edif EXPORTTEST
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 1998 10 11 11 54 32)
(program "VIEWlogic's edifnet" (version "5.00"))))
(library EXPORTTEST
(edifLevel 0)
(technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
(cell (rename ACTELCELLS_DF1_1 "DF1")
(cellType GENERIC)
(status (written
(timeStamp 1998 5 29 18 33 0)))
(userData VL_PLATFORM_CODE (string "K XXXXXXXXXXXX DF1")
(owner "Viewlogic_Systems"))
(userData LIBNAME
(string "ACTELCELLS")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port D
(direction INPUT))
(port Q
(direction OUTPUT))
(property LEVEL (string "HARD") (owner "Viewlogic_Systems"))
(property TF (string "DF1.TIM") (owner "Viewlogic_Systems")))
))
(cell (rename ACTELCELLS_INV_2 "INV")
(cellType GENERIC)
(status (written
(timeStamp 1998 5 29 18 33 0)))
(userData VL_PLATFORM_CODE (string "K XXXXXXXXXXXXX INV")
(owner "Viewlogic_Systems"))
(userData LIBNAME
(string "ACTELCELLS")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port A
(direction INPUT))
(port Y
(direction OUTPUT))
(property LEVEL (string "HARD") (owner "Viewlogic_Systems"))
(property TF (string "INV.TIM") (owner "Viewlogic_Systems")))
))
(cell (rename ACTELCELLS_DFC1B_3 "DFC1B")
(cellType GENERIC)
(status (written
(timeStamp 1998 5 29 18 33 0)))
(userData VL_PLATFORM_CODE (string "K XXXXXXXXXXXXXXX DFC1B")
(owner "Viewlogic_Systems"))
(userData LIBNAME
(string "ACTELCELLS")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port CLR
(direction INPUT))
(port D
(direction INPUT))
(port Q
(direction OUTPUT))
(property LEVEL (string "HARD") (owner "Viewlogic_Systems"))
(property TF (string "DFC1B.TIM") (owner "Viewlogic_Systems")))
))
(cell (rename ACTELCELLS_DFC1_4 "DFC1")
(cellType GENERIC)
(status (written
(timeStamp 1998 5 29 18 33 6)))
(userData VL_PLATFORM_CODE (string "K XXXXXXXXXXXXXX DFC1")
(owner "Viewlogic_Systems"))
(userData LIBNAME
(string "ACTELCELLS")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port CLR
(direction INPUT))
(port D
(direction INPUT))
(port Q
(direction OUTPUT))
(property IMPL (string "CS") (owner "Viewlogic_Systems"))
(property LEVEL (string "SOFT") (owner "Viewlogic_Systems")))
(contents
(instance U0
(viewRef view_1 (cellRef ACTELCELLS_INV_2))
(property LABEL (string "U0") (owner "Viewlogic_Systems")))
(instance U1
(viewRef view_1 (cellRef ACTELCELLS_DFC1B_3))
(property LABEL (string "U1") (owner "Viewlogic_Systems")))
(net CLK
(joined
(portRef CLK)
(portRef CLK (instanceRef U1))))
(net CLR
(joined
(portRef CLR)
(portRef A (instanceRef U0))))
(net D
(joined
(portRef D)
(portRef D (instanceRef U1))))
(net NET0
(joined
(portRef Y (instanceRef U0))
(portRef CLR (instanceRef U1))))
(net Q
(joined
(portRef Q)
(portRef Q (instanceRef U1))))
(userData &_1 (property DESIGN_NAME
(string "DFC1") (owner "Viewlogic_Systems")))
(userData &_2 (property SCH_FILE_DATE
(string "29 MAY 98") (owner "Viewlogic_Systems")))
(userData &_3 (property SCH_FILE_NAME
(string "DFC1") (owner "Viewlogic_Systems")))
(userData &_4 (property SCH_FILE_PATH
(string "DFC1") (owner "Viewlogic_Systems")))
(userData &_5 (property SCH_FILE_TIME
(string "10:45") (owner "Viewlogic_Systems")))
(userData &_6 (property SCH_PGM_NAME
(string "VIEWGEN") (owner "Viewlogic_Systems")))
(userData &_7 (property SCH_PGM_VER
(string "3.6.1") (owner "Viewlogic_Systems")))
(userData &_8 (property SHEET
(string "1") (owner "Viewlogic_Systems")))
(userData &_9 (property USER_NAME
(string "VIEWGEN") (owner "Viewlogic_Systems")))
(userData &_10 (property WIR_FILE_DATE
(string "1 JAN 70") (owner "Viewlogic_Systems")))
(userData &_11 (property WIR_FILE_NAME
(string "DFC1") (owner "Viewlogic_Systems")))
(userData &_12 (property WIR_FILE_PATH
(string "DFC1") (owner "Viewlogic_Systems")))
(userData &_13 (property WIR_FILE_TIME
(string "0:00") (owner "Viewlogic_Systems")))
)
))
(cell EXPORTTEST
(cellType GENERIC)
(status (written
(timeStamp 1998 10 11 10 47 40)))
(userData VL_PLATFORM_CODE (string "K XXXXXXXXXXXXX EXPORTTEST")
(owner "Viewlogic_Systems"))
(view view_1
(viewType NETLIST)
(interface
(port CLK
(direction INPUT))
(port GOTIT
(direction INPUT))
(port GOTIT_PULSE
(direction OUTPUT)))
(contents
(instance FF3
(viewRef view_1 (cellRef ACTELCELLS_DF1_1))
(property LABEL (string "FF3") (owner "Viewlogic_Systems")))
(instance FF2
(viewRef view_1 (cellRef ACTELCELLS_DFC1_4))
(property LABEL (string "FF2") (owner "Viewlogic_Systems")))
(instance FF1
(viewRef view_1 (cellRef ACTELCELLS_DFC1_4))
(property LABEL (string "FF1") (owner "Viewlogic_Systems")))
(net CLK
(joined
(portRef CLK)
(portRef CLK (instanceRef FF3))
(portRef CLK (instanceRef FF2))))
(net GOTIT
(joined
(portRef GOTIT)
(portRef CLK (instanceRef FF1))))
(net GOTITL
(joined
(portRef D (instanceRef FF2))
(portRef Q (instanceRef FF1))))
(net GOTITS1
(joined
(portRef D (instanceRef FF3))
(portRef Q (instanceRef FF2))))
(net GOTIT_PULSE
(joined
(portRef GOTIT_PULSE)
(portRef Q (instanceRef FF3))
(portRef CLR (instanceRef FF2))
(portRef CLR (instanceRef FF1))))
(net VDD
(joined
(portRef D (instanceRef FF1)))
(property GLOBAL (boolean (TRUE))
(owner "Viewlogic_Systems"))
)
)
))
)
(design ROOT
(cellRef EXPORTTEST
(libraryRef EXPORTTEST)))
)
_______________________________________________________
Article: 12404I'm looking to implement a PCI target. I've found a chip from AMCC that does it, but at a cost of uk26.00 100 off, its too expensive - costing more than fpga real estate. I've also contacted xilinx but the PCI logicCore is well over uk3000.00 and a full development system well over uk5000.00. I can currently use xilinx devices and vantis cpld's, but for the right target I'm will to look elsewhere. I have downloaded the vantis pci kit, but it is undocumented and dosen't look complete. Does anyone know of free or low cost HDL/Schematic for a PCI target? -- Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031, Gerald Coe | .demon.co.uk | 68302, 64180, 80C188EB cpu modules. http://www.devantech.demon.co.uk | Full custom uP control systems designed.Article: 12405
rk wrote: > > Rickman wrote: > > I'm not trying to pick a fight or anything, > > why not? it's getting a bit dull around here :-) Personally, I prefer a different kind of excitement, fights are not my thing. ;) > - - - - - - - - - - - - - - - - - - - - - - - - - - - > > > but this > > sounds like a > > contradiction to me. If you are accustomed to programming in text why > > would hardware be any different? SW has the same type of data flows and > > control as hardware. > > > > nope, not at all. traditional applications s/w is sequential, hardware is not. > > also, time matters more in h/w than s/w and a well-drawn schematic you can easily see > how time progresses and how delays line up in various paths graphically - tougher to > do with a text-oriented format. Good point. > also it's a lot easier to see the relationships between blocks (or instantiated > macros) by following wires and busses on a schematic than having the eye-balls do > pattern matching on signal names and then connecting them together in the head. of > course, that's where i take out the scrap paper and pencil and draw a schematic. I agree with that too. I guess the problem I have is that once a schematic is done, I never get the time to make it "pretty" and my coworkers never seem to see the advantage. Of course a lot of people just plain get used to settling for less than optimal. It's a level of quallity I call "Good Enough". > otoh, to see the operation of a sequencer, for example, it's generally easier to > follow a case statement with a enumerated type than a bank of flip-flops and a pile > of gates. of course, it's even easier to see the operation when using a graphical > tool such as statecad - see rationale above. > > ___________________________________________________________________________ > > > I really like being able to look at code to get a feel for a design. Of > > course a GOOD top level schematic is worth its weight in gold, but many > > times it is not easy to do a clean, clear top level schematic for a > > complex design. > > it does take time to make a 'GOOD' schematic/roadmap - but worth it. > > and it's been, well, more than once, i had to make a schematic out of synthesized > code to see what the machine decided to do. gotta keep schematics. I have to do that for my fast state machines. The synthesizer ouput can be read in the simulator one logic gate at a time. Not easy to "see" without drawing it. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12406
rk wrote: > watch windows are nice - got 'em in DOS a number of years ago. seems to me it is much > easier just to look at a schematic and see all of the values and how all of the signals > interrelate. the more modern s/w tools i'm using now still have watch windows. but neat > feature, if you put the mouse over the signal name it'll put the value in a bubble - they > realized that watch windows were a pain. > > most importantly, if the vendor doesn't support schematics, there are no symbols - we've > hit that problem before. then you gotta make them yourself. Which software are you using. I like Foundation pretty well, but it has no VHDL simulator so I can't run testbenches, which I consider to be the main advantage of VHDL. I would like to consider other tools as well. The mouse bubble state sounds pretty nice. > > Again the one I used preserved the names from the schematic. It was the > > synthesized VHDL where they tossed out signal names, but that was only > > in a simulation of compiled VHDL. You could simulate the VHDL source and > > not miss a thing. > > did it preserve the reference designators also? most important for plunking the macros > down where you want them or to tell them to stay put once you got them in a good spot. Don't know. I didn't do any placement of components, so I didn't get into the Xilinx side of things too much. That is where the RDs would have shown up or not. > i sort of like being able to talk to the simulator interactively, 'h' and 'l' and 'assign' > and then, for output, look at the schematic or do a print. good way to get the design up > and running and find all the things that are fine for a good design but bad for the > simulator [like the classic divide by two f-f w/out reset]. How do you handle having to go back to tweek your design after a couple of weeks have gone by without any bugs. I find that I have forgotten most of the manual touches that I need to get a simulation to run or just plain how to use the darn macro files I wrote. But a testbench can be built to completely test a design and report Pass/Fail and which test failed. So when I make a tweek, I can resimulate in a matter of minutes without having to remember all the test points that need to be examined. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12407
rk wrote: > > ok, here's a thrown together schematic exported to structural vhdl using expt1076 w/ > viewlogic. > > 1. this s/w does keep the reference designators. > > 2. it also kept my signal names, mostly. for the output, it was left intact. but since > the output of this simple circuit also fed back into the circuit, it added an internal > signal, same name as the original, but with '_Buffer' appended to the signal name. > > 3. i'd rather read a schematic - and i was nice, told it to used named rather than > positional notation. > > 4. i'd rather draw a schematic than write top-level code like this. > > 5. this structural vhdl is easier to read than the edif version, also included. point => > vhdl. > > r "geezer" k I think this thread has both gotten off the original point and has beaten it to death. My suggestion was that if you had a top level schematic (which is what I normally do), you can have that translated into VHDL so that a VHDL simulator can simulate the entire design in a case where only VHDL was supported. I doubt that many people will want to use structural VHDL to enter a design. I'd rather shoot myself in the mouse hand and draw disablity. ;) But it is interesting to see that the structural VHDL is more concise than EDIF. But I don't write EDIF either... -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12408
Rickman wrote: > rk wrote: > > watch windows are nice - got 'em in DOS a number of years ago. seems to me it is much > > easier just to look at a schematic and see all of the values and how all of the signals > > interrelate. the more modern s/w tools i'm using now still have watch windows. but neat > > feature, if you put the mouse over the signal name it'll put the value in a bubble - they > > realized that watch windows were a pain. > > > > most importantly, if the vendor doesn't support schematics, there are no symbols - we've > > hit that problem before. then you gotta make them yourself. > > Which software are you using. I like Foundation pretty well, but it has > no VHDL simulator so I can't run testbenches, which I consider to be the > main advantage of VHDL. I would like to consider other tools as well. > The mouse bubble state sounds pretty nice. the mouse bubble thing comes with my pascal compiler, delphi 3.____________________________________________________________ > > > Again the one I used preserved the names from the schematic. It was the > > > synthesized VHDL where they tossed out signal names, but that was only > > > in a simulation of compiled VHDL. You could simulate the VHDL source and > > > not miss a thing. > > > > did it preserve the reference designators also? most important for plunking the macros > > down where you want them or to tell them to stay put once you got them in a good spot. > > Don't know. I didn't do any placement of components, so I didn't get > into the Xilinx side of things too much. That is where the RDs would > have shown up or not. my simple little pulse generator example showed that viewlogic did preserve the names, made them the labels for the instantiations. hey, i said something nice about viewlogic? do i get happy mail from them now? i think you'll find a hostile crowd here if the ref designators aren't kept and passed through for floor planning and placement, talking to static timing analyzers, verification of flip-flop macro types, etc., etc. ______________________________________________________________ > > i sort of like being able to talk to the simulator interactively, 'h' and 'l' and 'assign' > > and then, for output, look at the schematic or do a print. good way to get the design up > > and running and find all the things that are fine for a good design but bad for the > > simulator [like the classic divide by two f-f w/out reset]. > > How do you handle having to go back to tweek your design after a couple > of weeks have gone by without any bugs. I find that I have forgotten > most of the manual touches that I need to get a simulation to run or > just plain how to use the darn macro files I wrote. But a testbench can > be built to completely test a design and report Pass/Fail and which test > failed. So when I make a tweek, I can resimulate in a matter of minutes > without having to remember all the test points that need to be examined. ah, easy, i pass it over to my lab partner to finish :-) seriously, i use the interactive mode to get it up and on the air - after that, i collect them up and stick them in a batch or .cmd file (in viewlogic-ese). then you can re-run. as far as automagic pass/fail, you can insert 'check' statements [or whatever your simulator has] to verify logic values and it will tell you if you have an error. if you use a tool like state-cad, you can move through your logical machine with the mouse, it'll generate the stimulus to get to that state, and it will automagically generate the check statements also. of course, we've been using test benches for 15 years, just didn't know to call them that, for more complex tests. mostly i do 'em with schematics in a big block, puts out stimulus, checks inputs. in viewlogic simulator, you can read and write to files. lots of power there. or you can compile vhdl into the gate simulator. no, not as powerful as a vhdl simulator where you can use the full vhdl language. point => vhdl. ________________________________________ rkArticle: 12409
Gerald Coe wrote: > > I'm looking to implement a PCI target. I've found a chip from AMCC that > does it, but at a cost of uk26.00 100 off, its too expensive - costing > more than fpga real estate. > > I've also contacted xilinx but the PCI logicCore is well over uk3000.00 > and a full development system well over uk5000.00. > > I can currently use xilinx devices and vantis cpld's, but for the right > target I'm will to look elsewhere. I have downloaded the vantis pci kit, > but it is undocumented and dosen't look complete. > > Does anyone know of free or low cost HDL/Schematic for a PCI target? The cost of development tools is always a problem for a low end user. Sometimes you can get your FAE to lend/give you the tools. Usually this is when you are a potentially big customer. If you can get the tools, Lucent has a chip that already has a PCI interface in it. So you don't have to pay for the IP of a core. It only comes in a 55K gate size so it may still be expensive. But you can check it out at <http://www.lucent.com/micro/fpga/series3plus.html> -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12410
Rickman wrote:
> rk wrote:
>
< snip >
> I think this thread has both gotten off the original point and has
> beaten it to death.
it's been dead for days. we're just kicking the corpse.
___________________________________________
> My suggestion was that if you had a top level schematic (which is what I
> normally do), you can have that translated into VHDL so that a VHDL
> simulator can simulate the entire design in a case where only VHDL was
> supported.
fine if info isn't lost. compile into vhdl, compile into edif, compile into proprietary
viewlogic format, who cares? but the inter-tool communication, linking schematic <==>
simulator is nice. and i don't particularly want to look at structural vhdl. see my previous
example.
of course, with the growing amount of vhdl, we want breakpoints, value bubbles, and the rest of
the typical s/w stuff.
___________________________________________
> I doubt that many people will want to use structural VHDL to enter a
> design. I'd rather shoot myself in the mouse hand and draw disablity. ;)
er, i've seen a lot of ppl do it (structural stuff, not shoot themselves). 'group leader' at
my anonymous day job hates schematics, TEXT ONLY!!!! i bought 'vhdl' IP core, had a ton of
structural vhdl in it. also had bugs in it. no fun. chucked it all, designed it up by hand
w/ trusty lab partner (~35,000 gates worth of stuff - easier to do by hand than with the vhdl
IP).__________________________________________
> But it is interesting to see that the structural VHDL is more concise
> than EDIF. But I don't write EDIF either...
going through the edif to chase bugs is a nightmare and i've been procrastinating buying the
edif specification. after waiting for that stuff for 10 years, it's a mess. works well
though. as long as the info gets passed and there's a lot of tools who can reliably and
portably read and write, doesn't seem to matter which one ...
... as long as ...
... we can keep smart tools from putting their fingertprints on a design when we want them to
DONT-TOUCH ... sometimes they just don't wanna listen.
___________________________________________
rk
Article: 12411Careers in Engineering and related jobs A few miles from North San Francisco, in a beautiful vine county, a large TELECOM company (making cable modems, routers, special modems, PC boards, providing related services) is looking for Engineers, with telecommunications, telephony, LAN-WAN knowledge. (we provide US work visa if needed) All Engineering positions require a BSEE, BSCS along with 2 to 5 years of experience in a telecommunications/data communications environment. A MSCS/MSEE degree is preferred. Several c opportunities are available: Product Marketing Managers Program Managers Telecommunications Systems Engineers Test Development Engineers Electrical Test Technicians Electronic Assembly Manufacturing Engineers Production Planners Purchasing/Materials Management Vendor Quality Engineers Regional Sales Managers Every telecom experts is welcome, here are some specs: Hardware Engineers: IC designers, ASIC/FPGA knowledge toward board level, Firmware, embedded and PCB designers, Software TEST Engineers Experience working through a complete software lifecycle •Develop and test Telcom SW product/ Systems Engineers Technical Support Engineer Technician Laslo Chaki http://www.acdcon.com/ Advanced Control Data, Inc. (949) 360-4155Article: 12412
Try doing a functional simulation....I believe the underlying simulation libraries are not there.... And, yes, I was referring to Viewlogic support mostly anyway... Austin Nick Hartl <"nhartl[no_spam]"@earthlink.net> wrote in article <361F9457.4093397C@earthlink.net>... > Well now I do see Virtex library symbols in the Foundation Schematic Editor and > have placed a Virtex chip using Foundation schematics only (No HDL). So where > is this no schematic support? > > I did here that at this time there is some question if ViewLogic will support > Virtex in schematics. I am not sure if this is a decision made by Veiw or by > Xilinx. > > Have FUN!!! > Nick > > > It appears that Xilinx may not be supporting Viewlogic Viewdraw schematic > > entry for Virtex (or any other schematic entry tool for that matter). > > SOMEhow, SOMEone, interviewed SOME people, and these people were apparently > > taken by the Xilinx decision making tree as the 'golden' cross section of > > 'important' users. These SOME people said they did not want schematics, > > that HDLs would do fine. > > > > Now, nothing against HDLs, as I do use them, and they are fine...BUT there > > are some things just done better in schematics. Let's not get into that > > subject, as we all have bantered this issue of schematics v HDLs about, but > > for Xilinx to dictate what my design methodology is to be is not OK. > > Personally, I think this, what I would call, a quite 'uneducated' decision, > > is a very bad decision.... > > > > ANYone else know ANYthing more about this? > > > > Austin Franklin > > darkroom@ix.netcom.com > > > >Article: 12413
--------------A8333A18FB3B7661780DC617 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I have following books for sale: Learning Perl (The Camel book) -O'reilly & Assoc. Mastering Regular Expressions (The Owl book) -O'reilly & Assoc. PCMCIA System Architecture -Mindshare PC Systems Architecture series. CardBus System Architecture -Mindshare PC Systems Architecture series. All the 4 books are in excellent condition and latest editions (I am selling because I have never used them.) They are all average 30.00 $ per piece but I 'll sell them at 24.00$ each. If interested, please call or write. Thanks, Hitesh -- Hitesh N. Brahmbhatt Hitesh N. Brahmbhatt PHILIPS 100 N. Whisman Rd. #87 440 Wolfe Road, M/S 78 Mountain View, CA 94043 Sunnyvale, CA 94088 (650)-938-5561 (408)-991-2924 hitesh.brahmbhatt@sv.sc.philips.com --------------A8333A18FB3B7661780DC617 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <P>I have following books for sale: <P>Learning Perl (The Camel book) -O'reilly & Assoc. <BR>Mastering Regular Expressions (The Owl book) -O'reilly & Assoc. <BR>PCMCIA System Architecture -Mindshare PC Systems Architecture series. <BR>CardBus System Architecture -Mindshare PC Systems Architecture series. <P>All the 4 books are in excellent condition and latest editions (I am selling because <BR>I have never used them.) <P>They are all average 30.00 $ per piece but I 'll sell them at 24.00$ each. <P>If interested, please call or write. <P>Thanks, <P>Hitesh <PRE>-- Hitesh N. Brahmbhatt Hitesh N. Brahmbhatt PHILIPS 100 N. Whisman Rd. #87 440 Wolfe Road, M/S 78 Mountain View, CA 94043 Sunnyvale, CA 94088 (650)-938-5561 (408)-991-2924 hitesh.brahmbhatt@sv.sc.philips.com</PRE> </HTML> --------------A8333A18FB3B7661780DC617--Article: 12414
rk wrote: > > How do you handle having to go back to tweek your design after a couple > > of weeks have gone by without any bugs. I find that I have forgotten > > most of the manual touches that I need to get a simulation to run or > > just plain how to use the darn macro files I wrote. But a testbench can > > be built to completely test a design and report Pass/Fail and which test > > failed. So when I make a tweek, I can resimulate in a matter of minutes > > without having to remember all the test points that need to be examined. > > ah, easy, i pass it over to my lab partner to finish :-) > > seriously, i use the interactive mode to get it up and on the air - after that, i collect them up > and stick them in a batch or .cmd file (in viewlogic-ese). then you can re-run. > > as far as automagic pass/fail, you can insert 'check' statements [or whatever your simulator has] > to verify logic values and it will tell you if you have an error. if you use a tool like > state-cad, you can move through your logical machine with the mouse, it'll generate the stimulus > to get to that state, and it will automagically generate the check statements also. > > of course, we've been using test benches for 15 years, just didn't know to call them that, for > more complex tests. mostly i do 'em with schematics in a big block, puts out stimulus, checks > inputs. in viewlogic simulator, you can read and write to files. lots of power there. or you > can compile vhdl into the gate simulator. no, not as powerful as a vhdl simulator where you can > use the full vhdl language. point => vhdl. I see. I have found that VHDL is a lot more flexible. For example, I can describe in a process how my bus controller works in the PCI interface chip. Then if I change some timing in my design, the simulation stimulus and checks still work without tweeking the batch file. When I abandoned Orcad for my last design I had to drop testbenches. I really did not like using the simulator language. I found the VHDL stimulus to be every bit as easy and simple or as powerful as you would like. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12415
rk wrote:
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> Rickman wrote:
>
> > rk wrote:
> >
>
> < snip >
>
> > I think this thread has both gotten off the original point and has
> > beaten it to death.
>
> it's been dead for days. we're just kicking the corpse.
>
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Rick Collins
redsp@XYusa.net
remove the XY to email me.
Article: 12416Ed McCauley wrote: > > It'l work fine Justen, just pipeline your comparators. > > justen wrote: > > > > Hello, > > > > I need for my new project (PWM Generator) a 100MHz 16-Bit Counter with > > 3 Comparators. Because, I have no experience with such a high frequency, > > I would like to know if this PWM-Generator works inside a XILINX > > XC4010XL FPGA or a 95108 CPLD? I can't find an answer for this question > > in my current databook. > > > > Thanks > > Detlef Justen Counters to 100MHz should be no problem, in current technologies. Comparitors, pipelined, may have a problem with single clock width values - if you do not need to go hard to the limits, but just need 10nS mid-scale resolution, then pipelined could work. There is also more than one way to do PWM :: - create a U/D/PL counter - Preload with PWM on Count -> 0 & Toggle Dirn - Up is PWM On, Down is PWM off, The ratio of U/D changes with PWM, the total period does not. This is 4 terms wide (with a T FF) & width independant, which is better than the 2 terms / bit needed for Comparitor trees. This fits better into CPLDs, and parts from Atmel,Altera,Xilinx etc should handle this - 3 x 16 bit counters, 3 x 16 bit value latches, possibly a 8 bit load-queue buffers, if you have a 8 bit BUS, This is fits in a 128 macrocell part. - jgArticle: 12417
David Decker wrote: snip... > I simply placed three 4000e unified cc16cled counters into adjacent > columns, using RLOCs. Each counter had the 'UP' line tied low. > > These counters are RLOCed, by Xilinx, into two columns of 9 CLBs each, > but the 'UP' line grounded should have resulted in the 'UP' column > being stripped. If the 'UP' logic were properly stripped, the counters > should have been able to be placed into adjacent columns. > > When I copied the schematic of the counter and manually stripped the > 'UP' stuff, of course, the three resulting down only counters placed > into adjacent columns OK. My working hypothesis is that the M1 > stripper does not strip 4000 series carry chains properly. I wonder if > 5200s have the same symptom. Hi, this is my first posting so excuse me for any etiquette I may break, My experience with m1.4 was similar. Had many 16-bit fast-carry counters in a 4062XL (carry logic is uni-directional vs 4kex) device which the TC was not used. The RLOC origin was with the TC logic (Xilinx provided schematic). The TC logic was trimmed correctly, but the counter placement was not adjusted to compensate. So, an empty CLB was left where the TC logic would have been and Q15 one CLB below. To exacerbate the situation, if a RPM was placed above the previously mentioned counter, and the trim of the TC logic was considered in the placement of the new RPM, then the tool would report an error. It thought the two RPMs were overlapping even though the offending logic would have been trimmed. I got around the problem, by doing the "customizing the RPM" boogie also. The design was 50MHz and 99% utilized. I used every feature in the part. No way I could have done that with anything but schematics. Side question, anyone ever try to use F and G driving FFs for say a RAM with capture latch and then use the H as a combo latch (or some other three input)? The tool would not allow me to put the combo latch in the same CLB although the resources were there. I ended up using a hard macro to solve the problem? Anyone else have a different solution?? Again I was using M1.4 and using the Step 6 floor planner in a piece wise fashion (long story) to get the placement constraint file. I don't use Xilinx right now, but Xilinx said they would have a floor planner in 1.5. Did they? I was promised one since 1.3. trivia - did you know that 1.4 had a 64K constraint file size limit for the PC version? I discovered it during this design. Took Xilinx forever to admit it, but I think they have since fixed the issue. I didn't enjoy having a cst file that size, but to make it fit.... thanks for tolerating my rambling Stephen Swearingen Sr. Hardware Engineer ICS Triplex 16400-A Park Row Houston, TX 281-647-4348 sasweari@orbitworld.netArticle: 12418
Rickman wrote: > > Isn't is possible to turn your schematic output into VHDL? I know that > is how it is done in Orcad and that is what happens when you use > Foundation with Active VHDL. > I'm currently using Protel schematic to generate XNF netlists which I import into Orcad Express to simulate. Express is able to convert XNF netlists to VHDL because Orcad Express has a VHDL model for all the standard Xilinx schematic building blocks like FD8, CB4CE etc etc. If it weren't for these schematic building blocks, the conversion to VHDL would not be possible. Xilinx MUST keep supporting schematics. Schematics entry can produce optimal mappings between what the designer wants and the hardware. On the other hand VHDL makes some things which are difficult to enter and maintain in schematic easy, like state machines. Cheers, Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 12419
Rickman wrote: > > I'm not trying to pick a fight or anything, but this sounds like a > contradiction to me. If you are accustomed to programming in text why > would hardware be any different? SW has the same type of data flows and > control as hardware. Software and hardware ARE different. Hardware is implicity parallel while 99% of ALL software runs by a processor executing each instruction in a serial fashion. In addition, the structure of VHDL code does not explicity show the structure of the hardware as does the structure of say the C programming language. Cheer, Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 12420
Rickman wrote: > > I find that 33 Mhz is very easy in VHDL with little or no optimization. > I just completed a XC4010XL-1 design with about 80% VHDL. I had to check > the VHDL to make sure it was giving me a clean design. But then this was > my learning exercise and I had to get a feel for what form of VHDL > worked with this particular tool. But I did not have to place a single > object other than pins. And this design ran at 33 up to 50 Mhz. I'm not trying to say that mine's bigger than yours, but 50MHz in an XC4010XL-1 should be trivial however you do it. I recently completed a design in an XC4010XL-3 (slower speed grade) with 25% of the chip running at 100MHz implementing a number of very wide parallel to serial converters. This was done by generating a new library component as a schematic and instantiating it numerous times. The design also ended up using over 90% of all CLBs. This would plain and simply NOT have been possible in VHDL. Erik -- ------------------------------- Erik de Castro Lopo Fairlight ESP Pty Ltd e.de.castro AT fairlightesp.com.auArticle: 12421
In article <6vjffo$nir$1@news.inter.net.il>, "Ido Kleinman" <kleinn@mail.biu.ac.il> wrote: >Dear all, > >I am looking for a good VHDL development (compiling, simulation, gate-level >sim/FSM support, Testbench generator) software tool. I need it to have a >comfortable interface to maxplus2 for exporting compiled designs for >synthesis in Altera's devices. >I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and >quite happy with it, but I have a slow internet connection, therefore, >before I start downloading tens of megabytes again, I would like to know if >there are any other compact software tools worth looking at...? > >Anyone got any experience with Aldec's tool? >Are the big ones (Synopsys, Examplar..) worth the investment? There's a free toolset called alliance from P & M Curie U in Paris. Sorry, I don't have the URL to hand.Article: 12422
You probably need to look to Rochester Electronics. They are a commercial house that specializes in taking obsolete masks and inventory from silicon manufacturers and extending the products life. Altera, Intel and quite a few others authorize them as such. Need help finding them (or OTHER companies)? Check out http://start.at/semipage Good luck! Rick Filipkiewicz wrote: > Kevin Horton wrote: > > > Is it possible to get the NFX780-series of chips any more? I've looked around > > and cannot seem to find these for sale anywhere any more. I would really like > > to get my hands on several more of this chips (say, 2-10 or more depending on > > price) for my own projects. If I cannot get these any more, is there another > > similar part I can use? I already have the "dev system" for these parts > > (read: PLDshell and a parallel port :-) and this chip is perfect for my needs > > and budget. > > I assume you're talking about the parts I know as the Altera EPX780 that was > originally the Intel FX780. The bad news is that Altera stopped making them and > they are so difficult to find that we've had to re-spin a board around the Xilinx > 95xx series. Even if you do find some be careful as the last trawl we did found > a batch of chips that didn't work!!Article: 12423
You probably need to look to Rochester Electronics. They are a commercial house that specializes in taking obsolete masks and inventory from silicon manufacturers and extending the products life. Altera, Intel and quite a few others authorize them as such. Need help finding them (or OTHER companies)? Check out http://start.at/semipage Good luck! Rick Filipkiewicz wrote: > Kevin Horton wrote: > > > Is it possible to get the NFX780-series of chips any more? I've looked around > > and cannot seem to find these for sale anywhere any more. I would really like > > to get my hands on several more of this chips (say, 2-10 or more depending on > > price) for my own projects. If I cannot get these any more, is there another > > similar part I can use? I already have the "dev system" for these parts > > (read: PLDshell and a parallel port :-) and this chip is perfect for my needs > > and budget. > > I assume you're talking about the parts I know as the Altera EPX780 that was > originally the Intel FX780. The bad news is that Altera stopped making them and > they are so difficult to find that we've had to re-spin a board around the Xilinx > 95xx series. Even if you do find some be careful as the last trawl we did found > a batch of chips that didn't work!!Article: 12424
Joe Gallegos wrote: > > I'm looking for high speed (up to 80 MHz input) clock divider chips with > > > > programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and > > CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven > > by a external clock source. Does anybody know whether there are chips > > commercially available? > > > > Thomas Also ICS and Cirrus Logic. ICS probably has the most interesting range of chips. However they also have very high MOQs. And Cypress has the Roboclock range of chips which go to 125MHz. Garry Allen
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