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dalai lamah <antonio12358@hotmail.com> wrote: >Un bel giorno austin digiṭ: >> I strongly recommend that folks try our forums at: >You should give the possibility to access the forums also with NNTP and a >news client. Web forums are disappointing. I agree that webforums suck. And NNTP clients make discussion forums much easier to handle.Article: 134601
On Aug 20, 7:50 am, KJ <kkjenni...@sbcglobal.net> wrote: > On Aug 20, 2:45 am, rickman <gnu...@gmail.com> wrote: > > > On Aug 19, 10:22 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > > Does this work for the Xilinx and Altera versions of the Synplify > > tool? > > > Rick- Hide quoted text - > > Quartus didn't like it when targetting a Cyclone II device, it got > implemented with logic cells. When it sees the second path in the > code for writing to memory (i.e. enable2 and write2) it can't map it > into the internal memory of the device. I tried it with the full ispLever tool and this generates so much logic that it won't fit in the chip. I guess the fact that Synplify makes a ram component doesn't mean it gets mapped to an EBR. When I make it a single port interface it does use an EBR. My local FAE suggested an attribute to map it to a block ram, but that didn't work either. RickArticle: 134602
Gabor wrote: > O.K. Big announcement, lots of marketing buzz, etc. > > Now without looking it up at the Xilinx website, i.e. using > only the press release, what end of the line was extended? > > Was anything actually added or is this just a marketing > gimmick? Are there new parts or did they just put > three series (3A, 3AN, 3A DSP) into one datasheet? > > And where is Spartan 4? > > Eagerly awaiting much needed clarification, > > Gabor > > :) New device/package combinations are available. XC3S50A-VQ100 XC3S200A-VQ100 XC3S700A-FT256 XC3S1400A-FT256 Ed McGettigan -- Xilinx Inc.Article: 134603
On Aug 20, 4:47 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Gabor wrote: > > O.K. Big announcement, lots of marketing buzz, etc. > > > Now without looking it up at the Xilinx website, i.e. using > > only the press release, what end of the line was extended? > > > Was anything actually added or is this just a marketing > > gimmick? Are there new parts or did they just put > > three series (3A, 3AN, 3A DSP) into one datasheet? > > > And where is Spartan 4? > > > Eagerly awaiting much needed clarification, > > > Gabor > > > :) > > New device/package combinations are available. > > XC3S50A-VQ100 > XC3S200A-VQ100 > XC3S700A-FT256 > XC3S1400A-FT256 > > Ed McGettigan > -- > Xilinx Inc. I must have missed the big announcement. What was it? I have a strong interest in parts in a 100 pin QFP package and the two listed above are in the 3A data sheet from this past April. I assume "New" means in the last six months or so, or am I missing something? RickArticle: 134604
On Aug 20, 4:47 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Gabor wrote: > > O.K. Big announcement, lots of marketing buzz, etc. > > > Now without looking it up at the Xilinx website, i.e. using > > only the press release, what end of the line was extended? > > > Was anything actually added or is this just a marketing > > gimmick? Are there new parts or did they just put > > three series (3A, 3AN, 3A DSP) into one datasheet? > > > And where is Spartan 4? > > > Eagerly awaiting much needed clarification, > > > Gabor > > > :) > > New device/package combinations are available. > > XC3S50A-VQ100 > XC3S200A-VQ100 > XC3S700A-FT256 > XC3S1400A-FT256 > > Ed McGettigan > -- > Xilinx Inc. Oh yeah, I still don't see any of these parts in the VA100 package at Digikey. Are they in full production? RickArticle: 134605
On Aug 20, 12:36=A0pm, cs_post...@hotmail.com wrote: > On Aug 20, 11:53 am, cep...@nc.rr.com wrote: > > > I'm looking for an efficient multichannel narrowband digital down > > converter core for my virtex-4 design. I need a rate change of about > > 256 to 28000. Seems the rf engines IP is overkill and the XIlinx stock > > IP is not efficient (no serialized comb in CIC, for example). I need > > independent tuning and bandwidth. > > Have =A0you considered =A0writing your own? > > It is not all that complicated, and you get the opportunity to tune it > to your exact needs and resource budget. > > I wonder if a serializing the parts of the CIC that =A0run at the > decimated rate is worth the trouble. =A0It doesn't seem like it would be > very hard to do though - use something akin to an M512 (sorry, wrong > vendor language) and do the math one bit at a time - or if you don't > have enough clocks in between output rate samples, 2 or 4 bits at a > time. I actually have my own DDC design but it's overkill too. We probably will have to do our own multichannel too, its just cumbersome because some coregen pieces are available multichannel(fir) and others aren't (cic). I was hoping to avoid reinventing the wheel. BTW, a serialized comb cuts the device utilization in half if you use the SRL16s correctly. I've done it and it works so long as you integrator section bitwidth is less than the minimum decimation factor. In my case they where 84 and 112 respectively so it worked out nicely. Thanks, ClarkArticle: 134606
I'm wondering if anyone has found a workaround to install Xilinx EDK 10.1 on Vista x64. 64-bit Vista is not "officially" supported. However, the 32-bit version of Vista is. The majority of the applications I use support Vista x64. I'm running some implementations for a LX330T part, which could really benefit from the extra memory. I really don't want to dual-boot XP and Vista x64. Has anyone found a workaround to at least get the installer to run? I can deal with EDK crashes (it crashes anyway, in XP). My fingers have instinctively learned "Ctrl-S" by now. Thank you for your help.Article: 134607
Can someone please recommend some VHDL DDR2 SDRAM models? Specifically, I'm targetting a MT47H64M16 part. I've tried using an open source model from the "Free Model Foundry," but it's buggy and doesn't support seamless writes. Micron doesn't seem to be publishing free VHDL models anymore (only Verilog). We run a VHDL shop and don't even have Verilog/Mixed licenses for our simulator. Does anyone have any suggestions? I've started looking into Denali. The functionality is impressive, but seems a bit "overkill" for this application. I just need to simulate the lower 16MB of the part, and don't need any fancy debugging ports. I just want to be able to read back the data I store. I'm at the point where I'm thinking about just replacing the controller with my own behavioral VHPI. I'm using the Xilinx MIG, so I'm perfectly content trusting it to exercise the pins properly, provided that I use the application interface properly. Thanks, in advance for any advice you can provide.Article: 134608
On Aug 20, 7:03 pm, Clark Pope <cep...@nc.rr.com> wrote: I'm not sure I see the problem with mixing coregen FIR's with custom CIC's, other than the whole thing not being turnkey. > BTW, a serialized comb cuts the device utilization in half if you use > the SRL16s correctly. Yes, but I tend to run out of multipliers due to the FIR's before I run out of logic fabric for the CIC's, even with some very high ratios and fifth order (=large bit growth). >I've done it and it works so long as you > integrator section bitwidth is less than the minimum decimation > factor. In my case they where 84 and 112 respectively so it worked out > nicely. Yes, that's the simplex constraint, though if I was going to go to the trouble I'd try to do all the slow egister stages with one serialized block just for fun. I think I might have to split it or do the math 2 bits at a time. It might also be possble to overclock this bit relative to the input sample rate?Article: 134609
Hello,
I want to integrate an image processing algorithm (half tone pixel
converter, etc.) in Xilinx Spartan-3 FPGA (for a demo project only),
and the concern bugging me is how to get a simple image input.
* Which camera should I use
* Will it be directly controlled by the FPGA and if yes then how, if
no then how will it be controlled
* How will it physically interface with the FPGA
* What will be the image format and how will it be read by the FPGA
* Will an image sensor be easier to interface and use or digital
camera
* Will a video camera take a snapshot image which can be processed
* Will any pre-processing or analog-to-digital conversion of the
image / captured snapshot be required
* Is there a Xilinx prototype board for image capturing only
If anyone has designed / worked on cameras / images with FPGA .... do
let me know ... it will help me quick start the things here !!!
Anxiously waiting.
Regards,
Ghazal Javed
Article: 134610
The first read operation to the AD7874 after conversion always
accesses data from Data Register 1 (i.e., the conversion result
from the VIN1 input). INT is reset high on the falling edge of RD
during this first read operation. The second read always accesses data
from Data Register 2 and so on. The address pointer is reset to point
to Data Register 1 on the rising edge of
CONVST. A read operation to the AD7874 should not be attempted during
conversion. The timing diagram for the AD7874 conversion sequence is
CONVST--> ---------
---------//------------------------------------------------------------//---
--------------------
\ / <-----
>t5
\ /
\---------/ |
|
\--------/
INT--> --------------------------------------//----\ |
|/--------------------------------------------//-----------------
\----|---/|
| |
CS--> ---------------------------------------//--------\ |
| /-----\ /------
\ /------//----------------
\-|------/ \-------/ \-----------/
|
RD-->---------------------------------------//----------
\| /--------\ /--------
\ /-------//-----------------
|\-----/ \-----/ \---------/
|
DATA--> -----------------------------------//-----------|- \ / -------
\/-----------
/
\ /\
-----------------------------------//------------/
\------/ \---------
So my Question here is: i Wrote a VHDL code as well as Test bench for
this, but i am getting timing violations, on INT and RD signals (Both
are in Inline intead of getting a time gap 60 ns between them). Can
any body give the logic for this
Article: 134611Hi all! Just as could be expected, it was a simple error on my account. I was using a too old version of Impact. It seems ISE 9.1.03i has support for S-3AN in the synthesis and P&R flow, but Impact failed to fully recognice the device I used. After upgrading to 9.2.04i it all worked. It took me a full eavning of work though, to download and install ISE 9.2 (1.6GB) and then the web update to .04i failed until I de-selected the Virtex5 device additions (that I didn'n need). With ISE and IP updates it still was close to 1GB. I did set the VS pins correctly (111) before the configuration worked, but I am not 100% sure that that was needed. I had some concerns about the power sequensing as it is stated in the Configuration Guide: Due to requirements of the integrated SPI serial Flash memory, the 3.3V VCCAUX supply must reach its minimum supply rail before the FPGA=92s 1.2V VCCINT supply reaches its minimum power-on reset voltage level. I do not think my design complies with this as VCCINT is derived from VCCIO with a simple LDO regulator and VCCAUX is simply a LC-filtered version of VCCIO, but so far I have seen no missed start-up sequences. I will keep my fingers crossed on this one as a proper power sequencing will reqiure a "power good" signal from VCCAUX to enable the LDO for VCCINT and the components I have choosen does not have that capability... /Lars P.S. Remove the obvious from my email address if you want to answer directly. D.SArticle: 134612
On 21 aug, 00:17, rickman <gnu...@gmail.com> wrote: > On Aug 20, 4:47 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > Gabor wrote: > > > O.K. =A0Big announcement, lots of marketing buzz, etc. > > > > Now without looking it up at the Xilinx website, i.e. using > > > only the press release, what end of the line was extended? > > > > Was anything actually added or is this just a marketing > > > gimmick? =A0Are there new parts or did they just put > > > three series (3A, 3AN, 3A DSP) into one datasheet? > > > > And where is Spartan 4? > > > > Eagerly awaiting much needed clarification, > > > > Gabor > > > > :) > > > New device/package combinations are available. > > > =A0 XC3S50A-VQ100 > > =A0 XC3S200A-VQ100 > > =A0 XC3S700A-FT256 > > =A0 XC3S1400A-FT256 > > > Ed McGettigan > > -- > > Xilinx Inc. > > Oh yeah, I still don't see any of these parts in the VA100 package at > Digikey. =A0Are they in full production? > > Rick delayed as usual AnttiArticle: 134613
On 21 Sie, 08:18, Ghazal <gzl.ja...@gmail.com> wrote: > Hello, > > I want to integrate an image processing algorithm (half tone pixel > converter, etc.) in Xilinx Spartan-3 FPGA (for a demo project only), > and the concern bugging me is how to get a simple image input. > > * Which camera should I use > * Will it be directly controlled by the FPGA and if yes then how, if > no then how will it be controlled > * How will it physically interface with the FPGA > * What will be the image format and how will it be read by the FPGA > * Will an image sensor be easier to interface and use or digital > camera > * Will a video camera take a snapshot image which can be processed > * Will any pre-processing or analog-to-digital conversion of the > image / captured snapshot be required > * Is there a Xilinx prototype board for image capturing only > > If anyone has designed / worked on cameras / images with FPGA .... do > let me know ... it will help me quick start the things here !!! > Anxiously waiting. > > Regards, > Ghazal Javed You can use two aproaches, one is to use a analog video signal (from camera, laptop (S-Video) or anything else) and use a ADC Video converter (if you have a Hirose FX2 port on board you can use VDEC1 http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1&Nav1=Products&Nav2=Accessory , Xilinx has a Verilog demo using the board), second way is to buy a cheap digital camera module (like one in a mobile phone) and connect data lines directly to FPGA, using both ways you will process an YUV/ RGB/Grayscale image it all depends on what you need and what color conversion you will use. >From VDEC1 you will get image formatted to YUV 4:2:2 @25MHz the Xilinx demo convert it to RGB (8-bit per color) @25MHz, basicaly using a digital camera you will get the same format and you will need to reformat it almost the same way as the demo.Article: 134614
On Aug 4, 7:42 pm, Mike Treseler <mtrese...@gmail.com> wrote: > Svenn Are Bjerkem wrote: > > I converted some vhdl files from text to graphics and note that > > connections to signals in records does not get a visual connection to > > the pins where the single wires are supposed to be connected. They are > > just open, and there are no input pins for the records entering the > > block placed. I inspect the generated vhdl and symbol, and they are > > added correctly to the symbol and to the output rtl. > > Anybody know if this is a "feature" or is there an option that I need > > to set somewhere to see the connections? I use version 2007.1a. > > The last time I evaluated a text to graphics application, > I got so annoyed about having to type critical bits of code > into little graphical boxes that I went back to emacs vhdl-mode > and never looked back. We decided to stop paying MGC money for HDL-designer. Using the tool simply took too much time, and since we never really had any control what it did with our files, we scrapped it. Maybe investing some k$ and hours of training would make us productive, but that cycle would start again when another guy enter the team. The features of xemacs vhdl-mode was well known to me up ahead, so I saw no risk in letting HDL-designer go. > > The vhdl-mode browser (speedbar) sorts out locating, editing > and compiling the source files for this or that vhdl design unit. > It also helps with creating structural entities. > vhdl-mode is bread and butter when coding vhdl. I personally like vi better, but I take the tools the way they are. Viper mode is an option, but it never hurts to shift finger gymnastics due to RSI :-) > The quartus rtl viewer does a good job for graphical browsing > and for creating postscript schematic views from the synthesis code. > A key point is that such viewers are a post-process > on working code, rather than a nasty lump in > the design description itself. I use rtlvisionpro from Concept Engineering in Germany for graphical browsing. I know this company from my SPICE days, and they concentrate on what they can, visualizing code, nothing more nothing less. The nice thing about rtlvision is that it give you a quasi-synthesis on the fly so that the graphical view is not just boxes, but also logic gates resulting from the assignments in the HDL. It has a nice link between the code and the graphics so that clicking on a box highlight the respecitve code in the souce. Editing is done with an external editor and then reread into rtlvision. It is not nescessary to add all vhdl files to the project in order to use so large projects can be easily handled. The cone view in rtlvision is extremely useful to track single signals accross hierarchies when looking for mistakes in code. rtlvision reads both vhdl and verilog. I currently have an evaluation license, but I hope to get a more permanent one. Takes a bit time to get used to seeing FSM as logic and comparators than as bubbles, but the naming of those comparators take instance names from the states they get in the code to make it easier. Cool to see how latches are introduced when I forget to assign a signal in a state. -- SvennArticle: 134615
Ghazal <gzl.javed@gmail.com> writes: > Hello, > > I want to integrate an image processing algorithm (half tone pixel > converter, etc.) in Xilinx Spartan-3 FPGA (for a demo project only), > and the concern bugging me is how to get a simple image input. > For a demo, just buy a Xilinx VSK (Video starter kit) and plug it in. It's got a S3ADSP on it, but there's not reason you have to use the DSP48A blocks :) If you *want* to do your own hardware you have three routes: 1) Use off-the-shelf cameras - in which case you are probably going to use a webcam (USB interface) which can be quite a challenge to get an image into your FPGA, or a machine vision camera, which is likely to be Camera Link or GigE vision. A Camera Link interface into FPGA is reasonably straightforward - Xilinx have an appnote (look for 7 to 1 deserialisation). And you can download the specs easily. 2) Make a camera out of an image sensor and lens etc. More hassle/fun (depending on how you look at it). 3) Use an analog camera (eg the video out of a camcorder) and feed it into a digitiser chip. > * Which camera should I use > * Will it be directly controlled by the FPGA and if yes then how, if > no then how will it be controlled > * How will it physically interface with the FPGA See above. > * What will be the image format and how will it be read by the > FPGA It'll be a stream of pixels at some point. > * Will an image sensor be easier to interface and use or digital > camera Yes, but harder to make ;) > * Will a video camera take a snapshot image which can be processed Yes > * Will any pre-processing or analog-to-digital conversion of the > image / captured snapshot be required Maybe, depends on your sensor. Certainly ADC will be needed! But that'll be done on the sensor, or in the camera, unless you go option 3. > * Is there a Xilinx prototype board for image capturing only > VSK will do the lot. > If anyone has designed / worked on cameras / images with FPGA .... do > let me know ... it will help me quick start the things here !!! > Anxiously waiting. > HTH! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 134616
Hi all, sorry for the very dumb question, I am doing something wrong, but I am stuck. Short version: I have a processor that has two serial ports, both are directly accessible ( I can check the output with the scope). One serial port is tied to a FPGA (Spartan 3E) that is connected to a serial adapter. I would like to use the FPGA to route the signal of the uart1 tx pin to the tx pin of the serial adapter. I am using this:Article: 134617
Pete wrote: > I'm wondering if anyone has found a workaround to install Xilinx EDK > 10.1 on Vista x64. 64-bit Vista is not "officially" supported. > However, the 32-bit version of Vista is. The majority of the > applications I use support Vista x64. I'm running some > implementations for a LX330T part, which could really benefit from the > extra memory. I really don't want to dual-boot XP and Vista x64. > > Has anyone found a workaround to at least get the installer to run? I > can deal with EDK crashes (it crashes anyway, in XP). My fingers have > instinctively learned "Ctrl-S" by now. > > Thank you for your help. install vmware player with a Linux distribution. it also enables you to work much faster as bonus. TacoArticle: 134618
"Pete" <petersen.curt@gmail.com> wrote in message news:166ed929-7d1f-495f-91be-e249f810ab5b@y38g2000hsy.googlegroups.com... > I'm wondering if anyone has found a workaround to install Xilinx EDK > 10.1 on Vista x64. 64-bit Vista is not "officially" supported. > However, the 32-bit version of Vista is. The majority of the > applications I use support Vista x64. I'm running some > implementations for a LX330T part, which could really benefit from the > extra memory. I really don't want to dual-boot XP and Vista x64. > > Has anyone found a workaround to at least get the installer to run? I > can deal with EDK crashes (it crashes anyway, in XP). My fingers have > instinctively learned "Ctrl-S" by now. > > Thank you for your help. VMWare?Article: 134619
On Wed, 20 Aug 2008 20:11:59 -0700 (PDT), Pete <petersen.curt@gmail.com> wrote: >Can someone please recommend some VHDL DDR2 SDRAM models? >Specifically, I'm targetting a MT47H64M16 part. I've tried using an >open source model from the "Free Model Foundry," but it's buggy and >doesn't support seamless writes. Micron doesn't seem to be publishing >free VHDL models anymore (only Verilog). We run a VHDL shop and >don't even have Verilog/Mixed licenses for our simulator. Same here, back in the DDR1 era. It's worth looking at Hynix; they published DDR1 models (I think, pre-compiled for Modelsim), they probably also have DDR2. The first step would be to identify their part number that most closely matches the Micron part. Incidentally we still used Micron parts, but the Hynix model seemed to match it well enough. - BrianArticle: 134620
On Aug 21, 6:58 am, "Giuseppe Marullo" <giuseppemarullonotspa...@iname.com> wrote: > I would like to use the FPGA to route the signal of the uart1 tx pin to the > tx pin of the serial adapter. You will need to define appropriate input and output pins on the fpga, with appropriate I/O voltage standards. Then you will need to connect them together with a combinatorial path int the FPGA fabric, for example the "wire" type in verilog. If you can find a demo project for your board, often it would be easiest to just add this one connection to that (and then maybe cut out some of what you don't need) rather than try to figure it all out from scratch. This might be one of the few cases where schematic entry if still available in your fpga tools would shine compared to a language such as verilog or vhdl. All of this assumes that the FPGA can tolerate and generate suitable voltages for what it is connected to.Article: 134621
I stumbled onto this when looking for fpga/sdram combo: Apple II on FPGA: http://www1.cs.columbia.edu/~sedwards/apple2fpga/ http://www1.cs.columbia.edu/~sedwards/apple2fpga/apple2fpga-0.1.tar.gzArticle: 134622
On Aug 21, 7:43=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > "Pete" <petersen.c...@gmail.com> wrote in message > > news:166ed929-7d1f-495f-91be-e249f810ab5b@y38g2000hsy.googlegroups.com... > > > I'm wondering if anyone has found a workaround to install Xilinx EDK > > 10.1 on Vista x64. =A064-bit Vista is not "officially" supported. > > However, the 32-bit version of Vista is. =A0The majority of the > > applications I use support Vista x64. =A0I'm running some > > implementations for a LX330T part, which could really benefit from the > > extra memory. =A0I really don't want to dual-boot XP and Vista x64. > > > Has anyone found a workaround to at least get the installer to run? =A0= I > > can deal with EDK crashes (it crashes anyway, in XP). =A0My fingers hav= e > > instinctively learned "Ctrl-S" by now. > > > Thank you for your help. > > VMWare? Looks like taco is talking about "VMWare Workstation" from a company named vmware (vmware.com). I'm reading about it now. It sounds......kind of scary: quote: "VMware Workstation 6 makes it simple to create and run multiple virtual machines on your desktop or laptop computer. You can convert an existing physical PC into a VMware virtual machine, or create a new virtual machine from scratch. Each virtual machine represents a complete PC, including the processor, memory, network connections and peripheral ports. VMware Workstation lets you use your virtual machines to run Windows, Linux and a host of other operating systems side-by-side on the same computer. You can switch between operating systems instantly with a click of a mouse, share files between virtual machines with drag-and- drop functionality and access all the peripheral devices you rely on." It sounds great, in theory....but does it work? What happens when I'm using EDK in my WinXP virtual machine, and I switch over to my Vista virtual machine? I've had some bad experiences with using the Xilinx programming cable driver on Linux, and this sounds even more complicated to me I'm going to get the 30-day license and give it a shot. Thanks so much!Article: 134623
On Thu, 21 Aug 2008 11:47:23 -0700 (PDT), Pete <petersen.curt@gmail.com> wrote: >Looks like taco is talking about "VMWare Workstation" from a company >named vmware (vmware.com). I'm reading about it now. It >sounds......kind of scary: > Actually it's. It's scary good. >It sounds great, in theory....but does it work? What happens when I'm >using EDK in my WinXP virtual machine, and I switch over to my Vista >virtual machine? I've had some bad experiences with using the Xilinx >programming cable driver on Linux, and this sounds even more >complicated to me I haven't tried programming cables but USB flash works very nicely. I have windows 2k & centos 6 under Vista 64 and everything works very nicely. One very nice thing is that you never have to re-install an old app again when you move to a new machine. You just copy the VM under which the app is installed and you're done. When machines become powerful enough I'm considering running in a completely virtual environment so there won't be a need to make a new machine as long as I need the same apps.Article: 134624
stewarma@gmail.com wrote:
> I want to implement 1280x1024but cannot synthesize an 108MHz pixel
> block for the timing. I would prefer to use a 100 MHz (generated from
> 200) but can also make a 104 or 112 Mhz.
>
> Normal 1280x1024 timing:
> Horizontal
> Resolution pixels: 1280
> Front porch pixels: 48
> Sync pulse pixels: 112
> Back porch pixel: 248
> Veritcle
> Resolution lines: 1024
> Front porch lines: 1
> Sync pulse lines: 3
> Back porch lines: 38
>
> Has anyone had any experience altering the porch/sync lengths and
> pixel clock to keep 60Hz that will sync to an LCD monitor?
>
> Thanks!
I pulled this piece of code from a video controller I wrote a while back:
"1280x1024_60Hz": // pixel clk 110MHz
begin
H_FRONT_PORCH=48; HSYNC_WIDTH=112;
H_BACK_PORCH=248; LEFT_BORDER=0; LINE_WIDTH=1280;
RIGHT_BORDER=0; V_FRONT_PORCH=1; VSYNC_WIDTH=3;
V_BACK_PORCH=38; TOP_BORDER=0; FRAME_HEIGHT=1024;
BOTTOM_BORDER=0; SYNC_POLARITY=1;
end
This seems to be exactly what you have. My comments note that I used a
110MHz clock. (This HDL did work in hardware testing on the LCD
monitors I tried.) You have some leeway in what refresh rates you can
use. If your pixel clock is 112MHz, that will probably work fine, and
will just have a refresh rate a little higher than 60Hz. I think if you
want something closer to 60Hz you can stuff extra pixels/lines into the
front/back porch, but I would just try the 104 or 112MHz pixel clocks
with the constants you already have.
-Kevin
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