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Bryan, Thanks for the tip on the avnet example. I was looking for such an example, but failed to find one. Mike On Dec 11, 9:46=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > Avnet has an example using a 1Mx8 Cypress MicroPower SRAM with > Spartan-3A MicroBlaze (EDK 10.1.3). =A0You can find it atwww.em.avnet.com= /mxp-sram > --> Support Files & Downloads. =A0The example was generated using BSB, > which automatically instantiates IP UTIL_BUS_SPLIT to align the > busses. > > BryanArticle: 136901
On Dec 11, 12:37=A0pm, Marlboro <cco...@netscape.net> wrote: > Just a polling question, which way people use the most to insert the > Chipscope into the design? > > For my own, if using the Inserter to add Chipscope to the ngc netlist, > then there're chances the Tranlate step has changed your net names > around make it difficult to see and attach what you have built and > want to attach to the scope > > Thnks I guess it depends on whether you think about what you want to look at before or after you have built the design. Sometimes when you know something will require debugging you can place the ILA in the appropriate place while you are writing the code. For me the biggest reason to use the inserter is when I have a design that takes a long time to synthesize and I want to debug something I've found to be a problem late in the design process. Another point is trying to debug a design with a lot of hierarchy where getting debug signals to the ILA involves adding lots of debug ports to lower level modules. I will admit that poring through the translated net names and attaching them to the core is a bit of a pain. I guess there's no free lunch... Regards, GaborArticle: 136902
Hi Marboro, Marlboro wrote: > For my own, if using the Inserter to add Chipscope to the ngc netlist, > then there're chances the Tranlate step has changed your net names > around make it difficult to see and attach what you have built and > want to attach to the scope For me it's a matter of where in the development process I am. If I know that my design is complex and requires debugging I will put in at a early stage as an IP. If the design is synthesized and I keep changing where the probes are places it's much faster to merge it into the netlist. However to help yourself with the net names you can force the compiler not to flatten your design leaving your net-names in a readable form. I can't remember exactly where to do this and I don't have ISE here. So you have to dig into it yourself. Regards JanArticle: 136903
On Dec 8, 4:57=A0am, xiaoling...@fme.fujitsu.com wrote: > Hi there, > I'm wondering whether it's possible to put both an encrypted design > and an unencrypted design into the same FPGA device (Virtex 5), and > they should work together side by side and interact with each other . Yes, it is possible. It depends on the type of encryption algorithm and the over all design. If encryption/decryption is the only design that you want to implement in FPGA then its easily possible.Article: 136904
On Thu, 11 Dec 2008 11:26:39 +0000 (UTC), Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote: >On 2008-12-11, Brian Drummond <brian_drummond@btconnect.com> wrote: >> One option would be to translate a post-synthesis netlist (e.g. from >> Quartus or Xilinx Webpack) which has already been translated into a >> finite set of primitives; 4-LUTs, carry structures and the like. > >You should probably read the EULA thoroughly before doing this though. >I believe that all major FPGA vendors have some language in the EULA >which tries to prohibit you from doing this. Good point. I expect the OP could ask his vendor for a specific limited waiver for academic purposes. - BrianArticle: 136905
xiaoling...@fme.fujitsu.com wrote: > I'm wondering whether it's possible to put both an encrypted design > and an unencrypted design into the same FPGA device (Virtex 5), and > they should work together side by side and interact with each other . karthick.ramu@gmail.com writes: > Yes, it is possible. It depends on the type of encryption algorithm > and the over all design. If encryption/decryption is the only design > that you want to implement in FPGA then its easily possible. I think the OP was referring to use of an encrypted FPGA configuration bitstream, not the use of soft encryption/decryption IP blocks in the FPGA. If so, I think the answer is that the configuration bitstream is either entirely encrypted or not encrypted at all.Article: 136906
On Dec 12, 8:02=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 11 Dec 2008 11:26:39 +0000 (UTC), Andreas Ehliar > > <ehliar-nos...@isy.liu.se> wrote: > >On 2008-12-11, Brian Drummond <brian_drumm...@btconnect.com> wrote: > >> One option would be to translate a post-synthesis netlist (e.g. from > >> Quartus or Xilinx Webpack) which has already been translated into a > >> finite set of primitives; 4-LUTs, carry structures and the like. > > >You should probably read the EULA thoroughly before doing this though. > >I believe that all major FPGA vendors have some language in the EULA > >which tries to prohibit you from doing this. > > Good point. I expect the OP could ask his vendor for a specific limited > waiver for academic purposes. > > - Brian Thanks for your reply! I actually emailed our vendor to see if they have any support for this, as I know there is an open standard that I should be able to use to define my FPGA but can't remember where I saw it. I also thought about using icarus, because then I wouldn't need to worry so much about vendor specific limitations. I have been looking at ODIN (a part of VPR) which does this, running icars to map a verilog file to a custom architecture (with hetrogenous blocks, etc), so maybe I can change the configiration file used to match my architecture and use this. Although there dosen't seem to be any documentation on how to do this so I am currently reading though the source. ---If anyone has any experence with using VPR/ODIN for research and could possible help me with using ODIN/icarus to map to a custom FPGA architecture that would be a great help! (it really is a simple architecture, 3 input LUTs and carry chains) BenArticle: 136907
Gabor schrieb: > On Dec 11, 12:37 pm, Marlboro <cco...@netscape.net> wrote: >> Just a polling question, which way people use the most to insert the >> Chipscope into the design? >> >> For my own, if using the Inserter to add Chipscope to the ngc netlist, >> then there're chances the Tranlate step has changed your net names >> around make it difficult to see and attach what you have built and >> want to attach to the scope >> >> Thnks > > I guess it depends on whether you think about what you want to look > at before or after you have built the design. Sometimes when you > know something will require debugging you can place the ILA in > the appropriate place while you are writing the code. > > For me the biggest reason to use the inserter is when I have a > design that takes a long time to synthesize and I want to debug > something I've found to be a problem late in the design process. > Another point is trying to debug a design with a lot of hierarchy > where getting debug signals to the ILA involves adding lots > of debug ports to lower level modules. I will admit that poring > through the translated net names and attaching them to the core > is a bit of a pain. As for designs with deep hierarchy, can you use global signals (in VHDL) and connect the Chipscope to them? Of course, this is difficult when using multiple instances of the same module. > > I guess there's no free lunch... > > Regards, > GaborArticle: 136908
On Dec 11, 3:12 pm, hardbreaker <goo...@schwarzers.de> wrote: > Does someone has a mini EDK project with sources for me ? > I would really appreciate it ... :-) Download a Genode FX project http://sourceforge.net/projects/genode-fx/ Cheers, AlesArticle: 136909
On Dec 11, 6:37 pm, Marlboro <cco...@netscape.net> wrote: > Just a polling question, which way people use the most to insert the > Chipscope into the design? > > For my own, if using the Inserter to add Chipscope to the ngc netlist, > then there're chances the Tranlate step has changed your net names > around make it difficult to see and attach what you have built and > want to attach to the scope > > Thnks I use Chipscope in EDK. For my (custom) cores I always attach a 32bit chipscope port. I use ILA for monitoring and IBA for bus analysis. Cheers, AlesArticle: 136910
Just a question if anybody has some pointers for the following: We need a FPGA board for dsp operations (preferred Xilinx fpga) with 8 channels input with highspeed ADC. Every channel should be sampled at >1 MSPS. There should be enough FPGA and RAM space to buffer results (32 MB for example). Sundance is offering something which is in this direction, but with an annoying closed software environment. It would be nice if it's a board which can be directly plugged in to simulink->system generator-> ise. thanks for any information. TacoArticle: 136911
I don't insert debug logic post-synthesis because: 1. Digging through machine generated net names is tedious and painful 2. It creates a substantial risk of "false negative". Indeed, synthesis perform deep optimizations that can throw you off when observing the mapped netlist. For example, if an adder was shared during synthesis, its output will differ from the RTL adder you *think* you are observing, and you'll end-up chasing a false bug. The analogy for SW people out there, is that I much prefer debugging source code than compiled machine code... I thus prefer inserting debug logic in RTL since it forces the synthesis tool to exactly maintain the logic function of the nets I am observing. Now, RTL insertion usually means modifying the HDL, which I dislike for obvious reasons. For that, I like tools like Identify that lets you insert your debug logic in your HDL through a graphical interface (mouse clicks) and then spin-out a modified HDL with the debug logic. Finally, on the runtime issue, I found that the synthesis machine time was well worth my working time saved not doing tedious work. In addition, the synthesis runtime is often a fraction of the P&R runtime, thus a marginal cost.Article: 136912
Gael Paul wrote:
> I don't insert debug logic post-synthesis because:
> 1. Digging through machine generated net names is tedious and painful
> 2. It creates a substantial risk of "false negative".
Well said.
A post-synthesis problem rarely has anything to do with synthesis.
It is either a logical problem, or a timing problem.
-- Mike Treseler
Article: 136913while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800 starter kit, I got this error : Place:848 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further information see the "Quadrant Clock Routing" section in the Spartan3adsp Family Datasheet. The competing Global / Side clock buffers for this device are as follows: BUFGMUX_X2Y1 : BUFGMUX_X0Y2 BUFGMUX_X2Y0 : BUFGMUX_X0Y3 BUFGMUX_X1Y1 : BUFGMUX_X0Y4 BUFGMUX_X1Y0 : BUFGMUX_X0Y5 BUFGMUX_X2Y11 : BUFGMUX_X0Y6 BUFGMUX_X2Y10 : BUFGMUX_X0Y7 BUFGMUX_X1Y11 : BUFGMUX_X0Y8 BUFGMUX_X1Y10 : BUFGMUX_X0Y9 BUFGMUX_X2Y1 : BUFGMUX_X3Y2 BUFGMUX_X2Y0 : BUFGMUX_X3Y3 BUFGMUX_X1Y1 : BUFGMUX_X3Y4 BUFGMUX_X1Y0 : BUFGMUX_X3Y5 BUFGMUX_X2Y11 : BUFGMUX_X3Y6 BUFGMUX_X2Y10 : BUFGMUX_X3Y7 BUFGMUX_X1Y11 : BUFGMUX_X3Y8 BUFGMUX_X1Y10 : BUFGMUX_X3Y9 I am new to quadrant clock constraint, can somebody provide help to manualy place the BUFGMUXes... regardsArticle: 136914
taco <blop@joepie.org> wrote in news:ghtge2$1lb$1@usenet.uva.nl: > Just a question if anybody has some pointers for the following: > We need a FPGA board for dsp operations (preferred Xilinx fpga) with 8 > channels input with highspeed ADC. Every channel should be sampled at >1 > MSPS. There should be enough FPGA and RAM space to buffer results (32 MB > for example). > Sundance is offering something which is in this direction, but with an > annoying closed software environment. It would be nice if it's a board > which can be directly plugged in to simulink->system generator-> ise. > thanks for any information. > Taco > We have part of the solution now and a plan sometime next quarter. Our dspblok 21369cy05 or 21369cy25 is a combo SHARC DSP - Cyclone 3 board. We are planning a high speed 8 channel ADC. We have 2 channel combos now. Check out our web site or email me if you are interested. Al ClarkArticle: 136915
I normally will test the design in real hardware and see where it breaks to get an idea of what the system margins are. I say normally because I still do some designs that are sub 50MHz and in these cases for the most part I trust that if the static report and post route simulations say its good, its good. So, no I don't ignore the information from ISE, Aldec or Mentor but I sure don't take any of them as the gospel truth. Good luck with your design.Article: 136916
Hello, My name is Nadav and I am the author of http://www.C-to-Verilog.com ; This website allows FPGA developers to take regular C code and "compile" it into Verilog. The Verilog code can be verified with the auto generated test-bench and then synthesized to an FPGA. The compiler tries to "pipeline" as much code as possible to get a design which is fast, operates at high frequencies and takes as few resources as possible (LUT, DSPs, BRams, etc). I would appreciate any feedback. Nadav RotemArticle: 136917
On Dec 11, 4:08=A0am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > When reading for example the Virtex 4 datasheet under > switching characteristics. More specifically the section > named "Clock Buffers and Networks", there is a value > F_MAX which is specified as the maximum frequency for > a global clock tree. This value is 500 MHz in a Virtex-4 > speedgrade 12. > > However, when synthesizing simple designs which are heavily > pipelined it is easy to get a design which the static timing > analysis tool reports as having a maximum frequency of > significantly higher than 500 MHz in a speedgrade 12 device. > > There is no warning in the trce output about exceeding F_MAX. > > Since I have bitten in the past by the static timing analyser [1] > I thought it best to ask here whether trce is right in ignoring > F_MAX or not. My guess is that trce is indeed ignoring the maximum clock specification. IIRC, the maximum clock frequency specification indicates where you start to have significant rise/fall mismatch on the clock tree. Even with a 500 MHz clock, you can theoretically build functions that operate near 1 GHz using DDR flip-flops or clocking on both edges. -- Steve Knapp Prevailing Technology, Inc. (www.prevailing-technology.com)Article: 136918
Hi, I like to give you a first feedback before having a look at your tool just based on your announcement. On 13 Dez., 12:18, Nadav Rotem <nadav...@gmail.com> wrote: > compiler tries to "pipeline" as much code as possible to get a design > which is fast, operates at high frequencies and takes as few resources > as possible (LUT, DSPs, BRams, etc). > > I would appreciate any feedback. It sounds wrong to me when you convert an algorithm by "pipeline as much as possible to get high frequencies and take as few resources as possible". You should give the user the abbility to select between high frequency and few resource usage by additional constraints, because high frequency and few resource usage are typically contradictional tradeoffs. bye ThomasArticle: 136919
Depending on your timescales and actual needs we may have something coming to suit. Firstly I'd suggest looking at our Hollybush2 http://www.enterpoint.co.uk/oem_industrial/hollybush2.html as a base processing engine. We do have other things that might suit as well so do have a browse of our products. The DSP side of this board is not as polished as the Sundance offering but I would think it is a lot cheaper. For the ADC side we do have a companion board coming but you can also buy off the shelf ADC boards in either the ISA or PCI PC104 format and use with this board. That will require a ISA or PCI implementation within the FPGA design. We do also have an ADC module coming for our standard headers used on Raggedstone and Broaddown families of boards. We can also supply our AD7927 module as a AD7928 module (1msps) to special order, Don't rely on being able to use all 16 channels at 1Mhz due to the SPI bandwidth limitations but you can certainly get 2 or 4 going at that rate. John Adair Enterpoint Ltd. On 12 Dec, 11:03, taco <b...@joepie.org> wrote: > Just a question if anybody has some pointers for the following: > We need a FPGA board for dsp operations (preferred Xilinx fpga) with 8 > channels input with highspeed ADC. Every channel should be sampled at >1 > MSPS. There should be enough FPGA and RAM space to buffer results (32 MB > for example). > Sundance is offering something which is in this direction, but with an > annoying closed software environment. It would be nice if it's a board > which can be directly plugged in to simulink->system generator-> ise. > thanks for any information. > TacoArticle: 136920
I only ever wanted WebPack. However by using the Web Install Client and then installing, I ended up with the 60 day evaluation version of Foundation. This has now expired and I expected the functionality of the software to revert to WebPack but it just doesn't work (P&R won't run for small or large devices). How do I go about getting WebPack from this position please? TIA, Roger.Article: 136921
This sounds interesting, thanks for sharing. i'll try it sometime On Dec 13, 2:51=A0pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > Hi, > > I like to give you a first feedback before having a look at your tool > just based on your announcement. > > On 13 Dez., 12:18, Nadav Rotem <nadav...@gmail.com> wrote: > > > compiler tries to "pipeline" as much code as possible to get a design > > which is fast, operates at high frequencies and takes as few resources > > as possible (LUT, DSPs, BRams, etc). > > > I would appreciate any feedback. > > It sounds wrong to me when you convert an algorithm by "pipeline as > much as possible to get high frequencies and take as few resources as > possible". > You should give the user the abbility to select between high frequency > and few resource usage by additional constraints, because high > frequency and few resource usage are typically contradictional > tradeoffs. > > bye ThomasArticle: 136922
On Dec 13, 9:51=A0pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > Hi, > > I like to give you a first feedback before having a look at your tool > just based on your announcement. > > On 13 Dez., 12:18, Nadav Rotem <nadav...@gmail.com> wrote: > > > compiler tries to "pipeline" as much code as possible to get a design > > which is fast, operates at high frequencies and takes as few resources > > as possible (LUT, DSPs, BRams, etc). > > > I would appreciate any feedback. > Hi Thomas, Thank you for the feedback. I agree with what you have said. First, I identify the parallelism. Later I decide which parts I want to exploit. I let the user decide between several trade-offs. The user needs to decide between "cycles for completion" "design size" and "design frequency". The users cannot control these directly but only via the number or resources they assign to the circuit (example: memorts, multipliers, etc). Also, the properties of the resources they assign will determine the frequency. A 5-stages multiplier will operate at a much higher clock frequency than a 2-stages pipelined multiplier. This is also configurable. The video in the website shows some of the configuration options. Nadav Rotem > It sounds wrong to me when you convert an algorithm by "pipeline as > much as possible to get high frequencies and take as few resources as > possible". > You should give the user the abbility to select between high frequency > and few resource usage by additional constraints, because high > frequency and few resource usage are typically contradictional > tradeoffs. > > bye ThomasArticle: 136923
Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote:
>
>When reading for example the Virtex 4 datasheet under
>switching characteristics. More specifically the section
>named "Clock Buffers and Networks", there is a value
>F_MAX which is specified as the maximum frequency for
>a global clock tree. This value is 500 MHz in a Virtex-4
>speedgrade 12.
>
>However, when synthesizing simple designs which are heavily
>pipelined it is easy to get a design which the static timing
>analysis tool reports as having a maximum frequency of
>significantly higher than 500 MHz in a speedgrade 12 device.
>
>There is no warning in the trce output about exceeding F_MAX.
IMHO there are 2 seperate things to consider: F_MAX and flip-flop to
flip-flop delays. F_MAX is a property of the clock tree. Even if the
flip-flop to flip-flop delay allows for higher clock speeds, the
maximum frequency of the clock tree is the limit. In other words, you
can reduce the number of pipeline stages so the flip-flop to flip-flop
delay increases because more logic is in between.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 136924Hi all, I need some advice from FPGA experts and users. I am a front-end ASIC designer with very little experience in FPGA. Recently I have been thinking if I could buy an FPGA board and try and learn certain things in the field of digital design that I don't know very well yet. For example, (1) I would like to understand the backend flow better and be able to perform synthesis and STA. (2) I would also like to do something related to DFT. I need some hands-on experience to understand it better. (3) Besides, any other interesting design stuff will be fun to do. So, my questions are: * My basic assumption is whatever I learn on the FPGA platform will more or less translate into ASIC domain too. Is that right? * Which board(s) can you recommend for this? My budget is $100 to $200. Anything else I need to buy (for example, peripherals)? * Do I need to purchase tools for synthesis, STA etc separately, or do they come as a package with the board? * Can you suggest some website that has interesting FPGA projects, especially on the topics I mentioned above? Thanks in advance for any advice on this.
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