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Messages from 14125

Article: 14125
Subject: AHDL VS. VHDL
From: aweas <aweas_rammal@elgems.com>
Date: Thu, 14 Jan 1999 22:56:03 +0100
Links: << >>  << T >>  << A >>
Hi
I think a lot of poeple made the transfer from altera's ahdl to vhdl.
those how did it , can you please give me some feed back about the
results.
and info about the transfer to VHDL .
I'll be happy to get as much answer's as possible

thank you
Aweas

Article: 14126
Subject: AHDL VS. VHDL
From: aweas <aweas_rammal@elgems.com>
Date: Thu, 14 Jan 1999 22:56:31 +0100
Links: << >>  << T >>  << A >>
Hi
I think a lot of poeple made the transfer from altera's ahdl to vhdl.
those how did it , can you please give me some feed back about the
results.
and info about the transfer to VHDL .
I'll be happy to get as much answer's as possible

thank you
Aweas

Article: 14127
Subject: AHDL VS. VHDL
From: aweas <aweas_rammal@elgems.com>
Date: Thu, 14 Jan 1999 22:57:05 +0100
Links: << >>  << T >>  << A >>
Hi
I think a lot of poeple made the transfer from altera's ahdl to vhdl.
those how did it , can you please give me some feed back about the
results.
and info about the transfer to VHDL .
I'll be happy to get as much answer's as possible

thank you
Aweas

Article: 14128
Subject: Digital design services
From: "ovilup" <ovilup@mail.dnttm.ro>
Date: 14 Jan 1999 22:31:38 GMT
Links: << >>  << T >>  << A >>

Dear Madam/Sir,

We are a small profesional engineering team in Romania, Timisoara. We can
provide accurate and inexpensive IT designs in different domains like :
avionics, industrial, automotive, computers, mobile communications, etc.

In VHDL we can provide the following services :
   - a) Boardlevel models development
   - b) Boardlevel testing
   - c) Cores development

a) Boardlevel models development
At this level it is simulated the functionality of one or several printed
circuits boards builts with standard components. Board level simulation's
purpose is to verify the correct behavior of the board - that components
operate as intended in selected configurations.

When board designs contain processors, it is possible to verify the
hardware-software interaction, for example verifying the programmability
of ASIC registers, the operation of software drivers, and so on. 
In addition, we can evaluate the performance of the processor board. 
Board level simulation will also yield information about timing 
correctness, though it can probably not fully replace worst-case timing 
analysis for high-reliability applications.

By employing board level simulation, designers can integrate and test 
printed circuit boards early, since the first design and verification loop
does not need manufactured hardware.

We will deliver the source code for every model we develop, the testbench 
files and *.ps files with timing diagrams implemented.

b) Boardlevel testing
Based on the experience described above, we can implement the test
procedures
for custom printed circuit boards. We will deliver the entire's board
source
code for test programs in VHDL, *.ps files with timing diagrams and report
files with warnings or errors if a timing violation is found on custom
configuration.

c) Cores development
At this level we can develop ASIC's architectures by developing RTL code.
We can develop custom requested ASIC's to be implemented in FPGA's. For 
example, we can develop I2C controllers, ALU's, small DSP's, PCI-bus
devices, DMA controllers. We need written specification's for custom
devices to be developped.

Interested parties please e-mail the following enquiry form us, to the
one of the following e-mail account : 

    ovilup@mail.dnttm.ro

                    *** Services Reply Slip ***

We are interested in your 

__ VHDL boardlevel model development

__ VHDL boradlevel testing

__ VHDL core development

__ Digital design (microcontrollers, DSPs)

__ Software development


Our project description :
_____________________________________________________

____________________________________________________________________________
___

____________________________________________________________________________
___

____________________________________________________________________________
___

Company :        __________________________________________

Address :        __________________________________________

Tel :            __________________________________________

Fax :            __________________________________________

E-mail :         __________________________________________

Web Site :       __________________________________________

Contact person : __________________________________________
Article: 14129
Subject: FPGA/core PCI interface system
From: John Schewel <jas@vcc.com>
Date: Thu, 14 Jan 1999 16:19:37 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------89B355A54984C401737CC5E9
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

FYI

The cost of developing an FPGA/core PCI interface system just got a lot
cheaper.  
PLD Consulting Editor Murray Disman gives the scoop on a two team
approach in 
which two companies provide a populated board and netlist for a PCI
target for 
just $695. Compare that to $8,000 for a PCI core. Wow. But there's a
catch.
http://www.edtn.com/shared/redirect?url=http://www.edtn.com/pld/pldp.htm&source_code=26


-- 

Best Regards,
John Schewel, VP Marketing & Sales
Virtual Computer Corp.
http://www.vcc.com
--------------89B355A54984C401737CC5E9
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for John Schewel
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             John Schewel
n:              Schewel;John
org:            Virtual Computer Corporation
adr:            6925 Canby Ave. #103;;;Reseda;CA;91335;USA
email;internet: jas@vcc.com
title:          VP Marketing & Sales
tel;work:       +1 (818) 342-8294
tel;fax:        +1 (818) 342-0240
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard


--------------89B355A54984C401737CC5E9--

Article: 14130
Subject: Re: AHDL VS. VHDL
From: Brett George <b.george@clarityeq.com>
Date: Fri, 15 Jan 1999 12:51:40 +1000
Links: << >>  << T >>  << A >>
do you want me to answer all three queries?

Anyway, thought you might be interested to know that I have performed
one design using AHDL/graphical logic. And found AHDL very difficult
to use when trying to do things more complicated than can be visualised
in terms of gates. Things like asyncronous state-machines had to be
re-designed
in terms of edge triggered FFs etc.
    We will be making the move to VHDL shortly, for the next design and
expect
much better results. It seems to be a lot more flexible, as it is an
actual language,
rather than a text based logic system.

Will let you know how it went in a few weeks if you are still interested.

Brett.

aweas wrote:

> Hi
> I think a lot of poeple made the transfer from altera's ahdl to vhdl.
> those how did it , can you please give me some feed back about the
> results.
> and info about the transfer to VHDL .
> I'll be happy to get as much answer's as possible
>
> thank you
> Aweas



Article: 14131
Subject: HEX file format
From: "Kang YI" <yk@comp.snu.ac.kr>
Date: Fri, 15 Jan 1999 12:25:42 +0900
Links: << >>  << T >>  << A >>
Hello,

I'll appreciate if you let me know the Intel HEX file format.

Thank you.

Kang YI.


Article: 14132
Subject: Xilinx Bitstream
From: "Kang YI" <yk@comp.snu.ac.kr>
Date: Fri, 15 Jan 1999 12:28:07 +0900
Links: << >>  << T >>  << A >>
Hello,

Is there anyone who know the Xilinx Bitstream file format ?
I'm going to write a program that downloads the *.bit file from XACT tool to
Xilinx FPGA chip.

Thank you in advance.

Kang YI.


Article: 14133
Subject: DFF/Couter behavior with clock and control signals change
From: "Kang YI" <yk@comp.snu.ac.kr>
Date: Fri, 15 Jan 1999 12:55:25 +0900
Links: << >>  << T >>  << A >>
I have simple questions on the behavior of DFF with enable.(Assume that the
DFF is active-high.)

1. Do you know what happens if the data input and clock are changed
simultaneously from low to high ? (Does it imply any unstable output ?)

2. What happens if the DFF's data-input, enable signal, and clock are
changed simultaneously from low to high ?
(Does it imply unstable output ?)

I also cannot assure what happens when I use synchronous counters with
load-enable and increment control signals
for the similar condition above.
I'll happy if anybody gives me an answer.

Thank you.

Kang.


Article: 14134
Subject: Re: 1-wire
From: David Brantley <dumb1@worldnet.att.net>
Date: 15 Jan 1999 04:31:04 GMT
Links: << >>  << T >>  << A >>
Look at www.ibutton.com for info on all of Dallas Semi 1-wire chips.

G Henry Yogendran wrote:
> 
> Hi:
> 
> Can anybody tell me where I can get 1-wire interface code for
> Dallas parts.
> 
> Henry
> --
> ------------------------------------

Article: 14135
Subject: Re: DFF/Couter behavior with clock and control signals change
From: Ray Andraka <randraka@ids.net>
Date: Thu, 14 Jan 1999 23:45:25 -0500
Links: << >>  << T >>  << A >>
If you do not violate the setup and hold times for the particular inputs to the
flip-flop, it will behave as intended.  If you do violate either, the operation
can be unpredictable which means it may land in either stable state or in a
metastable state.  Picture the metastable state as a coin that has landed on
it's edge when flipped.  Eventually a disturbance will move the ff out of the
metastable state to one of the two stable states.  The time required to reach a
stable state is indeterminant (it is a probability function).

Good design practice calls for synchronous design and care to meet the setup
and hold requirements.  There are times (when accepting an external
asynchronous input for example) when the possibility of metastability cannot be
eliminated.  In those cases you will try to minimize the effect on the system
by 1) making the window where the setup and hold are violated small compared to
the clock interval of the interfacing flip-flop and/or 2) registering the
output of the first flip-flop with a second (or a chain of several) flip-flops
to reduce the probability of a metastable event at the system input (after the
syncronizing flip flops)

Kang YI wrote:

> I have simple questions on the behavior of DFF with enable.(Assume that the
> DFF is active-high.)
>
> 1. Do you know what happens if the data input and clock are changed
> simultaneously from low to high ? (Does it imply any unstable output ?)
>
> 2. What happens if the DFF's data-input, enable signal, and clock are
> changed simultaneously from low to high ?
> (Does it imply unstable output ?)
>
> I also cannot assure what happens when I use synchronous counters with
> load-enable and increment control signals
> for the similar condition above.
> I'll happy if anybody gives me an answer.
>
> Thank you.
>
> Kang.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14136
Subject: Re: Hard porting to FPGA Express
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Jan 1999 03:29:52 -0500
Links: << >>  << T >>  << A >>
Ido Kleinman wrote:
> 
> Hi!
> 
> I've been using Foundation 1.4 with it's Metamor synthesis for a while now,
> and I've got a few working designs.
> I recently moved to Foundation 1.5 and it's FPGA Express synthesis -
> I haven't been able to even successfully compile my previously WORKING
> designs:

I feel your pain. I just went through the same process. It took me about
2 weeks to convert one design with about 7 VHDL files. Unfortunately,
Xilinx doesn't really explain the various VHDL differnces you are likely
to encounter between the two compiliers. And the syntax stuff is just
the tip of the iceburg! I found that the resulting gates produced are
very inefficient unless you make even more drastic changes to your VHDL.
One of my modules which has a large state machine as well as many
assorted control registers, had to be almost completly rewritten. I
ended up making so many calls to Xilinx support (I'm a pretty squeeky
wheel) that I am on a first name basis with Jonathan T. and Mike P.! 
(Hi, guys  ~(:-)

 
> 1. FPGAEXP won't accept:
> if (LowerAddressBus > X"01F0") then
> 
> LowerAddressBus is just a std_logic_vector(15 downto 0).
> it yells about type mismatch between left/right binary operand. The X seems
> to be disturbing - it would only accept Binary notation without any prefix
> to the " character so I have to write:
> 
> if (LowerAddressBus > "0000000111110000") then
> 
> I tried using based literals such as 16#01F0# and variations - and it won't
> work. Any solution, or I will have to do all my comparisons in Binary?

Steve's posting likely has the best solution. I don't like either
approach. It is a bit rediculous having to declare a constant vector for
every stinkin' vector literal in your program. 
 

> 2. My inhibit_buf attribute on my global Clk signal wasn't accepted! What's
> the attribute for inhibiting insertion of IBUFs/OBUFs/etc on FPGAEXP? I
> don't want my clock signal buffered with a standard IBUF, that why I usually
> instanciate a BUFG/BUFGS for it and inhibit other buffers on the pad in the
> code.

There are many attributes that can no longer be used. Or as I found out,
they can't be used in some contexts. I picked up a trick of using 'left
or 'high or 'range to make aggregates follow the size of other vectors.
But you can't do this in Express. Kinda takes the fun out of programming
in an HDL when you can't use the H part!
 

> 3. After I made the annoying adjustments to my code, my previously working
> simulation files yielded strange new results in which some output signals
> were defined as "????" - what's this? I thought std_logic "only" has 9
> states...

The ? in a simulation just means that some of the bits in the Hex nibble
are not 1 or 0. You have a 10X0 for example. 
 

> 4. What about my two-dimensional arrays? I am not trying to synthesize
> anything special - just some
> better-looking-VHDL multi-bit look-up tables... FPGAEXP won't support it?
> Forever?

All I can do here is grin...
 

> Anyone who can help me out here - even to some of my problems, would be
> blessed.
> Sorry for my lame English, it ain't my mother-tounge... :-)
> Thanks in advance,
> 
> --
> 
> Yours,
>   -- Ido Kleinman.
>   kleinn@REMOVETHIS.mail.biu.ac.il
>  ** Please delete the "REMOVETHIS." substring to EMail me.

If you look at the XNF files from your VHDL you will see that anyplace
you put if statments inside of your if (rising_edge(clk)) then, you will
get a signal on the clock enable of the FF. This is great if you want to
use the CE. I had problems getting it to use the CE when using the Orcad
compiler. But Express can put more logic on the CE than it does on the D
input! I defined a loadable 4 bit counter and got an incredible mess of
gobbledygook for the gates feeding the CD and D inputs. I can't even
figure out how it works! 

So the moral is, keep your clocked processes very, very simple, AND
define the combinatoral logic in a separate process. 

I will cut it short here, but there is a whole chapter written in my
book of Express quirks concerning the use of one-hot state machines.
Let's just say this is the first VHDL compiler that I have heard of that
would make a 16 state, one hot encoded state machine out of 15 FFs...
That's right, it uses the state of no FFs set for a state where I told
it to set the FF that is gone!

Not that I am complaining! I just keep telling myself that this is
better than the compiler I was using before I got the Foundation
package. Notice that I didn't mention any names... for once!  ;)

You do know that you can still use the Metamor compiler with F1.5,
right?

PS some people have said that Synopsys makes a higher end compiler that
works much, much better. I believe it is targeted towards ASICs however.


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 14137
Subject: Re: Xilinx Bitstream
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Jan 1999 03:49:46 -0500
Links: << >>  << T >>  << A >>
Kang YI wrote:
> 
> Hello,
> 
> Is there anyone who know the Xilinx Bitstream file format ?
> I'm going to write a program that downloads the *.bit file from XACT tool to
> Xilinx FPGA chip.
> 
> Thank you in advance.
> 
> Kang YI.

Here is a format description that I wrote by reverse engineering bit
files produced for loading a single chip. The chip is an XC4013XL, but I
don't think that matters. I have not verified this against any other bit
files. 

*******************************************************************
Xilinx bit file format for a single chip:

Configuration info?: 16 bit count of bytes, N-1 bytes of data, followed
by a null byte

Chip count?: 16 bit count of chips to be loaded by this file,

File name: Character 'a', 16 bit count of bytes, N-1 characters followed
by a null byte,

Device type and package: Character 'b', 16 bit count of bytes, N-1
characters followed by a null byte, 

File date: Character 'c', 16 bit count of bytes, N-1 characters followed
by a null byte,

File time: Character 'd', 16 bit count of bytes, N-1 characters followed
by a null byte,

Bit stream data: Character 'e', 32 bit count of bytes, N bytes of bit
stream data. 
*******************************************************************

I am guessing at the purpose of some of the fields. For a simple
approach, many people just scan the file for the byte X"F2". This is the
first byte to be sent to the chip. 

Here is a description, in english, of how to load the bits into the
chip. This was from Philip Freidin in this newsgroup, I believe. 

*******************************************************************
The string of '1' bits before the '0010' can be as long as you like.

You can add '1' bits after the 4 bit CRC field at the end of each frame,
and before the '0' at the start of the next frame.

You can add '1' bits at the end of the bit stream.

When you add these '1' bits, you need to adjust the length count field
to
account for the extra bits (except for the extra ones at the end, if
any).

>I am programming 3 XC4000 fpgas all configured as slaves from a
>microprocessor serial port.  If the number of leading ones (the ones in the
>fill byte) are indeed important, I should mabey gate the serial port
>generated clock?

The number of bits sent ('1' or '0') is very important. The FPGAs are
counting rising edges on CCLK, from the time INIT goes high, and will
match it against the 24 bit length count that will follow the '0010' at
the begining of your bitstream. Since the rising edge of INIT is
ASYNCHRONOUS to your system (no, you CAN'T change this), you must NOT
have a free running CCLK.

The correct way to do this is:

Set CCLK LOW
Set Program LOW
Wait a few microseconds
Set Program HIGH
Wait till INIT goes high
Wait at least 6uS
Start generating CCLK Cycles, changing your data on the falling edge,
   so that the data has a nice long setup and hold time to the rising
edge
   of CCLK
*******************************************************************

I have not written code to this description, so I can't vouch for its
correctness. 

I would hazzard a guess that everytime a newbie has to write code to do
this, he has to reinvent the wheel. I don't believe Xilinx provides any
code written in a HLL, only 8051 ASM. Anyone out there have some C code
they would like to contribute to the cause? Although the algorithm is
not complex, it is not easy to glean from the data book description. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 14138
Subject: Re: DFF/Couter behavior with clock and control signals change
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 15 Jan 1999 03:52:55 -0500
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> If you do not violate the setup and hold times for the particular inputs to the
> flip-flop, it will behave as intended.  If you do violate either, the operation
> can be unpredictable which means it may land in either stable state or in a
> metastable state.  Picture the metastable state as a coin that has landed on
> it's edge when flipped.  Eventually a disturbance will move the ff out of the
> metastable state to one of the two stable states.  The time required to reach a
> stable state is indeterminant (it is a probability function).


Metastability? I don't think I have ever heard of that!    ;^)


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 14139
Subject: Re: HEX file format
From: Lasse Langwadt Christensen <fuz@kom.auc.dk>
Date: Fri, 15 Jan 1999 11:18:13 GMT
Links: << >>  << T >>  << A >>
Kang YI wrote:
> 
> Hello,
> 
> I'll appreciate if you let me know the Intel HEX file format.
> 
> Thank you.
> 
> Kang YI.

try this: 

http://www.8052.com/tutintel.htm

 
--Lasse                 
--___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_----
Lasse Langwadt Christensen, MSEE (to be in 1999) 
Aalborg University, Department of communication tech.    
Applied Signal Processing and Implementation (ASPI)      
http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.org
Article: 14140
Subject: General FPGA introduction needed
From: "Jim King" <j_e_king@snotmail.com>
Date: Fri, 15 Jan 1999 11:46:57 -0000
Links: << >>  << T >>  << A >>
Hi,
One of our staff here is looking for a general introduction to FPGAs.
Preferably something that is not too vendor specific, but gives an idea of
how they work, how they are used, etc.
Can anybody suggest books, or URLs of useful material.

Cheers

Jim King
Defence Evaluation and Research Agency
Defford
Worcestershire
WR8 9DU
UK


Article: 14141
Subject: Re: System reset
From: thor@sm.luth.se.NoSpam (Jonas Thor)
Date: Fri, 15 Jan 1999 12:37:01 GMT
Links: << >>  << T >>  << A >>
On Thu, 14 Jan 1999 01:06:46 +0700, "Phichai Liangtong"
<phichai@loxinfo.co.th> wrote:

>I designed a microprocessor and it finished.
>I test it by connect interface to computer (use PC as
>a I/O and memory) and it work but it has some problem.
>when it running (my microprocessor), the system will
>reset itself (FPGA) and the program is re-run from startup
>again. This reset signal didn't occur by my reset signal
>and this signal occur sometime.
>
>I don't understand and how to solve it.

I am no expert at this, but I guess someone will correct me if I am
wrong :) 

The problem migth be realted to asynch reset and noise. If the PCB is
sensitive to noise that might trigger the asynch reset. For example if
you have routed the GSR in a Xilinx device to a FPGA pin then you
should make sure that the PCB is properly designed so you don't get
spikes on that pin. Using a synch reset would solve most of those
problems, but not all... since that there is always the possibilty
that the spike occurs during the FFs setup time. If you haven't
already done it, try to synch any asynch reset to the FPGA clock or in
the worst case lowpass filter the reset.

Another possibility is that you have local asynch resets inside your
FPGA. Any glitch on this local reset will reset FFs.

/ Jonas Thor


 

Article: 14142
Subject: Re: FPGAs in die form
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 15 Jan 1999 07:43:52 -0500
Links: << >>  << T >>  << A >>
hi,

i remember that chip supply was working with xilinx parts and their www
site "line card" currently lists themselves as an authorized processor for
xilinx.  actel is also again selling bare die, according to their
marketeers.  chipx will sell bare die also.  haven't looked at any of the
other vendors.

one thing to remember is that you may have to bias the substrate and where
you connect it varies from chip to chip.

rk

=============================================

Arrigo Benedetti wrote:

> Dear all,
>
> we are undertaking a new project involving the 3D stacking of several
> FPGAs, memories and a CMOS image sensor to form a very compact system
> for real-time image acquisition and processing. We have been trying
> to get Xilinx FPGAs in die form but since new Xilinx devices (Virtex,
> XV) are not currently available as individual dies, we are looking for
> other FPGA vendors.
>
> Any suggestions?
>
> thanks in advance,
>
> -Arrigo
> --
> Arrigo Benedetti          o         e-mail: arrigo@vision.caltech.edu
> Caltech, MS 136-93       < >                    phone: (626) 395-3695
> Pasadena, CA 91125       / \                    fax:   (626) 795-8649



Article: 14143
Subject: AT40K popularity and available tools...
From: "denis lachapelle" <sysacom@cam.org>
Date: Fri, 15 Jan 1999 07:59:38 -0500
Links: << >>  << T >>  << A >>
Is there many poeple using the AT40K family ?
Which tools do you use?

Thank you,


Denis Lachapelle, sysacom@cam.org
Sysacom R&D plus inc.
www.cam.org/~sysacom
tel 450 585-6396, fax 450 582-3231


Article: 14144
Subject: Crosstalking
From: "John" <godzilla_67@hotmail.com>
Date: Fri, 15 Jan 1999 14:24:27 +0100
Links: << >>  << T >>  << A >>
When dealing with signaltransmission, one often encounter issues like
crosstalking,  reflection, ... to just name a few. What about crosstalking
inside the FPGA. Does that ever occur? If not , why is that?


Article: 14145
Subject: Re: FPGA/core PCI interface system
From: sam@palmnet.net
Date: Fri, 15 Jan 1999 13:36:41 GMT
Links: << >>  << T >>  << A >>
QuickLogic and Lucent have FPGAs with embedded PCI I/F's.  So?

In article <369E8999.BB154B52@vcc.com>,
  jas@vcc.com wrote:
> This is a multi-part message in MIME format.
> --------------89B355A54984C401737CC5E9
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> FYI
>
> The cost of developing an FPGA/core PCI interface system just got a lot
> cheaper.
> PLD Consulting Editor Murray Disman gives the scoop on a two team
> approach in
> which two companies provide a populated board and netlist for a PCI
> target for
> just $695. Compare that to $8,000 for a PCI core. Wow. But there's a
> catch.
>
http://www.edtn.com/shared/redirect?url=http://www.edtn.com/pld/pldp.htm&source_
code=26
>
> --
>
> Best Regards,
> John Schewel, VP Marketing & Sales
> Virtual Computer Corp.
> http://www.vcc.com
> --------------89B355A54984C401737CC5E9
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> n:              Schewel;John
> org:            Virtual Computer Corporation
> adr:            6925 Canby Ave. #103;;;Reseda;CA;91335;USA
> email;internet: jas@vcc.com
> title:          VP Marketing & Sales
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>

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Article: 14146
Subject: Re: FPGA/core PCI interface system
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 15 Jan 1999 14:39:29 GMT
Links: << >>  << T >>  << A >>
> The cost of developing an FPGA/core PCI interface system just got a lot
> cheaper.  
> PLD Consulting Editor Murray Disman gives the scoop on a two team
> approach in 
> which two companies provide a populated board and netlist for a PCI
> target for 
> just $695. Compare that to $8,000 for a PCI core. Wow. But there's a
> catch.
>
http://www.edtn.com/shared/redirect?url=http://www.edtn.com/pld/pldp.htm&sou
rce_code=26

You forgot to mention this little 'tidbit', which is probably what you mean
by 'there's a catch':

"The user is free to use the core to develop their system, but must
negotiate the purchase of the core if the system goes into production. "

What's that going to cost?

Austin Franklin
austin@darkroom.com

Article: 14147
Subject: Re: General FPGA introduction needed
From: Ray Andraka <randraka@ids.net>
Date: Fri, 15 Jan 1999 09:44:20 -0500
Links: << >>  << T >>  << A >>
Try http://www.optimagic.com, I think Steven put quite a bit of introductory
material there.  I also have a brief (one page) dixcussion of what an FPGA is
on my site.  The URL to that page is:
http://users.ids.net/~randraka/whatisan.htm

Jim King wrote:

> Hi,
> One of our staff here is looking for a general introduction to FPGAs.
> Preferably something that is not too vendor specific, but gives an idea of
> how they work, how they are used, etc.
> Can anybody suggest books, or URLs of useful material.
>
> Cheers
>
> Jim King
> Defence Evaluation and Research Agency
> Defford
> Worcestershire
> WR8 9DU
> UK



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14148
Subject: Re: AHDL VS. VHDL
From: Jamie Lokier <spamfilter.dec1998@tantalophile.demon.co.uk>
Date: 15 Jan 1999 16:35:39 +0000
Links: << >>  << T >>  << A >>
This is interesting, as I know someone who switch from _V_HDL to _A_HDL
because he found VHDL too difficult to work with, and AHDL much more
straightforward.

His AHDL code contains a fair amount of asynchronous stuff, crossing clock
domains, tight timing etc.  (I know, I work with his code).  So it can
be done.

I don't know much about either language (except I have had to read and
understand some AHDL), but it does appear that with VHDL, you are
relying to some extent on the compiler knowing what you mean by various
constructs.  See other threads in this very newsgroup for "how do I
generate XXX flip-flop" questions.

-- Jamie

Brett George writes:
> do you want me to answer all three queries?
> Anyway, thought you might be interested to know that I have performed
> one design using AHDL/graphical logic. And found AHDL very difficult
> to use when trying to do things more complicated than can be visualised
> in terms of gates. Things like asyncronous state-machines had to be
> re-designed
> in terms of edge triggered FFs etc.
>     We will be making the move to VHDL shortly, for the next design and
> expect
> much better results. It seems to be a lot more flexible, as it is an
> actual language,
> rather than a text based logic system.

> Will let you know how it went in a few weeks if you are still interested.

> Brett.

> aweas wrote:

>> Hi
>> I think a lot of poeple made the transfer from altera's ahdl to vhdl.
>> those how did it , can you please give me some feed back about the
>> results.
>> and info about the transfer to VHDL .
>> I'll be happy to get as much answer's as possible
>> 
>> thank you
>> Aweas



Article: 14149
Subject: The development of a free FPGA synthesis tool
From: Jamie Lokier <spamfilter.jan1999@tantalophile.demon.co.uk>
Date: 15 Jan 1999 17:18:18 +0000
Links: << >>  << T >>  << A >>
I am interested in exploring FPGA fitting & optimisation strategies, for
real FPGAs.  If I develop anything interesting, I will be wanting to
produce a _free_ (GPL) FPGA synthesis tool.  So proprietary information
is not useful if it requires a NDA.

Has anyone published much of reverse engineered formats for the popular
FPGAs?  (Xilinx, Altera, Lucent etc.)

Or for that matter, do any of the popular FPGA vendors supply their
information freely?  I know that there is a lot to be inferred from data
sheets, which is why I think it is only a small step to infer the
detailed programming information.

I am also interested in the less popular vendors, if they are friendly
to the idea of a free synthesis tool.  I will certainly provide
preferential support for helpful vendors.

BTW, the Xilinx 6000 series is not really what I have in mind.  I'm
thinking of more "butch" chips like Altera 10KE100-1s and Xilinx 40125s
(I forget the letters), and the new generation of big chips from these
vendors.

If necessary, I am sure it is not hard to reverse engineer these things
by pushing a lot of well chosen examples through vendor's tools.
There's the complication that access to the vendor's tools is usually
restricted in various ways, so I will need volunteers to compile and
analyse some test programs using their software.

However, I'd really rather find that someone has done the reverse
engineering already.

Summary:

  Project goal: To develop a program which (1) translates logic circuits (as
                netlists or equation lists) to FPGA bitmaps, subject to
                timing constraints; (2) can be targetted at many
                different FPGA and FPGA-like architectures; (3) analyses
                bitmaps to recover timing information; (4) can do
                simulation of compiled bitmaps, not necessarily quickly,
                but accurately.

  _Not_ a goal: Higher level languages for describing circuits are not
                part of the scope of this project.  Of course,
                interoperability with other tools, especially those with
                open development models, is important.  And being free
                software, others will be able to use and modify the
                synthesis tool as they require.

  Long term:    To support vendors who openly publish specs.  Reverse
                engineering is only required as an interim solution,
                as the most readily available quality devices are
                (I believe) currently supplied by uncooperative vendors.

  Questions:

  - Any of the big, fast & popular chips have public specs?
  - Anyone published reversed engineered specs?
  - Any FPGA vendors interested in supporting development of a free,
    retargettable synthesis tool?  (Development style similar to GCC/EGCS).
  - Anyone willing to run a bunch of compiles & simulations from time to
    time, and return the results of analysing the output to me?
  - Anyone interested in collaborating on a free FPGA synthesis tool?
      -- Willing to run compiles & simulations from time to time using
         your FPGA vendor's tools, and send me the results.
      -- Willing and able to write logic optimisation & synthesis code.
         Retargettable synthesis code is especially interesting.
      -- Have other stuff to contribute.
      -- Have already written the equivalent of GCC for FPGAs? :-)
  - Anyone able to offer legal advice on reverse engineering issues?
  - Is there any demand for this sort of tool?

The success and timescale will depend on the quality and quantity of
contributions from volunteers.

Sincerely,
-- Jamie


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