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Messages from 13000

Article: 13000
Subject: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
From: Bill Pringlemeir <bpringlemeir@yahoo.com>
Date: Tue, 10 Nov 1998 15:06:01 GMT
Links: << >>  << T >>  << A >>
This is an excellent example.  Currently we have a line of products.  Some
of the logic is very similar between devices; others (the screen drivers)
are not.  We have an ASIC for one and a XILINX hard wire device for another.

If you had an integrated ASIC/FPGA it may have been more appropriate.  This 
would be a cost situation.  The reason we went with hard wire was the NRE.

Also, as several people pointed out being able to update FIR, IIR, state
machine code etc is an advantage.

Bill

>>>>> "null" == null  <null@I.Hate.Spam> writes:

    null> Considering that many uC applications end up using
    null> programmible logic 'glue' to interface the CPU to whatever
    null> it's supposed to be controlling, a combination CPU/FPGA
    null> would seem ideal for a wide variety of embedded controllers.

-- 
Noah's unknown brother - Made arc full of aquariums
Article: 13001
Subject: Re: free Xilinx developer tools
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 10 Nov 1998 07:06:34 -0800
Links: << >>  << T >>  << A >>
I'm not sure if you can find free Xilinx tools but there are some low-cost
tools (< $100).  You can find free or low-cost versions of most FPGA vendors
tools on The Programmable Logic Jump Station at
http://www.optimagic.com/lowcost.html.

Another good way to get the Xilinx tools is through the Xilinx Student
Edition book available on-line at http://www.optimagic.com/books.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

F. Arnold wrote in message <7297tr$ds$1@goliat.eik.bme.hu>...
>Hi!
>
>Where or how can i get a free developer tools for
>xilinx fgpa.
>(I tried protel98 trial, but doesn't works)
>
>Thanks
>Arnold
>
>


Article: 13002
Subject: hard macros design flow for XILINX Foundation Express
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Tue, 10 Nov 1998 16:26:12 +0100
Links: << >>  << T >>  << A >>
Hello,
we want to use hard macros (prorouted) with XILINX 
Foundation and Synopsys FPGA-Express (or XILINX Alliance
and Synopsys FPGA-Compiler).
As far we have searched it seemas to be hard to intergrate this
into a reasonable design flow.
Details:
Assume I have already defined and routed a macro (with EPIC).
I want to declare it as a component in VHDL and integrate 
it in the design flow. Therefore I have to run 
VHDL-Express, NGDBUILD and MAP with one undefined 
component. Of course for VHDL-Express this is no problem
because this is the same as using LogiBlox components.
But how do I pass NGDBUILD and MAP?
(The rest of the design flow is clear:
load unplaced/unrouted design into epic, add the macro,
connect it, save it from EPIC go through PAR - done)
I have to make sure that the signals/logic connected to 
my macro do not get optimized away. 
In the moment I have only two ideas: 
A) define some crazy component with flip-flops at the boundaries,
protect them by dont-touch through Synopsys (possible at least with FPGA
compiler), hope that the flip-flops are enough for XILINX tools to not
fuzz around with it and remove this in EPIC.
Problem: dirty solution, apears as a lot of hacking is necessary.
B) create the complete netlist/components for the macro 
   and procede as in A, maybe then one does not really 
   use EPIC but uses the knowledge of the placement of the
   individual CLBS and the routing between them for constraints.
   I am afraid that this is very slow. 
Andreas
-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                 
                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
                        http://www.iti.mu-luebeck.de/~doering/
----------------------------------------------------------------
Article: 13003
Subject: Affordable boundary scan (JTAG) interconnect testing software any
From: Edward Wallington <edward@crsltd.com>
Date: Tue, 10 Nov 1998 16:18:46 -0000
Links: << >>  << T >>  << A >>
Hi,

apologies if this is slightly off subject, but I figured we must all
have to do something about testing:

Has anybody found any affordable(?) JTAG interconnect testing software?
The likes of JTAG technologies, Asset intertech, and Goepel seem to be
charging about =A315 - =A320k +  for a suite of test vector generation =
and
execution software. Goepel did have a budget system, but it had
something like a 900 node limit (which I exceed).

The board I am trying to test has a couple of larger Altera 10k =
devices,
two '6201 DSPs, some Lattice ispLSI 5k and a lot of memory (it is a
specialized graphics system). This is mostly BGA, so JTAG seems to be
the only logical choice.

We are a small company producing equipment in low volume for medical
research. It seems that nobody has a marketing strategy that covers us
(low budget!). I figured there must be lots of other companies in a
similar position wanting to use JTAG but can't afford to?

Comments anyone?

Edward Wallington,

Cambridge Research Systems Ltd.,

www.crsltd.com



Article: 13004
Subject: Problem with the ABEL to Macro convertion in XILINX FB1.3
From: this_address_is_invalid_see_signature@hotmail.com (Jaroslaw Cichorski Jr.)
Date: Tue, 10 Nov 1998 16:54:26 GMT
Links: << >>  << T >>  << A >>
Hi,
I have following Problem with the HDL in Foundation 1.3.
After I define ABEL code and try to convert it to Macro, the
abl2edif.exe (called from HDL) reports following Error:

quote
Errors report not available
Use Synthesis/View Report for detailed synthesis report
/quote

And in 'Synthesis/View Report' reports:

quote
#Created by S95_SYN 2.60.0.39 
CNTRES.ABL: abl2edif.exe  -a XC9500 -o cntres.EDN -s mod  cntres.ABL
CNTRES.ABL: Errors
/quote

The same problem occurs with the example projects.
There is no information in this report, how to solve this problem.

If you had the same problems or know any solution - please let me know
- I have found nothing about it on XILINX site)

TIA - this is unfortunately urgent


--------
Jaroslaw Cichorski Jr.
E-mail cichy@amart.JUNKMAILPROTECTION.com.pl
WWW http://www.amart.com.pl
E-mail address is invalid due to stop junk mail.
Please r_e_m_o_v_e JUNK MAIL PROTECTION.
This message was not tested on animals.
Article: 13005
Subject: free Xilinx developer tools
From: "F. Arnold" <arno@freemail.c3.hu>
Date: Tue, 10 Nov 1998 12:28:06 -0800
Links: << >>  << T >>  << A >>
Hi!

Where or how can i get a free developer tools for
xilinx fgpa.
(I tried protel98 trial, but doesn't works)

Thanks
Arnold


Article: 13006
Subject: Re: placement&routing problems
From: Edward Moore <edmoore@edmoore.demon.co.uk>
Date: Tue, 10 Nov 1998 21:13:03 +0000
Links: << >>  << T >>  << A >>
In article <36478D21.5026AE41@ids.net>, Ray Andraka
<no_spam_randraka@ids.net> writes
>Use the floorplanner.  The RAM should be a regular structure, but the M1
>PAR is not smart enough to do it well.  The floorplanner is a bit
>painful to use for synthesized designs, but it is still better than
>nothing.  This is a case where a schematic entry would have been a
>better entry method, as it would have allowed you to easily build the
>structure hierarchically, complete with relative placement.
>
>Utku Ozcan wrote:
>
>> Design entry: Verilog-XL.
>> Synthesis: Synplify 5.0.7
>> Placement&Routing: Design Manager 1.5
>>
>> etc, etc..
>
>--
>-Ray Andraka, P.E.
>President, the Andraka Consulting Group, Inc.
>401/884-7930     Fax 401/884-7950
>email randraka@ids.net
>http://users.ids.net/~randraka
>
>

A few of points:

1. One of the improvements to Par/v1.5 is that ram blocks are recognised
as such, and are supposedly placed in a sensible manner. This should
remove the need for RLOC'ing.

2. It sounds like Xilinx have suggested the -ir map option to get round
some mapping bug's in version 1.5. However, if the -ir option is used
relative placement information is lost, so RLOC'ing wouldn't get you
anywhere.  I suggest getting the M1.5 service pack anyway.

3. If the clb's with rams are intended to also have flip-flops, it might
be worth while checking in EPIC that they are both going in the same
clb.

4. Contrary to popular belief, structured hierarchical relative
placement is possible with VHDL too. In fact it's easier and quicker.

-- 
Edward Moore
Hardware Engineer
Snell & Willcox Ltd
Ed.Moore@snellwillcox.com
Article: 13007
Subject: Re: How to determine macro size in Xilinx Foundation?
From: Edward Moore <edmoore@edmoore.demon.co.uk>
Date: Tue, 10 Nov 1998 21:18:13 +0000
Links: << >>  << T >>  << A >>
In article <36439884.109ACC0C@home.com>, JOHN KENNEDY
<johnkennedy@home.com> writes
>What is the best way to determine the post optimization CLB count for
>the macros I am generating in VHDL and the State Machine editor?  I
>realize that these macros are packed with with other logic to share
>CLBs, but is there a way to estimate the size of the individual macros
>using Xilinx foundation 1.5
>
>Thanks

Are these macros RLOC'd ?. If so, as long as you don't use the -ir
option MAP lists the CLB counts for each huset block at the end of the
.mrp report file.

-- 
Edward Moore
Snell & Willcox Ltd
Ed.Moore@snellwillcox.com
Article: 13008
Subject: Power Consumption
From: Stephen Swearingen <sasweari@orbitworld.net>
Date: Tue, 10 Nov 1998 16:16:57 -0600
Links: << >>  << T >>  << A >>
Can anyone provide unbiased, independent research data which compares
power consumption of different FPGA families (Altera and Xilinx must be
included)?  No FPGA vendor provided data please.  Hopefully there's some
test group that does such things.

Thanks in advance,

Stephen Swearingen

ICS Triplex
Houston, TX
281-647-4348
swearingen@icshou.com


Article: 13009
Subject: CCLK on Spartan
From: Stephen Swearingen <sasweari@orbitworld.net>
Date: Tue, 10 Nov 1998 16:31:35 -0600
Links: << >>  << T >>  << A >>
Hello all,

I have a daughter card that is serially configured through an optic link
from the main board.  Only one clk and one data go to the daughter board
from the main board.  The intent is to use the clk initially for CCLK
and then after configuration as the system clock.  The clk rate is SLOW
(6 MHz).  So this one signal goes into CCLK and a global clock buffer
pin.  Is this ok?  Will having a clk on CCLK after config affect the
device?  Will it increase power consumption?  I know I could use a
single AND gate and HDC to gate off the signal (or something like that)
but I really don't like that.  The only use of CCLK after config (to my
knowledge) is as an input for readback (if enabled).  I won't be using
the readback feature.

Thanks in advance,

Stephen Swearingen
Sr. Hardware Engineer
ICS Triplex
281-647-4348
swearingen@icshou.com

Article: 13010
Subject: Make your own Printed Circuit Boards. Press-n-Peel in Europe
From: ward@cibs.demon.co.uk (David Ward)
Date: Wed, 11 Nov 1998 00:00:37 GMT
Links: << >>  << T >>  << A >>
Make your own Printed Circuit Boards.  Press-n-Peel in Europe

Laser toner transfer system.  Press-n-Peel Blue.  Please visit my
website at www.cibs.co.uk/etch/x7.html for more details.
Article: 13011
Subject: Re: CCLK on Spartan
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 11 Nov 1998 03:21:53 GMT
Links: << >>  << T >>  << A >>
In article <3648BEC7.CA7DF7B7@orbitworld.net> Stephen Swearingen <sasweari@orbitworld.net> writes:
>I have a daughter card that is serially configured through an optic link
>from the main board.  Only one clk and one data go to the daughter board
>from the main board.  The intent is to use the clk initially for CCLK
>and then after configuration as the system clock.  The clk rate is SLOW
>(6 MHz).  So this one signal goes into CCLK and a global clock buffer
>pin.  Is this ok? 

Yes.

> Will having a clk on CCLK after config affect the
>device?

No.

> Will it increase power consumption? 

By less than 10uA, the leakage load of having CCLK on the net.

> I know I could use a
>single AND gate and HDC to gate off the signal (or something like that)
>but I really don't like that.

Not needed.

> The only use of CCLK after config (to my
>knowledge) is as an input for readback (if enabled).  I won't be using
>the readback feature.
>Thanks in advance,
>Stephen Swearingen


Philip Freidin


Article: 13012
Subject: connecting 2 FPGA together
From: cpegfa@uxmail.ust.hk (Leprechaun)
Date: 11 Nov 1998 03:25:34 GMT
Links: << >>  << T >>  << A >>

Hi all,
Recently I am working on a circuit which require 2 Xilinx XC4028XL-1-PG299
communication to the same DSP on the same bus. One of the chips is for 
outputting to DSP while the other is for inputting from DSP. To prevent
crosstalk between the 2 xilinx, I used tristate buffer to control the 
input / output port of the 2 chips.
The problem is as follows : 
After I downloading the circuit to the 2 chips separately (one after the
other, instead of in a daisy chain manner), those input/output pins 
would have a value of 1/0, when I connected the 2 ports on the same bus,
the current goes up 10 times (probably because a '1' pin is connected to 
a '0' pin) and all the pins will have a voltage value around 2 V (0 = 0V,
1 = 3.5V). Then, no matter what I do, it cannot restore to normal state
unless I re-download the circuit.

Did anyone experience similar problem?

Thanks a lot.

Oliver
Article: 13013
Subject: Re: CCLK on Spartan
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Wed, 11 Nov 1998 09:03:44 GMT
Links: << >>  << T >>  << A >>
On Wed, 11 Nov 1998 03:21:53 GMT, fliptron@netcom.com (Philip Freidin)
wrote:
>In article <3648BEC7.CA7DF7B7@orbitworld.net> Stephen Swearingen <sasweari@orbitworld.net> writes:
>>I have a daughter card that is serially configured through an optic link
>>from the main board.  Only one clk and one data go to the daughter board
>>from the main board.  The intent is to use the clk initially for CCLK
>>and then after configuration as the system clock.  The clk rate is SLOW
>>(6 MHz).  So this one signal goes into CCLK and a global clock buffer
>>pin.  Is this ok? 
>
[snip]
>
>> Will it increase power consumption? 
>
>By less than 10uA, the leakage load of having CCLK on the net.

If we assume the data sheet value of 10pF for the pin, and 0pF for
internal nodes, then the extra current drain due to the capacitive
load will be 300uA at 5V, 6MHz.  This is a lot higher than the DC
leakage.

Ok, so it's not much more, but if it was a battery powered system
every little bit counts.

Allan.
Article: 13014
Subject: Re: CCLK on Spartan
From: Mike Randelzhofer <Michael.Randelzhofer@mchf.siemens.de>
Date: Wed, 11 Nov 1998 10:36:22 +0100
Links: << >>  << T >>  << A >>
I have a similar application with 2 spartan devices coupled with a
SPI-opto-interface. Is there any way to get the cclk in the device
(routing to a SGCLK-buffer) without a second connection ?

If there is any pip inside the LCA, how to use it in VHDL ?

Thanks in advance
Mike
Article: 13015
Subject: Example of clock circuit needed !
From: "ovilup" <ovilup@hotmail.com>
Date: 11 Nov 1998 13:35:37 GMT
Links: << >>  << T >>  << A >>
Hello !

I am working on an I2C controller. Now, I am designing the
internal clock generator. I have an 1.5 MHz internal clock,
from which I have to generate the 100 KHz, 90 KHz, 44 KHz
1.5 KHz SCL clocks. 

Any examples of such an clock generator would be appreciated !

Thank you in advance.
OL
Article: 13016
Subject: Re: FPGA VGA interface
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 11 Nov 1998 09:13:13 -0500
Links: << >>  << T >>  << A >>
There are other boards out there as well.  For example, you might look at
Visicom's Vigravision card which has an S3 chip, ADC, an FPGA and frame
memory on it.

Roman Pollak wrote:

> Take a look at http://www.xess.com/FPGA/homepage.html.
> They have a board with fpga same ram anf vga connector as well as source
> for the programming as a vga controler.
>
>
> > >Hi,
> > >Can you be more specific? VGA? it is an analog system, do you want a
> > graphic
> > >card system? Or do you want a fully compatible VGA system controller
> > with
> > all of
> > >it's registers and parameters?
> >
> > What I hope to be able to do is generate VGA color signals with a
> > Xilinx
> > FPGA so that I can directly drive a VGA monitor. I also want to be
> > able to
> > add an interface for a mouse so that the Xilinx chip can display the
> > mouse
> > pointer on the monitor. I will probably need some D/A converters in
> > order to
> > generate the analog signals for the VGA monitor, but I'm not quite
> > sure
> > where to start.
> >
> > -EKC



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13017
Subject: Looking for a good documentation on FPGA
From: "ovilup" <ovilup@hotmail.com>
Date: 11 Nov 1998 16:51:50 GMT
Links: << >>  << T >>  << A >>
Dear all,

I am looking for a good documentation on programming FPGA's and
ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn
more about FPGA's and ASIC's. 

Thank you. 

Article: 13018
Subject: Test - please ignore!
From: "johnd" <djon@dragoncon.net>
Date: 11 Nov 1998 13:08:42 -0500
Links: << >>  << T >>  << A >>
Told you!

Get free web based email and newsgroup sending from 
http://www.dragoncon.net
Article: 13019
Subject: Re: hard macros design flow for XILINX Foundation Express
From: Todd Kline <todd@wgate.com>
Date: Wed, 11 Nov 1998 18:11:16 GMT
Links: << >>  << T >>  << A >>


Andreas Doering wrote:

> Hello,
> we want to use hard macros (prorouted) with XILINX
> Foundation and Synopsys FPGA-Express (or XILINX Alliance
> and Synopsys FPGA-Compiler).

Could you use an unrouted xnf of your "hard-wired" macro to
pass the map stage then use the pre-wired macro as a guide
file to P&R?

I had to give up guide files when I moved to VHDL, so I'm
not even certain if this path will work.

Todd

Article: 13020
Subject: Test - please ignore!
From: "johnd" <djon@dragoncon.net>
Date: 11 Nov 1998 13:12:01 -0500
Links: << >>  << T >>  << A >>
Told you!

Get free web based email and newsgroup sending from 
http://www.dragoncon.net
Article: 13021
Subject: Test - Ignore2
From: John Davis <nad1@zdnetmail.com>
Date: Wed, 11 Nov 1998 13:15:30 -0500
Links: << >>  << T >>  << A >>
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Ignore222
<br>&nbsp;</html>

Article: 13022
Subject: Test - Ignore
From: johnd1489@my-dejanews.com
Date: Wed, 11 Nov 1998 18:17:08 GMT
Links: << >>  << T >>  << A >>
As I told You - Ignore!

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 13023
Subject: Re: connecting 2 FPGA together
From: Todd Kline <todd@wgate.com>
Date: Wed, 11 Nov 1998 18:23:57 GMT
Links: << >>  << T >>  << A >>


Leprechaun wrote:

> Hi all,
> Recently I am working on a circuit which require 2 Xilinx XC4028XL-1-PG299
> communication to the same DSP on the same bus. One of the chips is for
> outputting to DSP while the other is for inputting from DSP. To prevent
> crosstalk between the 2 xilinx, I used tristate buffer to control the
> input / output port of the 2 chips.
> The problem is as follows :
> After I downloading the circuit to the 2 chips separately (one after the
> other, instead of in a daisy chain manner), those input/output pins
> would have a value of 1/0, when I connected the 2 ports on the same bus,
> the current goes up 10 times (probably because a '1' pin is connected to
> a '0' pin) and all the pins will have a voltage value around 2 V (0 = 0V,
> 1 = 3.5V). Then, no matter what I do, it cannot restore to normal state
> unless I re-download the circuit.
>
> Did anyone experience similar problem?
>
> Thanks a lot.
>
> Oliver

1) Are the tri-state buffers external to the FPGAs or internal?
2) Can both FPGAs drive the bus or just one FPGA and the DSP?

Before programming, all user I/Os are tri-stated.  After programming
the I/Os are user defined.  You almost certainly have multiple active
drivers on the bus driving different values.  Double check your tri-state
control logic.  If the tri-states are internal, make sure that tri-state
buffers are actually being inserted.

Todd

Article: 13024
Subject: FS: XC3142A5PC84C
From: michael@webuyparts.com
Date: Wed, 11 Nov 1998 19:50:28 GMT
Links: << >>  << T >>  << A >>
We have stock in house of recently discontinued Xilinx part
number XC3142A5PC84C.  Please contact us for details.

Electronic Components Company
http://www.webuyparts.com
Ph: 949-493-7603
Fx: 949-493-6273

-----------== Posted via Deja News, The Discussion Network ==----------
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