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Messages from 14200

Article: 14200
Subject: Re: Ratings for Synplicity Synplify
From: crm182c@nortelnetworks.com (Hing-Fai Lee)
Date: 19 Jan 1999 14:18:05 -0500
Links: << >>  << T >>  << A >>
I used synplicity on a Xilinx 40150. The versions I used were:
5.0.6, 5.0.7 and 5.0.8. Before getting to know synplicity, I
used Synopsys's FPGA Compilor on a Xilinx 4036. All works were
done on SUN workstations. Here is a summary of problems that
I have seen:

1. Crashing the WS from 5.0.6 to 5.0.7 when browsing the design
under technology view. 5.0.8 seemed to fix the problem although
there exist a Solaris patch to fix the a video card bug.

2. Running out of memory on 5.0.7. There is a memory leakage
problem that eats up all 1Gbytes of RAM in our Ultra. 5.0.8
fixed this problem.

3. Doing mapping forever on 5.0.6. The design ran for 20 hours
and still not done! 5.0.8 fixed this problem.

4. Misleading CLB usage count. In the beginning, I used the stats
reported in the .srr file to estimate how big the device would be.
Big mistake, as a lot of CLBs are used as route through and
the final size is 20% bigger (roughly).

5. Timing estimation is way off. At one time, we have hundreds
of timing violation from par. The par figure reported was like
19 nanosecong worst than that estimated by synplicity. Overall
synplicity's estimate is always too optimistic.

These are the worst problem that I have. There are many more. On the
plus side, the compile speed is very high compare to the FPGA
compiler. On the 4036 design, it was like 180 seconds vs 3.5 hours.
As well, the support is excellent. Every call is answered very
quickly with work around that works. The tool has improved a lot
since the beginning but is still being developed. At the end,
we decided to stay with synplicity inspite of its many problems.

Good luck, Hing-Fai 

Nortel Networks
Dept 1D13, Mail Stop 162   Phone: 613-765-2097
P.O. Box 3511, Station C   FAX  : 613-763-1327
Ottawa, Canada, K1Y 4H7    Email: crm182c@nortelnetworks.com
Article: 14201
Subject: ASIC/FPGA Designers Available
From: "Andrew Bunsick" <abunsick@designpr.com>
Date: Tue, 19 Jan 1999 15:09:09 -0500
Links: << >>  << T >>  << A >>
***************  DesignPRO Inc.  ******************

Does your company have programs that are being delayed
due to a shortage of skilled ASIC/FPGA Design Engineers?

                    Maybe we can help!

DesignPRO is an engineering design organization, located in Ottawa,
Canada, specializing in telecom solutions in silicon.  Our specialty is ASIC
and FPGA development and we provide a full turnkey service using industry
leading design tools that incorporate support for multiple vendors.  We
offer a full spectrum of product development services, including system
design, chip and board specification, ASIC and FPGA design and verification,
DSP coding, firmware and software development, and hardware and software
integration testing.  We have significant experience throughout the network,
including:

- Transport (ATM and PPP over SONET/SDH with UTOPIA interfaces - OC-1,
  OC-3, OC-12 & OC-48c);
- Access devices (xDSL Serial ATM Mux (Utopia & PCI Interfaces), cable
  modems); and
- Wireless technologies (GPS, CDMA, LMDS, PCS).

We have an extensive library of reusable blocks that provide our customers
with the additional "value added" of cutting time to market, while reducing
the risks associated with new designs.

For additional information about DesignPRO, please visit our website at
www.designpr.com.

We are currently completing the development of 5 FPGAs for a high speed
access product and expect to have 12 design engineers available in the next
several weeks.

We are very interested to explore all opportunities and would welcome
inquiries
at (613) 596-5030, or by email at abunsick@designpr.com.

Thank you for your consideration.

Sincerely,

Andrew Bunsick
General Manager
DesignPRO Inc.


Article: 14202
Subject: Re: Q:Hardware debugging with Xilinx M1.4
From: Ray Andraka <randraka@ids.net>
Date: Tue, 19 Jan 1999 16:59:25 -0500
Links: << >>  << T >>  << A >>
You need to put the readback component in your design and connect it up.  If
you are doing schematic entry, the symbol is called readback.  If you are
using an HDL you need to instantiate the readback macro in the xilinx
library.

As far as the misbehavior of you design goes, first check to make sure the
questionable logic was not trimmed out (look at the trim report-hopefully
your design is hierarchical and you labeled your hierarchy blocks so you can
make some sense of the report).  Assuming that your simulation accurately
portrays the real world signals, the next place to look is at the timing
analysis.  Make sure all paths meet the timing you need to make the design
work.  Normally I do a functional simulation (no timing) till I am satisfied
the logic does what it is supposed to do.  Then I run the place and route
followed by a static timing analysis using the timing analyzer.  If you used
timing constraints, check to make sure all were met.  Also check the report
of paths without timing constraints to make sure you got good coverage.  If
all is in order, check the lists of registers under each time group to make
sure you didn't fall victim to overlapping constraints (sorry, that is
painful but there is currently no better way to do it).

If you pass a complete functional sim, nothing critical is trimmed out and
everything meets timing then the design should work.  If not then it is time
to start looking at power, ground, clock and signal integrity.

Gerd Beil wrote:

> Hi to everyone!
>
> I'm using Xilinx M1.4 (Alliance) on a workstation (HP) and the
> Xchecker-cable for downloading the generated *.bit-file on a XC4010E. My
> problem is that the downloaded design doesn't do what the simulation
> makes me expecting it to do. Some parts of my design are working fine
> what makes me sure that I did the implementation correctly. But some
> parts don't work at all and the report files don't show any
> warnings/errors that seem to be the cause for this problem. I know there
> is a posibility for a hardware debugging but I don't know how to get
> there.
> When implementing the design the check-box "Enable Bitstream
> Verification and In-Circuit Hardware Dedugging" is checked in the XC4000
> Configuraion Options and the Readback Clock is set to CCLK. But when I
> call the Hardware Debugger it tells me that the "design does not have a
> readback block connected". The the xchecker-program run from the command
> line detects a cable "serial-readback". Does this just mean that the
> cable supports readback-mode if the design does too? And what exactly is
> the "Readback Block"? Do I have to add some functions to my design? Or
> do I have just to change some settings for the implementation? What do I
> have to do to run the Hardware Debugger???
>
> Bye,
>
> Gerd



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14203
Subject: help w/ broken xilinx dongle
From: C Kuethe <ckuethe@gpu.srv.ualberta.ca>
Date: 19 Jan 1999 23:06:17 GMT
Links: << >>  << T >>  << A >>
In a dusty old storage closet here, I dug up an XACT XC-DS21 evaluation
kit, complete with demo board and dongle. I installed XACT on an IBM box,
486 w/ 16M ram. Unfortunately, when I try to run the software, I get an
error to the effect of "can't find the key." Xkey reports no valid keys. I
checked the key on other machines and check my bios settings to make sure
that it wasn't the parallel port failing, but no machine found any keys.

Does anyone have any idea on where to go from here?

Be Well,
Chris

-- 
  Chris Kuethe: System Administrator - U of A Math Dept
      http://www.[math.]ualberta.ca/~ckuethe/
pager: 403.917.6448             office: CAB553, x1704	cell: 903.9475
wargames@edmc.net               ckuethe@ualberta.ca
ckuethe@math.ualberta.ca        ckuethe@gecko.math.ualberta.ca

Article: 14204
Subject: I don't trust Orcad
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Tue, 19 Jan 1999 19:14:05 -0800
Links: << >>  << T >>  << A >>
Based on how bad Orcad schematic entry still is after 7.2 generations, I
wouldn't trust anything else they do. (I tried their first VHDL and it
couldn't implement a counter within a testbench - they'd released garbage)

Seems they could get all the schematic features working after all these
years.  It's obvious their designers don't draw schematics.

Everytime I do schematics with Orcad I curse.  They eventually work, but its
a drag.  Cryptic error messages, subtle changes from version to version.
Tweaky performance.

Xilinx tools have their problems too, but why deal with 2 sets of problems
and interface problems to boot. Seems like trusting Orcad is asking for
problems.

Bruce

Pawel Michocki wrote in message ...
>Does anyone use Orcad Express Plus v9.0 ?
>Now I use Orcad Express 7.20 with Xilinx Aliance 1.5, but Orcad won't
>provide
>support for virtex in Express (only in Express Plus). Is it worth to
upgrade
>to Plus
>version or simply buy Foundation from Xilinx ?
>Any other suggestion ?
>
>Regards,
>Pawel Michocki, SIM POLAND
>
>
>PS
>Any satisfied Orcad user ? (not from USA)
>
>


Article: 14205
Subject: Re: The development of a free FPGA synthesis tool
From: d_cary@my-dejanews.com
Date: Wed, 20 Jan 1999 03:17:48 GMT
Links: << >>  << T >>  << A >>
This looks like something a few other "free" projects would be interested in
using and perhaps in contributing towards:

  gEDA: GNU Electronic Design Automation
  http://www.geda.seul.org/

  The Freedom CPU Project
  http://f-cpu.tux.org/
  mailing list:
  http://www.egroups.com/list/f-cpu/
  (wants to build early versions of their CPU out of FPGAs,
  so there is faster turn-around,
  trying out different ideas)

  FreeHDL
  http://www.freehdl.seul.org/
  A project to develop a free, open source VHDL simulator for Linux.

Perhaps you can re-use some work already done on a simulation and timing
estimator:

  Magic - A VLSI Layout System
  http://www.research.digital.com/wrl/projects/magic/magic.html
  comes with "irsim", a circuit simulator and timing estimator.

  Freeware, Shareware, or Academic
  VLSI CAD/CAE Software.
  http://www.mrc.uidaho.edu/cgi-bin/w3-msql/vlsi/CADfree.html

  Alliance: A Complete CAD System for VLSI Design
  http://www-asim.lip6.fr/alliance/
  Alliance source code is released under the GNU General Public License (GPL).

I've heard rumors that someone created a crude tool that translated from
ordinary C code to VHDL (or was it Verilog ?) for his thesis; the idea was to
run certain compute-intensive subroutines *really* fast, blurring the
distinction between hardware and software.

So, now what ?

Jamie Lokier <spamfilter.jan1999@tantalophile.demon.co.uk> enthused:
> I am interested in exploring FPGA fitting & optimisation strategies, for
> real FPGAs.  If I develop anything interesting, I will be wanting to
> produce a _free_ (GPL) FPGA synthesis tool.
...
> Summary:
>
>   Project goal: To develop a program which (1) translates logic circuits (as
>                 netlists or equation lists) to FPGA bitmaps, subject to
>                 timing constraints; (2) can be targetted at many
>                 different FPGA and FPGA-like architectures; (3) analyses
>                 bitmaps to recover timing information; (4) can do
>                 simulation of compiled bitmaps, not necessarily quickly,
>                 but accurately.
>
>   _Not_ a goal: Higher level languages for describing circuits are not
>                 part of the scope of this project.  Of course,
>                 interoperability with other tools, especially those with
>                 open development models, is important.  And being free
>                 software, others will be able to use and modify the
>                 synthesis tool as they require.
...
>       -- Have already written the equivalent of GCC for FPGAs? :-)
...
>   - Is there any demand for this sort of tool?
...
> -- Jamie

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14206
Subject: Re: The development of a free FPGA synthesis tool
From: cyliax@cs.indiana.edu (Ingo Cyliax)
Date: 20 Jan 1999 05:08:08 GMT
Links: << >>  << T >>  << A >>
In article <783hsj$816$1@nnrp1.dejanews.com>,  <d_cary@my-dejanews.com> wrote:
...
>I've heard rumors that someone created a crude tool that translated from
>ordinary C code to VHDL (or was it Verilog ?) for his thesis; the idea was to
>run certain compute-intensive subroutines *really* fast, blurring the
>distinction between hardware and software.

The one I'm aware of is called "nlc" by Christian Iseli. I downloaded a
copy of it way back when he announced it (version 0.8). It spits out 
Viewlogic netlists, so you'll need wir2xnf to munge them into xnf. I
tried to compile it, but it needs a library called LEDA which I wasn't
able to track down. I don't know what happeneded to the author or if there
is a newer version, but the code I have seems to be GPL. I'd be glad to
send out a copy or put it up for ftp, if anyone wants to give it a try.

See ya, -ingo
-- 
/* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 812-333-4854/4852 */
Article: 14207
Subject: VLSI Jobs @ Lucent <NJ>
From: ejob <engineer@ejob.com>
Date: Tue, 19 Jan 1999 23:50:24 -0800
Links: << >>  << T >>  << A >>

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Content-Type: text/plain; charset=iso-8859-1
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VLSI Architect <circuit design and implementation research engineers
(Members of Technical Staff)>

LOCATION:
Murray Hill, NJ

SHORT-TERM EXPECTATIONS: FIRST 90 DAYS

The succesful candidate will be assigned to
1) identify the circuit implement opportunities for optical, wireless,
switching and access communicaitons systems,
2) identify the algorithm implementation opportunties for various
communicaitons systems,
3) identify the design challenges for implementing Gb/s circuits, or
4) identify the opportunity for circuit realization cycle time reduction
in
communication systems

MEDIUM-TERM EXPECTATIONS: 90 DAYS TO ONE YEAR

The successful candidate will, based on the initial studies from the
first 3
months,
1) propose feasible architectures for efficient circuit realization of
various communications functions,
2) generate mathematical models of the various algorithms to compare
peformance and cost of various implementation options
3) provide initial designs of impementing Gb/s circuits on advanced
silicon
processing technologies
4) suggest methodology for cycle time management

The successful candidate will have completed the design projects, and is

expected to continue to identify emerging opportunities of circuit
realization for communication systems

IMPORTANT TASKS THIS PERSON WILL PERFORM ON AN ONGOING BASIS.

1) Identify opportunities for realizing communications functions on
integrated circuits
2) VLSI architecture and high speed circuit design for communication
systems

3) Realization of signal processing algorithms (layer I) on integrated
circuit
4) Realization of communications protocols (layer II and above) on
integrated circuits
5) Cycle time management

IMPORTANT TASKS THIS PERSON WILL PERFORM DAY ONE OF JOINING YOUR
ORGANIZATION.

Identifying and realizing communications functions on integrated
circuits

SKILLS THE SUCCESSFUL CANDIDATE MUST POSSESS IN ORDER TO ACCOMPLISH THE
GOALS OF THE ORGANIZATION?

Skills and Experience
· Candidates should possess expert design skills in one or more of the
following areas together with the knowledge of the technical challenges
facing the industry and, most importantly, a creative ability to lead
research projects that address these challenges.

 Design Skills
· custom circuit design · placement, routing and synthesis
· VHDL design · signal integrity management
· circuit simulation, timing and verification · mixed-signal design
· FPGA design ·

 Design Experience
· high speed digital circuits · application-specific integrated circuit
· co-processor and accelerators · application-specific standard circuit
product
· digital signal processors · design of peripheral, bus, and I/O
· microcontrollers and RISC processors · hardware and software co-design

· analog circuits including filters, analog-to-digital converters,
digital-to-analog converters, trans-impedance amplifiers, and laser
drivers
· VSLI Design For Testability (DFT) techniques
· memory and DMA

 Architecture and System Design Experience
· integrated circuit for communication systems, including optical
network,
wireless, switching, and access · realization of communication protocols

(layer II and above) on integrated circuits
· realization of signal processing algorithms   (layer I) on integrated
circuits

 Circuit Production Experience
· cycle time management · design process analysis and optimization

WHAT WE ARE N O T LOOKING FOR

The candidate must not expect an elaborate development process
surrounding
the projects, nor to have complete detailed frozen specification before
beginning design.  The candidate must not expect or require a large team

environment – the project teams are typically small and very focused.
The
candidate must not expect to concentrate only on circuit design – full
stream involvement from opportunity identification, system definition,
planning, architecture and development is expected.  The person should
be
very hands-on and not expect a large staff of technicians or other
support
personnel to be assigned to projects.

WHO WILL THIS POSITION REPORT TO?

Research department head

ORGANIZATIONAL STRUCTURE

The projects will be in about 3-4 research departments, as part of the
Bell
Labs Research organization.  The Research organization, which has
approximately 1000 people, is responsible for creating new technology
and
systems in support of the Lucent business units.

The design research engineers have been recruited steadily over the
years
but the present goal is to staff another 20-30 people very quickly.

TRAVEL

Depending on the specific function, the travel could range from very
little
to a couple of times a month. The travel could be both domestic and
international.

YEARS OF PREVIOUS EXPERIENCE

3-5 years or more of industrial experience would be a plus.

EDUCATIONAL REQUIREMENTS

PhD degress from EE or CS are strongly preferred.

FUNCTIONAL EXPERIENCE

The same as described above would be strongly preferred. (New PhD
graduates
are welcome as well.)

INDUSTRY EXPERIENCE

R&D organizations from telecommunication companies or integrated
circuits
vendors.

WHAT DO YOU SEE AS SOME OF THE KEY "PLUSES" OF THE POSITION AND YOUR
ORGANIZATION?

The successful candidates will have the opportunity and freedom to
define
circuit design and implementation projects for making communications
systems
more efficient and more cost-effective. The working environment will be
with
many talented and highly motivated researchers at Bell Labs.

COMPENSATION

The candidate will receive a base salary, plus an annual bonus based on
the
financial performance of Lucent, plus an additional bonus based on the
performance of the individual in the preceding year.

DESIRED CANDIDATE TRAITS

Exceptional technical skills, self confidence and the ability to work
independently are essential.  The candidate will work with other very
strong
technical contributors who expect outstanding performance from all of
their
colleagues.


OTHER REQUIREMENTS

Advancement in the Bell Labs environment typically requires taking a
lead
technical role in an innovative and successful project.  Key to
advancement
is the ability to identify new technology opportunities, developing and
clearly articulating a plan for capitalizing on the opportunity,
securing
management support, leading the effort, and delivering as proposed.

MISC

This organization has already 20-30 experienced researchers in the same
area. The laboratory is called “Wireless Research Laboratory” but the
projects are more than just for wireless.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Visit Lucent on ejob @:
http://www.ejob.com/lucent.htm
http://www.ejob.com/lucent3.htm
email:  mailto:lucent@ejob.com

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML>
<B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>&nbsp;
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>VLSI Architect &lt;circuit
design and implementation research engineers (Members of Technical Staff)></FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>LOCATION:</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Murray Hill, NJ</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>SHORT-TERM EXPECTATIONS:
FIRST 90 DAYS</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The succesful candidate
will be assigned to</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) identify the circuit
implement opportunities for optical, wireless,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>switching and access
communicaitons systems,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) identify the algorithm
implementation opportunties for various</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>communicaitons systems,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) identify the design
challenges for implementing Gb/s circuits, or</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) identify the opportunity
for circuit realization cycle time reduction in</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>communication systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>MEDIUM-TERM EXPECTATIONS:
90 DAYS TO ONE YEAR</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidate
will, based on the initial studies from the first 3</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>months,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) propose feasible architectures
for efficient circuit realization of</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>various communications
functions,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) generate mathematical
models of the various algorithms to compare</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>peformance and cost of
various implementation options</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) provide initial designs
of impementing Gb/s circuits on advanced silicon</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>processing technologies</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) suggest methodology
for cycle time management</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidate
will have completed the design projects, and is</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>expected to continue
to identify emerging opportunities of circuit</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>realization for communication
systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>IMPORTANT TASKS THIS PERSON
WILL PERFORM ON AN ONGOING BASIS.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>1) Identify opportunities
for realizing communications functions on</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>integrated circuits</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>2) VLSI architecture
and high speed circuit design for communication systems</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3) Realization of signal
processing algorithms (layer I) on integrated</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuit</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>4) Realization of communications
protocols (layer II and above) on</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>integrated circuits</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>5) Cycle time management</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>IMPORTANT TASKS THIS PERSON
WILL PERFORM DAY ONE OF JOINING YOUR ORGANIZATION.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Identifying and realizing
communications functions on integrated circuits</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>SKILLS THE SUCCESSFUL
CANDIDATE MUST POSSESS IN ORDER TO ACCOMPLISH THE GOALS OF THE ORGANIZATION?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Skills and Experience</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; Candidates should
possess expert design skills in one or more of the</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>following areas together
with the knowledge of the technical challenges</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>facing the industry and,
most importantly, a creative ability to lead</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>research projects that
address these challenges.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&nbsp;Design Skills</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; custom circuit
design &middot; placement, routing and synthesis</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; VHDL design
&middot; signal integrity management</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; circuit simulation,
timing and verification &middot; mixed-signal design</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; FPGA design
&middot;</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&nbsp;Design Experience</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; high speed digital
circuits &middot; application-specific integrated circuit</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; co-processor
and accelerators &middot; application-specific standard circuit</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>product</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; digital signal
processors &middot; design of peripheral, bus, and I/O</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; microcontrollers
and RISC processors &middot; hardware and software co-design</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; analog circuits
including filters, analog-to-digital converters,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>digital-to-analog converters,
trans-impedance amplifiers, and laser drivers</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; VSLI Design
For Testability (DFT) techniques</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; memory and DMA</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&nbsp;Architecture and
System Design Experience</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; integrated circuit
for communication systems, including optical network,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>wireless, switching,
and access &middot; realization of communication protocols</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>(layer II and above)
on integrated circuits</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; realization
of signal processing algorithms&nbsp;&nbsp; (layer I) on integrated</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuits</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&nbsp;Circuit Production
Experience</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&middot; cycle time management
&middot; design process analysis and optimization</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT WE ARE N O T LOOKING
FOR</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The candidate must not
expect an elaborate development process surrounding</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>the projects, nor to
have complete detailed frozen specification before</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>beginning design.&nbsp;
The candidate must not expect or require a large team</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>environment – the project
teams are typically small and very focused.&nbsp; The</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>candidate must not expect
to concentrate only on circuit design – full</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>stream involvement from
opportunity identification, system definition,</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>planning, architecture
and development is expected.&nbsp; The person should be</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>very hands-on and not
expect a large staff of technicians or other support</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>personnel to be assigned
to projects.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHO WILL THIS POSITION
REPORT TO?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Research department head</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>ORGANIZATIONAL STRUCTURE</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The projects will be in
about 3-4 research departments, as part of the Bell</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Labs Research organization.&nbsp;
The Research organization, which has</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>approximately 1000 people,
is responsible for creating new technology and</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>systems in support of
the Lucent business units.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The design research engineers
have been recruited steadily over the years</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>but the present goal
is to staff another 20-30 people very quickly.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>TRAVEL</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Depending on the specific
function, the travel could range from very little</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>to a couple of times
a month. The travel could be both domestic and</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>international.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>YEARS OF PREVIOUS EXPERIENCE</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>3-5 years or more of industrial
experience would be a plus.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>EDUCATIONAL REQUIREMENTS</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>PhD degress from EE or
CS are strongly preferred.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>FUNCTIONAL EXPERIENCE</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The same as described
above would be strongly preferred. (New PhD graduates</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>are welcome as well.)</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>INDUSTRY EXPERIENCE</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>R&amp;D organizations
from telecommunication companies or integrated circuits</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>vendors.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>WHAT DO YOU SEE AS SOME
OF THE KEY "PLUSES" OF THE POSITION AND YOUR</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>ORGANIZATION?</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The successful candidates
will have the opportunity and freedom to define</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>circuit design and implementation
projects for making communications systems</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>more efficient and more
cost-effective. The working environment will be with</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>many talented and highly
motivated researchers at Bell Labs.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>COMPENSATION</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>The candidate will receive
a base salary, plus an annual bonus based on the</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>financial performance
of Lucent, plus an additional bonus based on the</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>performance of the individual
in the preceding year.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>DESIRED CANDIDATE TRAITS</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Exceptional technical
skills, self confidence and the ability to work</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>independently are essential.&nbsp;
The candidate will work with other very strong</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>technical contributors
who expect outstanding performance from all of their</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>colleagues.</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>&nbsp;</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>OTHER REQUIREMENTS</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Advancement in the Bell
Labs environment typically requires taking a lead</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>technical role in an
innovative and successful project.&nbsp; Key to advancement</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>is the ability to identify
new technology opportunities, developing and</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>clearly articulating
a plan for capitalizing on the opportunity, securing</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>management support, leading
the effort, and delivering as proposed.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>MISC</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>This organization has
already 20-30 experienced researchers in the same</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>area. The laboratory
is called “Wireless Research Laboratory” but the</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>projects are more than
just for wireless.</FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>></FONT></FONT></B><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1></FONT></FONT></B>
<P><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Visit Lucent on ejob @:</FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1><A HREF="http://www.ejob.com/lucent.htm">http://www.ejob.com/lucent.htm</A></FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1><A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></FONT></B>
<BR><B><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>email:&nbsp; <A HREF="mailto:lucent@ejob.com">mailto:lucent@ejob.com</A></FONT></FONT></B></HTML>

--------------F172D99685E6E6103DD408B9--

Article: 14208
Subject: Re: I don't trust Orcad
From: z80@ds2.com (Peter)
Date: Wed, 20 Jan 1999 08:10:53 GMT
Links: << >>  << T >>  << A >>
Well that is certainly true.

>It's obvious their designers don't draw schematics.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 14209
Subject: Re: PLL in FPGAs?
From: stuart2775@my-dejanews.com
Date: Wed, 20 Jan 1999 09:01:04 GMT
Links: << >>  << T >>  << A >>
In article <76svdr$8t8$1@info-server.surrey.ac.uk>,
  nospam_ees1ht@ee.surrey.ac.uk (Hans) wrote:
>
> Actel recently published an article on DPLL's in an Actel FPGA. Unfortunately
I
> can remember were I've seen it. I remember that the author was Steff
> Niewadomski (spelling?).
>
> Hans.
>
> Brett George wrote in message <367F428F.5641E93E@clarityeq.com>...
> >Hi all,
> >
> >Has anyone tried implementing a PLL in an FPGA (eg. ALTERA), we are
> >thinking of using it to reduce clock jitter from an externally generated
> >clock source.
>
>

Altera's 10KE devices with PLLs will offer the Clock lock clockboost options
to reduce clock delay and skew, and to perform clock multiplication. More
info on these features can be found on the Altera Web page at www.altera.com


-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    

Article: 14210
Subject: Boundary Scan & FPGA
From: Milos Becvar <milosb@s3two.ie>
Date: Wed, 20 Jan 1999 11:06:03 +0000
Links: << >>  << T >>  << A >>
Hi to everyone !

We were trying to use JTAG Progammer from Xilinx tools. We were
experimenting with Boundary Scan and it long time did not work. After a
lot of headache we realised, that Boundary Scan Chain Debug program
instead of 1 pulse of TCK put 3 pulses, instead of 5 pulses put 7 pulses
and so, on (if you remove two aditional pulses on TCK it works !). I
hope our experience could help to someone. 

Now I have question. Does anybody have any experience with using
ReadBack property in JTAG interface ? There is not much information in
the Xilinx docummentation about it.

			Thanks
					Milos Becvar
					ASICentrum, Prague
Article: 14211
Subject: Re: The development of a free FPGA synthesis tool
From: Jamie Lokier <spamfilter.jan1999@tantalophile.demon.co.uk>
Date: 20 Jan 1999 13:08:04 +0000
Links: << >>  << T >>  << A >>
> This looks like something a few other "free" projects would be interested in
> using and perhaps in contributing towards:

Thanks for your interest!  The list of resources is very useful.
If you find any more, please post them or send them my way.

> I've heard rumors that someone created a crude tool that translated from
> ordinary C code to VHDL (or was it Verilog ?) for his thesis; the idea was to
> run certain compute-intensive subroutines *really* fast, blurring the
> distinction between hardware and software.

There are a few "C" to netlist translators around.  These are the
commercial ones I know of:

  - Handel-C (which I am affiliated with)
      http://www.embedded-solutions.ltd.uk/ProdApp/handelc.htm
  - C Level Design (formerly Compilogic)
      http://www.cleveldesign.com/

I have heard of a few academic (i.e. non-commercial) translators, but I
don't know of any in particular.

I don't think any of them translate the full C language properly.
Handel-C has a nice approach to parallel processing, concurrency and timing.

> So, now what ?

Read other people's source, encourage interest, check legal position.
Find out what I can use that already exists.  Think real hard about
retargettable fitting.

-- Jamie
Article: 14212
Subject: Re: Xilinx Bitstream
From: ems@riverside-machines.com.NOSPAM
Date: Wed, 20 Jan 1999 14:13:54 GMT
Links: << >>  << T >>  << A >>
i've put some C code up at:

http://www.riverside-machines.com/pub2/xilinx/configuration/configuration.htm

i've also included some useful stuff that has has appeared on this
newsgroup. feel free to mail me any useful docs/code/etc, or articles
that i've missed from the group, and i'll add them.

evan

Article: 14213
Subject: Secondary clock nets in Xilinx Virtex
From: Terry Fraser <noone@dont.bother.com>
Date: Wed, 20 Jan 1999 15:55:26 GMT
Links: << >>  << T >>  << A >>
Has anyone ever tried to use the 'secondary  global nets' for clock
distribution
in a Xilinx Virtex ?

The Virtex only has 4 primary global clock buffers, but I have a design
that uses more than 4 clocks, so I need to use secondary nets. So far, I
have not been able
to convince the Xilinx tool to use them. It routes the clocks using a
mess of local
routing, which give large delay and skew.

Anyone know how to do this ?

--
-----
Terry Fraser
Hardware Designer
Applied Microelectronics Inc
Halifax, NS
Phone: (902) 421-1250 ext 269
FAX:   (902) 429-9983
mailto:fraser@appliedmicro.ns.ca
http://www.appliedmicro.ns.ca


Article: 14214
Subject: EDTN Tech Note
From: "mdisman" <mdisman@ix.netcom.com>
Date: 20 Jan 1999 17:35:21 GMT
Links: << >>  << T >>  << A >>
This week's Tech Note is from Vantis and discusses the design
considerations when chosing between using CPLDs and FPGAs.  It can be found
on  http://www.edtn.com/pld

Murray Disman
Editor
EDTN PLD Design Center

Article: 14215
Subject: Design manager
From: Dominic Reitman <drreitma@iupui.edu>
Date: Wed, 20 Jan 1999 13:05:09 -0500
Links: << >>  << T >>  << A >>
After synthesizing my VHDL source code and creating the ".xnf" file I
create a project in Foundation Design Manager 1.4. Everything works
until I try to implement the project, at that point I receive an error
that states "illegal command line for invoking the Flow Engine". I can't
find anywhere what command line it is trying to run or any information
of the source of error. Any ideas would be helpful.

Thanks
Nick

Article: 14216
Subject: Re: PLL in FPGAs?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 20 Jan 1999 10:10:29 -0800
Links: << >>  << T >>  << A >>
stuart2775@my-dejanews.com wrote:

> > >Has anyone tried implementing a PLL in an FPGA (eg.
> ALTERA), we are
> > >thinking of using it to reduce clock jitter from an
> externally generated
> > >clock source.
> >
> Altera's 10KE devices with PLLs will offer the Clock lock
> clockboost options
> to reduce clock delay and skew, and to perform clock
> multiplication. More
> info on these features can be found on the Altera Web page
> at www.altera.com
>  

The Xilinx Virtex devices ( two of them have been shipping
since Oct/Nov  '98 ) each have four delay-locked loops that
can perform the functions asked for or mentioned in this
thread.
For detailed information, click on

http://www.xilinx.com/xapp/xapp132.pdf

Peter Alfke, Xilinx Applications
 

Article: 14217
Subject: Re: Foundation Express Problem
From: Dominic Reitman <drreitma@iupui.edu>
Date: Wed, 20 Jan 1999 13:22:05 -0500
Links: << >>  << T >>  << A >>
I've only done functional simulation and it operates ok, it's when I
download the bit file to the FPGA that I physically test an expensive wire.
Also, is there anyway to make that IOB setting from the DOS prompt? the
syntax for the "map" command shows settings to pack FF/latches into input,
output, or both types of IOB's (map -pr i|o|b ...).

Thanks
Nick

Rickman wrote:

> Here is my guess as to what is happening. I think your circuit is being
> synthesized correctly. But the FF is being pushed into the IOB of the
> input port. The messages above indicate this. The warning may be from
> the fact that the input and output IOB are now connected by a wire.
>
> If you go to the project manager and select "Implementation" and
> "Implementation Option" you will get the options dialog box. On the line
> that says "Implementation" click the "Edit Template" button and a new
> dialog box will come up. Find the "Pack I/O Registers/Latches into IOBs
> for:" control. Select "OFF". Now click OK and OK again. Now redo your
> Implementation. and you should get a good result.
>
> When you say that the output follows the input without waiting for the
> clock, are you running a simulation, or testing a chip? If a simulation,
> is it a functional simulation or timing (after place and route)?

> Rick Collins

Article: 14218
Subject: Re: Design manager
From: Hobson Frater <hobson@xilinx.com>
Date: Wed, 20 Jan 1999 10:36:13 -0800
Links: << >>  << T >>  << A >>
Check out Xilinx Answer 2141 on the Xilinx website.  The URL is:

http://www.xilinx.com/techdocs/2141.htm

Regards,
-Hobson Frater
Xilinx Applications

Article: 14219
Subject: Re: Problems with processes
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Wed, 20 Jan 1999 13:23:33 -0700
Links: << >>  << T >>  << A >>
Dominic Reitman wrote in message <369F99A4.D859CB19@iupui.edu>...
>I'm beginning to believe that the problem does not exist in the synthesis
>but rather the implementation. I've been implementing the designs at the
>dos prompt (not using XILINX Design manager) because the XILINX software
>gives me an error.

What error would that be?  MAP (Foundation 1.5) is throwing access faults,
even on designs that previously mapped.  Xilinx's response was, "Can you
install the tools on another machine?"  Luckily, they gave me a site license
rather than node-locked so I was able to install the tools on another NT
box; voila, the design implemented - on the other box.  Not exactly helpful.
The response to that was, "You'll have to reinstall NT."  Which I've
accepted as the only answer.  Actually, I blame Microsoft more than Xilinx.

Running map from the NT command line causes the same crash.  I pulled the
command-line parameters from what the GUI spit out.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14220
Subject: Re: Hard porting to FPGA Express
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Wed, 20 Jan 1999 13:54:01 -0700
Links: << >>  << T >>  << A >>
Ido Kleinman wrote in message <77lek9$5mo$1@news2.inter.net.il>...

>I've been using Foundation 1.4 with it's Metamor synthesis for a while now,
>and I've got a few working designs.
>I recently moved to Foundation 1.5 and it's FPGA Express synthesis -


In case it wasn't clear from Evan's post: Metamor is a VHDL'93-compliant
tool, FPGA Express is VHDL'87-compliant (with a couple of '93 things thrown
in).  The problems you're having are a result of Synopsys still living in
the Reagan era.

>1. FPGAEXP won't accept:
>if (LowerAddressBus > X"01F0") then


>LowerAddressBus is just a std_logic_vector(15 downto 0).

>it yells about type mismatch between left/right binary operand. The X seems
>to be disturbing - it would only accept Binary notation without any prefix
>to the " character so I have to write:

The X"xxxx" construct is valid only for bit vectors in '87. (See Evan's
comments.) SLVs are fine with it with '93.  That's why Metamor was happy and
FPGA Express was not.

>I tried using based literals such as 16#01F0# and variations - and it won't
>work. Any solution, or I will have to do all my comparisons in Binary?


Make sure you've included ieee.std_logic_arith.all and
ieee.std_logic_unsigned (or signed) and do a conversion:

    if (LowerAddressBus > CONV_STD_LOGIC_VECTOR(X"01F0", 16) then

which of course is a Synopsys work-around.

>2. My inhibit_buf attribute on my global Clk signal wasn't accepted! What's
>the attribute for inhibiting insertion of IBUFs/OBUFs/etc on FPGAEXP? I
>don't want my clock signal buffered with a standard IBUF, that why I
usually
>instanciate a BUFG/BUFGS for it and inhibit other buffers on the pad in the
>code.

FPGA Express is smart enough to recognize a clock as a clock (based on
sensitivity lists and how the signals are used in processes), so you don't
need to inhibit the IBUF on your clock signal.  A BUFG is automagically
instantiated for you.

>3. After I made the annoying adjustments to my code, my previously working
>simulation files yielded strange new results in which some output signals
>were defined as "????" - what's this? I thought std_logic "only" has 9
>states...


Sounds like a VHDL'87 vs '93 problem.  What simulator are you using?  Make
sure you compile all of your sources as VHDL'87 now!

>4. What about my two-dimensional arrays? I am not trying to synthesize
>anything special - just some better-looking-VHDL multi-bit look-up
tables...
> FPGAEXP won't support it?
>Forever?


With Synopsys, who knows?  Maybe when VHDL'2K comes out.  Then they'll be at
the '93 level.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14221
Subject: Re: Secondary clock nets in Xilinx Virtex
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Wed, 20 Jan 1999 21:18:47 GMT
Links: << >>  << T >>  << A >>
On Wed, 20 Jan 1999 15:55:26 GMT, Terry Fraser <noone@dont.bother.com>
wrote:

>Has anyone ever tried to use the 'secondary  global nets' for clock
>distribution
>in a Xilinx Virtex ?

This was probably the first question I asked of Xilinx when 1.5
dropped through the door with Virtex. It appears to be rather a bone
of contention, especially for most (if not all) of the Xilinx FAEs
here in the UK. The "official" line is that the router is supposed to
be smart and use these for wide fanout signals, but as yet there is no
way of actually telling the tool to use them. My common example is a
clock divider (by 100) which even on it's own gets crappy skew. In
Spectrum I just BUFFER_SIG it with a BUFGLS for 4000XL and hey-presto,
nice clock. In Virtex, I have not found anything to duplicate this.

I couldn't even see ay sign of these 24 internal buffers in EPIC.
Perhaps they are not true buffers?

Mr Alfke, can you help?

Cheers
Stuart
An employee of Saros Technology, The HDL Solutions Company:
Renoir
Model Technology
Exemplar Logic
TransEDA
www.saros.co.uk
(I sell these products, so paint me biased)
Article: 14222
Subject: Several EDA jobs in US with Work visa
From: garynlang@aol.com (Garynlang)
Date: 20 Jan 1999 22:32:08 GMT
Links: << >>  << T >>  << A >>
We have several  job openings in Portland (Oregon), San Jose (California)
Boulder (Colorado) and  Phoenix (Arizona) 
We provide US work visa for qualified candidates. Please send us 
text only resume if you are interested. 

Software Engineer:

Position #1, San Jose: Experience with one or more of the following is 
desired: Integrated Circuit or board design, 
HDL (VHDL, Verilog, or ABEL) design, Simulation and/or Synthesis tools, 
MFC, GUI, and graphics software development, and compiler design or GUI 
oriented text editors development.  

Pos #2: Development and enhancement to existing download 
and test tools to generate Java code.  Development of suite of tools to 
execute Java executables and verification of Java executables on a 
variety of platforms.  
Job Requirements: BSEE or CS.  Experience with Java, C, C++ (3-5 
years).  Digital logic design basics.  

Position #3, Arizona:  UNIX, C++, EDA knowledge with 2 years exp. 

Position #4: Senior Test Engineer
Job Responsibilities: Responsible for Test program development, 
augmentation and characterization, assisting with Yield 
Analysis/Enhancement, Statistical Data Collection and Interpretation, 
and the Transfer of Test Programs and associated Test Hardware into 
production.  
Job Requirements: BSEE or equivalent. 2-3 years experience with 
Versatest V11xx/V12xx/V33xx, strong programming skills>> "C" a must. 
Strong Memory Background, strong Logic Theory, and a desire to be 
challenged in a dynamic field of programmable logic. 


Applications Engineer  1.
 BSEE and 3 years minimum digital design experience. 
Working knowledge of FPGA and ASIC applications. At least 3 years of 
experience working with digital ICs and design tools. In-depth Hardware 
Descriptive Language (VHDL and/or Verilog) capability, strong synthesis 
and simulation tools experience, and good communications skills.  

Application Engineer 2.
Provide expert support of customers using Java as 
an essential system solution.  This involves understanding the operation 
and use of IEEE Std. 1149.1 as well as the capabilities of Xilinx's 
associated H/W and S/W.  
Job Requirements: BSEE or CS.  Digital logic design incorporating 
design-for-test rules.  In particular those related to IEEE Std. 1149.1  
Good oral and written communication skills.  

Applications Engineer (Physical Design) 3.

Perform Place and Route Activity for the HardWire 
designs. Assist in layout for HardWire Base array designs.  
Job Requirements: AA degree with 5-8 yrs. experience as a mask designer. 
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 Layout Designer  
Custom IC Layout of the CPLD products, layout 
verification using dracula LVS and DRC tools automatic routing.  
Job Requirements: Hands-on experience with EDGE and OPUS layout 
verification tools (LVS, DRC). And requires 5+ years of related 
experience.  

 CAD Engineer
Responsible for CAD software development and support.
 Also responsible support of Cadence tools.  
 BSEE. 3+ yrs. experience in CAD, IC design, or 
software development. Knowledge of IC design and good software 
development skills. Knowledge of Cadence tools. Programming in skill, c, 
UNIX shell, Perl.  

Sincerely: 
Gary Lang
http://www.acdcon.com
(949) 360-4155



Article: 14223
Subject: Re: Secondary clock nets in Xilinx Virtex
From: mcgett@efc0.xsj.xilinx.com (Ed McGettigan)
Date: 20 Jan 1999 15:57:06 -0800
Links: << >>  << T >>  << A >>
Terry Fraser wrote:
>The Virtex only has 4 primary global clock buffers, but I have 
>a design that uses more than 4 clocks, so I need to use secondary 
>nets. So far, I have not been able to convince the Xilinx tool to 
>use them. It routes the clocks using a mess of local routing, which 
>give large delay and skew.
>
>Anyone know how to do this ?

The "secondary global nets" is a misleading term that has been
used to describe how Virtex handles large fanout nets. A correct
term would be backbone routing. 

The Virtex backbone routing is comprised of 12 horizontal longlines
with specialized hex-lines in the top and bottom IOB rows and 12 
vertical longlines with specialized hex-lines in the vertical columns
with the hex-lines having the ability to connected directly to the
CLB, IOB and RAM clock and control inputs.  This provides for up-to
24 high-fanout, reduced-skew and reduced-delay nets with a maximum
of 12 per column.

Since these are flexible resources without a specific entry or exit 
point there isn't a library cell that represents them.  The router
has built-in algorithms to determine the need to use these routes
and the recipe for building the cells.  We have found two minor 
problems in routes to the IOB and BlockRAMs that will be fixed in 
the next M1.5i Service Pack release.

Designers can improve the overall delay and skew of the backbone
nets in several ways.

   1) Place the source of the net in the middle of the top or
      bottom row.  This provides for easier access to the horizontal
      longlines at the start of the backbone.   This can be done
      with a simple location constraint in the design's UCF file.

       INST  myclk_pad  LOC = AL17 ;     # Valid for BG432 package

      or

       INST  myclkdv_reg LOC = CLB_R32C24.S1 ; # Valid for XCV300 

   2) Cluster the logic together to reduce overall delay.  This can
      be done with a simple area location constraint in the design's
      UCF file.

       INST  mymodule   LOC = CLB_R1C1:CLB_R32C10 ; #Valid for XCV300


Routes that use these resources are quite easily determined in
the EPIC viewer.  When you have highlighted the net you will see
a top or bottom backbone that feeds the vertical longlines that in
turn feed the vertical hex-lines that then connect directly to the
CLB, IOB or RAM inputs.  You should not see any other horizontal 
routes in the core, unless you are also routing to LUT inputs.

I would include a pretty picture here showing a typical net, but we
don't want binaries cluttering up the newsgroup.  

Ed McGettigan
--
Xilinx Inc.

-- 

Ed
--
Article: 14224
Subject: Re: The development of a free FPGA synthesis tool
From: jspeter@twinkle.roanoke.infi.net
Date: 20 Jan 1999 20:03:01 -0500
Links: << >>  << T >>  << A >>
> There are a few "C" to netlist translators around.  These are the
> commercial ones I know of:
> 
>   - Handel-C (which I am affiliated with)
>       http://www.embedded-solutions.ltd.uk/ProdApp/handelc.htm
>   - C Level Design (formerly Compilogic)
>       http://www.cleveldesign.com/
> 
> I have heard of a few academic (i.e. non-commercial) translators, but I
> don't know of any in particular.

Coincidentally, this is my research topic as well.  Here are some notes I've
gathered on other attempts:

  C to Netlist Compiler (nlc):
    Given a program written in a ``small subset of C++ with a few extensions,''
    nlc compiles the program into an FPGA configuration. ftp://lslsun5.epfl.ch/pub/
  CEDES:
    C++ as an HDL.  Several C++ classes are provided to allow users to
    generate netlists programmatically, and synthesize them into an FPGA
    configuration.
    http://www.fbeedle.com/bookinfo/09-0.html
  COBRA-ABS:
    A. Duncan, D. Hendry, P. Gray, ``An Overview of the COBRA-ABS High Level
    Synthesis System for Mult-FPGA Systems,'' Proceedings: IEEE Symposium on
    FPGAs for Custom Computing Machines, Napa Valley, CA, to appear, April 1998.
  DISC:
    The Dynamic Instruction Set Compiler maps various function calls onto a
    partially reconfigurable FPGA.  Precompiled functions accelerate normal
    execution.
  Data Parallel C Compiler:
    M. Gokhale, R. Minnich, ``FPGA Computing in a Data Parallel C,'' IEEE
    Workshop on FPGAs for Custom Computing Machines, Napa Valley, CA, pp. 94-101,
    April 1993.
  GigaOps X Language Compiler (xc):
    http://www.reconfig.com/giga/xc_ic.htm
  Handel C:
    Uses ``a subset of the C language extended with a few powerful extra
    features'' to describe a circuit.
  Sisal:
    A ``functional language for parallel numerical computation''.
    http://www.physics.nmt.edu/raymond/sisaltutorial/Tutorial.html
  Systolic Parallel C:
    ``C dialect with systolic and parallel extentions''
    R. Zoz,
    http://www-mp.informatik.uni-mannheim.de/groups/mass_par_1/projects/spc.html
  Transmogrifier C:
    Takes in ``a restricted subset of the C programming language'' and generates
    a netlist.
    http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc/

> I don't think any of them translate the full C language properly.
> Handel-C has a nice approach to parallel processing, concurrency and timing.

So far as I know, none of these can take full ANSI-C code.  My research
attempts to support full ANSI-C by running the input through the freely
available retargettable compiler, LCC.  I then just use the output from LCC
as the input to the core compiler.

--Jim
(http://www.cs.princeton.edu/software/lcc/)
(http://www.ee.vt.edu/~ccm/)



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