Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 15600

Article: 15600
Subject: Re: virtex partial reconfiguration
From: Le mer Michel <michel.lemer@ago.fr>
Date: Fri, 02 Apr 1999 10:06:37 +0200
Links: << >>  << T >>  << A >>
Ed McGettigan wrote:

> In article <370323D8.68D63B6F@irisa.fr>,
> >Does a frame corresponds to the global reconfiguration of a small area of
> >the Virtex (CLB logic and Routing), or are there different types of
> >frames ? For example some frames for routing configuration and some
> >others for CLB/IOB ?
> >
> A Virtex frame contains a sequence of bits that spans the entire height
> of the device with multiple frames per column.
>
> >According to the virtex datasheet, a  XCV300 has a 32x48 CLB matrix, the
> >whole device needs 1,700,000 bits to be reconfigured, This means that the
> >"average" configuration data for a CLB plus routing is 1,100 bit i.e 2
> >frames.
> >
>
> You're forgetting the IOB configuration and the Block SelectRAM
> configuration space as well as configuration overhead.
>

Can we know the frame sequence? BlockSelectRAM have special columm number,
different from CLB, what about the IOB?
During IOB reconfiguration, are these IOB in tri-state, during a moment?

Are all configuration mode supported for partial reconfiguration?

Thank you.


Michel Le Mer
Gerpi sa (Xilinx Xpert)
3, rue du Bosphore
Alma city
35000 Rennes (France)
(02 99 51 17 18)
http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm

Article: 15601
Subject: Re: Schematic Capture & FPGA synthesis
From: ems@riverside-machines.com.NOSPAM
Date: Fri, 02 Apr 1999 11:54:09 GMT
Links: << >>  << T >>  << A >>
On Fri, 02 Apr 1999 00:50:46 -0500, Ray Andraka <randraka@ids.net>
wrote:

>Are you sure about that price?  Seems pretty low to me.

Sounds about right. It's about 10K in the UK, ie. about 16500 USD, so
I can believe that it's 12K in the US, given the extraordinary markups
we pay on everything here (Stuart - perhaps you'd care to comment on
this... :>)

There are various restrictions. You get the PE version of Modelsim
(which is fine for most things, and the one I have myself). You only
get Level 2 Spectrum, which may be a problem in some cases. I prefer
Level 3, which gives you scripting and some better hierarchical
optimisation options, but it's a lot more expensive. The only omission
on Renoir seems to be that you don't get the version control. VC on
Renoir seems to be simply a set of hooks into Gnu's RCS, which you can
get free off the web anyway (I personally use CS-RCS, which gives you
a fancy windoze front-end to RCS, and is free for a single user).

My current client has a couple of seats of this lot turning up next
week, so I'm hoping to get a better idea of any limitations then.

Evan (another one!)

Article: 15602
Subject: Re: How to implement Matched Filter in FPGA?
From: ems@riverside-machines.com.NOSPAM
Date: Fri, 02 Apr 1999 11:58:02 GMT
Links: << >>  << T >>  << A >>
On Fri, 02 Apr 1999 07:15:39 GMT, batman2054@my-dejanews.com wrote:

>Hello,	I have taken up a project to build a board as a CDMA baseband
>receiver. Basically I am planning to use an Altera FLEX10K device to
>implement it. A question I encountered is that how to build a Digital Matched
>Filter in FPGA. (Maybe about 256 taps or more? Is this parameter too
>difficult to realize?) I think the big barrier is that how to realize the
>high-speed  parallel adder. (The chip rate is about 4M cps. The sample rate
>for acquisition is 4M sps too.)
>
>  Could anyone give me some hints on this? Any help is greatly appreciated. 
>:) Thanks in advance.
>
>Forest Niuman
>niuman@263.net

Well, this is probably not the help you're looking for, but:

(a) Are you actually trying to implement CDMA baseband in a 10K? You'd
need a large board full of them. Presumably you're just doing some
filtering?

(b) My first reaction to a 256-tap FIR, at 4 Meg, is that it may be
impossible in an Altera device. You need to run bit-serial, and that's
much easier in a Xilinx, using distributed memory.

(c) You need to do the matching in the analog front-end. Why do you
want to do it in digits?

Evan

Article: 15603
Subject: Re: How to implement Matched Filter in FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 09:20:35 -0500
Links: << >>  << T >>  << A >>
A 256 tap 12 bit filter at 4MSPS can be done in Xilinx 4036 if you know what you
are doing (requires a fair degree of handcrafting and floorplanning).  Kids,
don't try this is an Altera 10K, this is performed by highly skilled designers in
a controlled environment...

The Xilinx design makes extensive use of the CLB "select RAM" capability to
implement the delay queues (one for each tap, 12 clocks each).  Altera has no
suitable equivalent so the queues need to be constructed with an LE per delay bit
(poof!, over 384 LABs gone) or using the EABs as 12 deep by 8 (16 if you use an E
part) queues...that gets an equivalent 96 (192 in E) flip-flops per EAB (that
would use up 16 EABs in a big E part).  Off the top of my head, the total filter
implemented in Altera is about 4700 LE's if you don't make use of the EABs at
all.  By using the EABs for delay queues (over twice the efficiency of using them
for the SDA LUTs),   You have just about enough logic in a 10K50E to do the
filter.  You still need to route it though.  Should be no problem to do in a
10K70E.  If the filter is symmetric, you can take advantage of the symmetry and
save about 250 LEs.

BTW, The adders should be arranged as a pipelined tree.  That is the easy part
regardless of the technology used.  If I had my druthers for this, I'd use the
xilinx part because it does the delays so much nicer.


batman2054@my-dejanews.com wrote:

> Hello,  I have taken up a project to build a board as a CDMA baseband
> receiver. Basically I am planning to use an Altera FLEX10K device to
> implement it. A question I encountered is that how to build a Digital Matched
> Filter in FPGA. (Maybe about 256 taps or more? Is this parameter too
> difficult to realize?) I think the big barrier is that how to realize the
> high-speed  parallel adder. (The chip rate is about 4M cps. The sample rate
> for acquisition is 4M sps too.)
>
>   Could anyone give me some hints on this? Any help is greatly appreciated.
> :) Thanks in advance.
>
> Forest Niuman
> niuman@263.net
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15604
Subject: Re: How to implement Matched Filter in FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 09:27:10 -0500
Links: << >>  << T >>  << A >>


ems@riverside-machines.com.NOSPAM wrote:

> Well, this is probably not the help you're looking for, but:
>
> (a) Are you actually trying to implement CDMA baseband in a 10K? You'd
> need a large board full of them. Presumably you're just doing some
> filtering?

No true, You should be able to do a 256 tap 12 bit  non-symmetric filter in a
10K70 at the required 4MSPS, but Xilinx is still the better choice because of the
delay queue implementation.  See my previous post

>
>
> (b) My first reaction to a 256-tap FIR, at 4 Meg, is that it may be
> impossible in an Altera device. You need to run bit-serial, and that's
> much easier in a Xilinx, using distributed memory.

Only easier in Xilinx because of the implementation of the delay queue.  The LUTs
in the Altera are faster, but the global routing will keep both to roughly 8 MSPS
max with 12 bit inputs.

>
>
> (c) You need to do the matching in the analog front-end. Why do you
> want to do it in digits?
>

Come again?  The matched filter can be translated through the demodulator (the
demod and the filters are all time invariant linear systems), and for that matter
can be lumped with the demodulation filter and any decimating filters if you do
the demodulation from IF digitally too.  Doing the matched filter digitally at
baseband has several advantages over doing an analog passband matched filter,
although it will cost a bit more in power.

> Evan



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15605
Subject: New Book: Programming Embedded Systems in C and C++
From: Michael Barr <info@netrino.com>
Date: Fri, 02 Apr 1999 14:28:56 GMT
Links: << >>  << T >>  << A >>
This is a periodic post to announce my new book, "Programming
Embedded Systems in C and C++" (ISBN 1-56592-354-5).  I believe 
this title may be relevant to some of the readers of this news-
group.

The book is published by O'Reilly & Associates and available
directly from them (http://www.oreilly.com/catalog/embsys/), 
in your local computer-friendly bookstore (Border's carries
it in all their stores), or online from Amazon:

 http://www.amazon.com/exec/obidos/ASIN/1565923545/netrino/

Unfortunately, though, Amazon and most of the other large on-
line book sellers have recently run out of stock.  It looks 
like the first printing may already be running out!  One online
vendor that does still have copies is Computer Literacy (now 
known online as fatbrain.com):

 http://www1.fatbrain.com/asp/bookinfo/bookinfo.asp?theisbn=1565923545

I've put the Table of Contents and Preface on my website to 
help potential readers get a feel for the book without buying
it.  I've also put copies of the Embedded Systems Glossary and 
Bibliography (from the back of the book) on my website as well:

 http://www.netrino.com/Books/EmbeddedC/

 http://www.netrino.com/Publications/Glossary/

 http://www.netrino.com/Publications/Bibliography/

It is my intention to make occasional changes and updates to 
the online version of the glossary and bibliography.  So I 
would very much like to hear your constructive feedback.  
Please write to me at <mailto:webmaster@netrino.com>.

I have put a lot of work into the book, as well as the online
versions of the glossary and bibliography.  I sincerely hope
that all three will be valuable contributions to the community
of embedded systems developers.

Sincerely,
           Michael Barr

Article: 15606
Subject: Re: Schematic Capture & FPGA synthesis
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 09:38:36 -0500
Links: << >>  << T >>  << A >>
I'd believe the $16,500.  That's about what I figured it was for Level 2
spectrum plus modelsim PE, based on quotes I got last year.

ems@riverside-machines.com.NOSPAM wrote:

> On Fri, 02 Apr 1999 00:50:46 -0500, Ray Andraka <randraka@ids.net>
> wrote:
>
> >Are you sure about that price?  Seems pretty low to me.
>
> Sounds about right. It's about 10K in the UK, ie. about 16500 USD, so
> I can believe that it's 12K in the US, given the extraordinary markups
> we pay on everything here (Stuart - perhaps you'd care to comment on
> this... :>)
>
> There are various restrictions. You get the PE version of Modelsim
> (which is fine for most things, and the one I have myself). You only
> get Level 2 Spectrum, which may be a problem in some cases. I prefer
> Level 3, which gives you scripting and some better hierarchical
> optimisation options, but it's a lot more expensive. The only omission
> on Renoir seems to be that you don't get the version control. VC on
> Renoir seems to be simply a set of hooks into Gnu's RCS, which you can
> get free off the web anyway (I personally use CS-RCS, which gives you
> a fancy windoze front-end to RCS, and is free for a single user).
>
> My current client has a couple of seats of this lot turning up next
> week, so I'm hoping to get a better idea of any limitations then.
>
> Evan (another one!)



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15607
Subject: Re: New Book: Programming Embedded Systems in C and C++
From: "Mark Levis" <mark_levis@compuware.com>
Date: Fri, 2 Apr 1999 09:56:08 -0500
Links: << >>  << T >>  << A >>

Michael Barr <info@netrino.com> wrote in message
news:3704D40C.C636F539@netrino.com...
| This is a periodic post to announce my new book, "Programming
| Embedded Systems in C and C++" (ISBN 1-56592-354-5).  I believe

| The book is published by O'Reilly & Associates and available
| directly from them (http://www.oreilly.com/catalog/embsys/),
| in your local computer-friendly bookstore (Border's carries
| it in all their stores), or online from Amazon:
|

Why does no one ever mention other online bookstores
like www.borders.com (my former employer)? If they
carry it in the store they have it online as well.

[snip]

| I have put a lot of work into the book, as well as the online
| versions of the glossary and bibliography.  I sincerely hope
| that all three will be valuable contributions to the community
| of embedded systems developers.
|
| Sincerely,
|            Michael Barr


Article: 15608
Subject: Re: virtex partial reconfiguration
From: Steven Derrien <sderrien@irisa.fr>
Date: Fri, 02 Apr 1999 17:00:44 +0200
Links: << >>  << T >>  << A >>
Hi,

Ed McGettigan wrote:

> In article <370323D8.68D63B6F@irisa.fr>,
> >Does a frame corresponds to the global reconfiguration of a small area of
> >the Virtex (CLB logic and Routing), or are there different types of
> >frames ? For example some frames for routing configuration and some
> >others for CLB/IOB ?
> >
> A Virtex frame contains a sequence of bits that spans the entire height
> of the device with multiple frames per column.

Sorry, I'm afraid my question was not clear :
You need several frames (48) to reconfigure the whole column right ?
Within these frames, are some of them dedicated to routing configuration and
some others to CLB configuration ?
Or does a frame contain data configuration for both routing and CLB ?

> To reconfigure all bits in a CLB column including CLB configuration,
> LUT equation and routing requires 48 frames.  However you do not need
> to write all 48 frames and this can lead to some interesting uses.

Does this mean 1 frame per CLB (the XCV300 has 48 CLB/Column right ?)

> >According to the virtex datasheet, a  XCV300 has a 32x48 CLB matrix, the
> >whole device needs 1,700,000 bits to be reconfigured, This means that the
> >"average" configuration data for a CLB plus routing is 1,100 bit i.e 2
> >frames.
>
> You're forgetting the IOB configuration and the Block SelectRAM

Right.

> as well as configuration overhead.

In this case what do you mean by "configuration overhead" ?

Thanks,

Steven Derrien


Article: 15609
Subject: Re: Schematic Capture & FPGA synthesis
From: Richard Guerin <guerin2@home.com>
Date: Fri, 02 Apr 1999 17:13:05 GMT
Links: << >>  << T >>  << A >>


Ray Andraka wrote:
> 
> I'd believe the $16,500.  That's about what I figured it was for Level 2
> spectrum plus modelsim PE, based on quotes I got last year.


That was last year .... before Mentor Graphics aquired Exemplar ! 
Here's a links to the press releases that announced the merger and the
introduction of Packaged Power suite.

	http://www.exemplar.com/corporate/html/prs/PR022399.html

	http://www.model.com/news/pr/pr9902.html

Like I had previously mentioned .... "It's a tough value to beat" !  For
about the price of single FPGA Express license or single node-locked
Synplify seat you get excellent quality graphical entry, simulation, and
synthesis tools from a leading CAE vendor.

Article: 15610
Subject: Re: virtex partial reconfiguration
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 2 Apr 1999 11:37:44 -0800
Links: << >>  << T >>  << A >>
In article <37047A8D.2D7934A0@ago.fr>,
Le mer Michel  <michel.lemer@ago.fr> wrote:
>Can we know the frame sequence? BlockSelectRAM have special columm number,
>different from CLB, what about the IOB?

Yes, Yes and Yes for the left and right edges, No for the top and bottom
edges.  We will be publishing this information shortly so please be patient 
for a little while longer.

>During IOB reconfiguration, are these IOB in tri-state, during a moment?
>

The IOB would only be in a tri-state mode only if you have asserted 
GTS.  But since you can't reconfigure your board connections on the
fly, I can't see much use in modify the IOB configuration from the
startup state so this should not be an issue.

>Are all configuration mode supported for partial reconfiguration?
>

Only the SelectMAP and JTAG ports support this. The Master/Slave serial
is designed primarily for SPROM usage and thus lacks addressabilty.

Ed

Article: 15611
Subject: Re: virtex partial reconfiguration
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 2 Apr 1999 11:49:37 -0800
Links: << >>  << T >>  << A >>
In article <3704DB9C.93CA36E5@irisa.fr>,
Steven Derrien  <sderrien@irisa.fr> wrote:
>Sorry, I'm afraid my question was not clear :
>You need several frames (48) to reconfigure the whole column right ?

Yes. 

>Within these frames, are some of them dedicated to routing configuration and
>some others to CLB configuration ?
>Or does a frame contain data configuration for both routing and CLB ?

A single frame contains a mix set of bits for CLB configuration and routing
information.  

>Does this mean 1 frame per CLB (the XCV300 has 48 CLB/Column right ?)

No.  Each frame contains a set of bits for all CLBs in the column. The
smallest Virtex part (XCV50) and the largest Virtex part (XCV1000) have
the same number of frames per column, but different frame sizes 384 and
1248 respectively.

>In this case what do you mean by "configuration overhead" ?

Housekeeping chores primarily, CRC start/stop/checks, Startup Sequence, etc..
and some padding to keep the data aligned. For a complete device 
configuration this amounts to about 1-2% of the bitstream.

We will be publishing further details shortly so please be patient with
us for a little while longer.

Ed

Article: 15612
Subject: Experiencing 8255 with Xilinx Foundation (XC4000E Family)
From: rider1037@my-dejanews.com
Date: Fri, 02 Apr 1999 21:36:33 GMT
Links: << >>  << T >>  << A >>
I am new to FPGAs and VHDL. After experiencing VHDL with Aldec compiler, I
chose 8255 for modelling at the behavioral level using Foundation 1.5. I used
a technique similar to the one described in comp.lang.vhdl (Re: Programmable
IO in VHDL) for modelling the inout ports of the 8255. Could somone who has
experienced or experiencing the modelling of 8255 share their thoughts on the
modelling of the device. I am also curious of the commercial cores for 8255.
Do they develop these cores using Intel's data sheet alone or otherwise.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15613
Subject: Problems with Foundation1.5
From: rider1037@my-dejanews.com
Date: Fri, 02 Apr 1999 22:22:42 GMT
Links: << >>  << T >>  << A >>
I am using Foundation 1.5 and Aldec 3.2. I am experiencing rather strange
behavior with F1.5, which I would like to share with others.

1. I declared a signal "Control_register(7 downto 0)". After synthesis, I
simulated the design. I wanted to see the activity on the signal mentioned
above. In the "Signal selection window", something like this shows up
"Control_register1". Four of the array members are there and the rest are
missing. I try to find the rest using "Find signal" feature. This feature does
not help. There is no help on xilinx answer database (they did assign an
Application Engineer to resolve the matter on my request). Has anyone
experienced similar behavior.

2. I was having problems defining a "programmable I/O". A warning message
shows up as I try to synthesize the design (which has D: inout (7 downto 0))
Dpm:Warning: The port type of port/ver22/D<7> upto <0> is unknown> An output
pad will be inserted. (FE-pmap-18). I started to remark my code to track down
the problem. Finally, I remarked the line where D itself was declared (which
means that the port D was no longer in use). I synthesize the design again.
To my surprise, the same warning message appears (even though D is not
declared). STRANGE!!!!!!!!!!!!!. I had copied the project from the previous
design and to me it seems that the Synthesis tool is reading a file from its
previous synthesized files (when D was declared). I have the files with me.
If someone wants to try them out. I can send them for experience. With these
two problems and experience of only one month with F1.5, I feel there are
serious bugs in the F1.5 itself. Regards

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15614
Subject: Verilog PLI website
From: Swapnajit Mittra <mittra@my-dejanews.com>
Date: Sat, 03 Apr 1999 00:51:15 GMT
Links: << >>  << T >>  << A >>
			Project VeriPage
		(http://www.angelfire.com/ca/verilog)

   This site is meant to be a meeting place for the users
   of Verilog PLI, where starters can glimpse into the
   resources and experts can impert their tips.

   Now the site is in its third revision. Apart from its
   tutorial and examples, the new addition to the site is
   a PLI FAQ.

   The site also has a growing section on Verilog related
   utilities and links.

   Enjoy.

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Project VeriPage - Your One Stop Source for Verilog PLI resources
http://www.angelfire.com/ca/verilog/
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15615
Subject: Re: How to implement Matched Filter in FPGA?
From: batman2054@my-dejanews.com
Date: Sat, 03 Apr 1999 01:32:40 GMT
Links: << >>  << T >>  << A >>
Thanks very much for your kind advice.

Because of some environment limits, I can only use the Altera device now.
If I would like to simplify the implementation, such as reduce the sample
data width to 6 bits or 4 bits,(Or to an extremeness, reduce to 1 bit,
but the sample rate should rise to 8M sps.)what do you think about it?
Is it much more simple to realize?

Thanks with my heart again.

Forest Niuman
Niuman@263.net


In article <3704D233.51FB26DB@ids.net>,
  Ray Andraka <randraka@ids.net> wrote:
> A 256 tap 12 bit filter at 4MSPS can be done in Xilinx 4036 if you know what
you
> are doing (requires a fair degree of handcrafting and floorplanning).  Kids,
> don't try this is an Altera 10K, this is performed by highly skilled designers
in
> a controlled environment...
>
> The Xilinx design makes extensive use of the CLB "select RAM" capability to
> implement the delay queues (one for each tap, 12 clocks each).  Altera has no
> suitable equivalent so the queues need to be constructed with an LE per delay
bit
> (poof!, over 384 LABs gone) or using the EABs as 12 deep by 8 (16 if you use
an E
> part) queues...that gets an equivalent 96 (192 in E) flip-flops per EAB (that
> would use up 16 EABs in a big E part).  Off the top of my head, the total
filter
> implemented in Altera is about 4700 LE's if you don't make use of the EABs at
> all.  By using the EABs for delay queues (over twice the efficiency of using
them
> for the SDA LUTs),   You have just about enough logic in a 10K50E to do the
> filter.  You still need to route it though.  Should be no problem to do in a
> 10K70E.  If the filter is symmetric, you can take advantage of the symmetry
and
> save about 250 LEs.
>
> BTW, The adders should be arranged as a pipelined tree.  That is the easy part
> regardless of the technology used.  If I had my druthers for this, I'd use the
> xilinx part because it does the delays so much nicer.
>
> batman2054@my-dejanews.com wrote:
>
> > Hello,  I have taken up a project to build a board as a CDMA baseband
> > receiver. Basically I am planning to use an Altera FLEX10K device to
> > implement it. A question I encountered is that how to build a Digital
Matched
> > Filter in FPGA. (Maybe about 256 taps or more? Is this parameter too
> > difficult to realize?) I think the big barrier is that how to realize the
> > high-speed  parallel adder. (The chip rate is about 4M cps. The sample rate
> > for acquisition is 4M sps too.)
> >
> >   Could anyone give me some hints on this? Any help is greatly appreciated.
> > :) Thanks in advance.
> >
> > Forest Niuman
> > niuman@263.net
> >
> > -----------== Posted via Deja News, The Discussion Network ==----------
> > http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15616
Subject: Re: How to implement Matched Filter in FPGA?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 21:40:11 -0500
Links: << >>  << T >>  << A >>
Let's start from the top.

Is there a specific Altera device you need to target?  What is the precision needed
on the coefficients?  Do you really need 256 taps (probably do, since it is a
matched filter), is there symmetry that can be exploited?  As I mentioned before, a
12 bit 250 tap filter would just  about fit the logic in a 10K50E (assuming 12 bit
coefficients too), but you'd likely run into routing problems unless you went to a
larger part.  With the 10K50E, you could probably eek out 8MSPS in a -1 part if you
got it to route or if you gave some bits in the coefficients.  Going to less bits in
the input allows you to crank up the data rate (the design I talked about earlier
runs the data through bit serially at about 100M bits/sec), but really doesn't do
much for the complexity.  In the extreme case where you only have a bit or two of
input, it really starts to look more like a bit correlator.  At that extreme, the
multiplications disappear, so a different approach may be warranted.

Out of curiosity, what type of environmental limits are forcing a selection of
Altera?


> Because of some environment limits, I can only use the Altera device now.
> If I would like to simplify the implementation, such as reduce the sample
> data width to 6 bits or 4 bits,(Or to an extremeness, reduce to 1 bit,
> but the sample rate should rise to 8M sps.)what do you think about it?
> Is it much more simple to realize?
>
> Thanks with my heart again.
>
> Forest Niuman
> Niuman@263.net



Article: 15617
Subject: Re: How to implement Matched Filter in FPGA?
From: mushh@jps.net (David Decker)
Date: Sat, 03 Apr 1999 05:40:43 GMT
Links: << >>  << T >>  << A >>
You can see a floorplan for a matched filter in a XC4028EX at the
fliptronics site: http://fliptronics.com/gallery.html
This chip has one 256bit by 8 equivalent shift reg with taps every
other sample, and with matches against two codes being run
simultaneously. This means there are two sets of everything  except
the shift register. The coefficients (all + or - one) are dynamically
programmable by shifting in two new arguments up to 128 each. 
The clock rate is 32M. The sample rate is 8M. The chip rate is 4M. 

This is surly one floorplan for the record books. There is about 60k
gates of stuff being used here, in a chip the Xilinx book puts at 18k
to 50k. It fits in a XC4025E too (15k to 45k gates). Diablo Research
and Fliptronics collaborated on the architecture, but Fliptronics did
the incredible floorplan.
Dave Decker
Diablo Research Co. LLC
diabloresearch.com

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 15618
Subject: Re: Does any one want to discuss about dynamic configuration?
From: mushh@jps.net (David Decker)
Date: Sat, 03 Apr 1999 05:56:36 GMT
Links: << >>  << T >>  << A >>
"Bourguiba Riad" <bourguiba@ensea.fr> wrote:

>here is my ICQ # 33301195
>
>Riad Bourguiba
>
>

I believe reconfigurable computer architecture is, or was, the main
topic for comp.arch.fpga when it was started. You certainly do not
have to take that topic off line. 

Dave Decker
Diablo Research Co. LLC
diabloresearch.com

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 15619
Subject: Re: How to implement Matched Filter in FPGA?
From: mushh@jps.net (David Decker)
Date: Sat, 03 Apr 1999 06:48:57 GMT
Links: << >>  << T >>  << A >>
You can see a floorplan for a matched filter in a XC4028EX at the
fliptronics site: 

http://fliptronics.com/gallery.html

This chip has one 256bit by 8 equivalent shift reg with taps every
other sample, and with matches against two codes being run
simultaneously. This means there are two sets of everything  except
the shift register. The coefficients (all + or - one) are dynamically
programmable by shifting in two new arguments up to 128 each. 
The clock rate is 32M. The sample rate is 8M. The chip rate is 4M. 

This is surly one floorplan for the record books. There is about 60k
gates of stuff being used here, in a chip the Xilinx book puts at 18k
to 50k. It fits in a XC4025E too (15k to 45k gates). Diablo Research
and Fliptronics collaborated on the architecture, but Fliptronics did
the incredible floorplan. Thank you Philip!



Dave Decker
Diablo Research Co. LLC
diabloresearch.com

Please use only one 'h' in mush. I'm trying to reduce the spam.



"Animals .  .  . are not brethren they are not 
underlings;  they are other nations, 
caught with ourselves in the net of life and time, 
fellow prisoners of the splendor and travail of 
the earth."
Henry Beston -  The Outermost House
Article: 15620
Subject: XILINX CLB architecture
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Sat, 03 Apr 1999 15:55:09 +0200
Links: << >>  << T >>  << A >>
The following are some ideas I got when doing 
a rather area intensive design with XILINX 40150XV/40250XV parts.
My design is quite multiplexer intensive. 
For part of the multiplexers (in this case better a cross point switch,
which can be made from several muxes) I use the TBUS and long lines. 
But this does not work for all of them. 
So I looked for ways to implement multiplexers with few resources.
In the moment I play around with LogiBlox.
I noticed from the figures in the data sheets, that 
each CLB contains a 16-to-1 multiplexer (made from trasnmission gates
as Peter Alfke told recently).
The problem is, that the inputs to them are not accessible.

So my idea is, whether the next generation (after virtex) should made 
another extension to the LUT's capabilities by making (part) of these
muxes available. For instance, use the inputs to the second LUT 
as inputs and make two 4-to-1 muxes from both LUTs. 
Another nice feature would have been cascade chains as found 
in the ALTERA parts. The carry chains are in front of the LUTs
not behind them. Therefore they are not as nice for MUXes.

Furthermore I am curios about the terms used for virtex resources:
A virtex CLB is twice as large as a 4000 CLB, but it consists of two 
slices which are each very similar to a 4000 CLB. 
In addition it seems as the two slices are totally independ (no common 
resources). 
So why are these two slices are are combined into one term.
Do I miss something here?
Andreas
-----------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                 
                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
                        http://www.iti.mu-luebeck.de/RBR/
----------------------------------------------------------------
Article: 15621
Subject: Re: XILINX CLB architecture
From: Ray Andraka <randraka@ids.net>
Date: Sat, 03 Apr 1999 11:16:18 -0500
Links: << >>  << T >>  << A >>
For a multiplexer intensive design, I'd look a bit closer at the virtex
architecture.  Each CLB contains two identical 'slices', each of which has
two 4-LUTs, a 2 bit carry logic and a pair o' registers.  If you look
closely at the CLB drawing, you'll see extra muxes labelled F5 and F6.  The
F5 muxes combine the outputs from the two LUTs in the slice to implement a
4 input mux in one slice.  The F6 mux combines outputs of the F5 muxes from
the two slices so that an 8:1 mux can be implemented in a CLB.  The slices
are grouped into CLBs to reflect the close coupling of the slice pairs
including the F6 mux and the very fast intra-CLB routing.

The carry logic in the Virtex CLB is different than the Xilinx 4000 carry.
The 4000 series has the carry logic in front of the LUTs, probably to keep
from adding the LUT delay to the time to get on the carry chain.  As you
point out, that prevents you from using the carry chain in a cascade mode.
It does however provide the opportunity for some cute circuit tricks for
certain types of functions.  The virtex carry chain follows the LUT, so it
conceivably could be used as a cascade chain for certain functions.  One
caveat is that if you are using the carry chain, the LUT outputs are always
XOR'd with the carry in before going to the flip-flops.  That means you
can't get at the LUT outputs for non-arithmetic stuff if you are using the
carry chain as part of the logic.  An example of where this is a
disadvantage is if you are using the carry chain as part of a first '1'
detector that turns the output on for the most significant '1' bit and all
others off.  Two different architectures, two different sets of advantages
and disadvantages.

Andreas Doering wrote:

> The following are some ideas I got when doing
> a rather area intensive design with XILINX 40150XV/40250XV parts.
> My design is quite multiplexer intensive.
> For part of the multiplexers (in this case better a cross point switch,
> which can be made from several muxes) I use the TBUS and long lines.
> But this does not work for all of them.
> So I looked for ways to implement multiplexers with few resources.
> In the moment I play around with LogiBlox.
> I noticed from the figures in the data sheets, that
> each CLB contains a 16-to-1 multiplexer (made from trasnmission gates
> as Peter Alfke told recently).
> The problem is, that the inputs to them are not accessible.
>
> So my idea is, whether the next generation (after virtex) should made
> another extension to the LUT's capabilities by making (part) of these
> muxes available. For instance, use the inputs to the second LUT
> as inputs and make two 4-to-1 muxes from both LUTs.
> Another nice feature would have been cascade chains as found
> in the ALTERA parts. The carry chains are in front of the LUTs
> not behind them. Therefore they are not as nice for MUXes.
>
> Furthermore I am curios about the terms used for virtex resources:
> A virtex CLB is twice as large as a 4000 CLB, but it consists of two
> slices which are each very similar to a 4000 CLB.
> In addition it seems as the two slices are totally independ (no common
> resources).
> So why are these two slices are are combined into one term.
> Do I miss something here?
> Andreas
> -----------------------------------------------------------------
>                         Andreas Doering
>                         Medizinische Universitaet zu Luebeck
>                         Institut fuer Technische Informatik
>                         Ratzeburger Allee 160
>
>                         D-23538 Luebeck
>                         Germany
>
>                         Tel.: +49 451 500-3741
>                         Fax:  +49 451 500-3687
>                         Email: doering@iti.mu-luebeck.de
>                         http://www.iti.mu-luebeck.de/RBR/
> ----------------------------------------------------------------



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15622
Subject: Re: Schematic Capture & FPGA synthesis
From: Joon Lee <joon.lee@quantum.com>
Date: Sat, 03 Apr 1999 14:57:10 -0500
Links: << >>  << T >>  << A >>
Check out:

www.optimagic.com/lowcost.shtml

Lots of goodies, from free to under 1K.

Joon Lee
Quantum Corp.


Evan Samuel wrote:

> I'm looking for an affordable package for schematic capture, VHDL systhesis
> & FPGA systhesis.  I work at home and do not have the resources of a large
> company.  If any one can help me identify any sources please reply to the
> post or email: evansamuel@earthlink.net.
>
> Thanks,
> Evan Samuel



Article: 15623
Subject: Re: How to implement Matched Filter in FPGA?
From: Joon Lee <joon.lee@quantum.com>
Date: Sat, 03 Apr 1999 15:07:32 -0500
Links: << >>  << T >>  << A >>
I have a rather dumb question,  not being an expert in this area.
Would a, say 16 TAP IIR filter, be considered as an alternative to the 256 FIR ?
FIR's are characteristically exploited due to their mathematical simplicity
(plain convolution), their inherent stability and linear phase transfer
function.  Long FIR are not very desirable due to the long group delay, i.e. the
time it takes for the first output to appear due to the first input.  This
generally is about (N+1)/2, where N is that tap number.
The IIRs on the other hand requires a little attention with the stability,
especially in fixed-point environment.  The transposed-canonical form II types of
implementation are one of the the most stable.  The phase relationship, of course
would match the analog filter's transfer function which it was "copied" from.
Despite all this, IIR, due to the feedback, are orders of magnitude better
performing than the FIR counter part.  For instance a 16 TAP IIR would "equal" a
256TAP FIR in the transfer function magnitude.

Just a thought

-Joon Lee
Quantum Corp.

batman2054@my-dejanews.com wrote:

> Hello,  I have taken up a project to build a board as a CDMA baseband
> receiver. Basically I am planning to use an Altera FLEX10K device to
> implement it. A question I encountered is that how to build a Digital Matched
> Filter in FPGA. (Maybe about 256 taps or more? Is this parameter too
> difficult to realize?) I think the big barrier is that how to realize the
> high-speed  parallel adder. (The chip rate is about 4M cps. The sample rate
> for acquisition is 4M sps too.)
>
>   Could anyone give me some hints on this? Any help is greatly appreciated.
> :) Thanks in advance.
>
> Forest Niuman
> niuman@263.net
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



Article: 15624
Subject: Re: IP cores and software industry
From: Joon Lee <joon.lee@quantum.com>
Date: Sat, 03 Apr 1999 15:13:00 -0500
Links: << >>  << T >>  << A >>
>

To add onto Jamil's list of links, here another one:

http://www.cmosexod.com (not an inappropriate site)


> Iif you like to join me please send me an email so as to organize our
> selves with other people on the net

Sign me up for it !

-Joon Lee
Quantum Corp.


Jamil Khatib wrote:

> It seems that there are lot of people interested in the idea of free
> hardware cores just like me.
>
> I have lot of links on IP cores and free circuit project at my site at
> Links to IPCores
> http://www.geocities.com/SiliconValley/Pines/6639/ip/
>
> free circuit projects
> http://www.geocities.com/SiliconValley/Pines/6639/freecir/free_circuit.html
>
> I also try to contact those people who like this idea in order to
> establish a project that can design both hardware cores and software
> tools.
>  if you like to join me please send me an email so as to organize our
> selves with other people on the net





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search