Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 16325

Article: 16325
Subject: High Speed Reconfigurability, Re:
From: "Italian Cowboy" <gmeardi@geocities.com>
Date: Sun, 16 May 1999 17:21:53 +0200
Links: << >>  << T >>  << A >>
Personally, I'm working on dynamic reconfiguration (PoliMorph Project,
Politecnico of Milan), i.e. exactly what you guys are talking about. Despite
the loads of projects in this promising field, though, I always notice that
everybody neglects what I deem the most important problem of all.
Steve himself pointed out that "the SW IS the computer", but maybe he forgot
the implications: the biggest hurdle here is *not* the reconfigurable array
(today's Xilinx could already provide us with outstanding results, were we
able to use them fully), but a suitable and overall automatic way to take
advantage of the beast.
I mean, everybody can imagine a computer that goes on reconfiguring the FPGA
on the fly and boosting performance like crazy, but as long as we don't have
a sort of compiler that gets a standard C++ code or whatever and understands
what portions of the code are to be implemented in Hardware and how, our
vision will just remain what it is... a vision.
That's why we at the Politecnico are working on the compiler better than on
hardware issues:
right now we already have a way to identify (in a standard C code)
interesting portions (we called them MISO, for Multiple In Single Out, since
they are kind of a generalization of a "normal" RISC instruction, where you
have a number of input operands but just one output), we have a way to
assess their value (GAIN heuristic, Gross Advantage INdex), and we're
developing a genetic algorithm that, working on the Control Flow Graph and
considering reconfiguration penalties, substitution policies and so forth,
decides which MISOs should be implemented in hardware for real (GENIUS,
GENetic Identification of Useful Superinstruction).
It's REAL tough, I'm telling you, and that's why I'm all too convinced that
here lies the S. Graal of reconfigurable computing.

Remember, Steve, "the software IS the computer"...

Aside from that, you can find info about DPGAs in the MIT web site: it was
DeHon's PhD Dissertation.


Guido Meardi







Article: 16326
Subject: suche caddy15 von ziegler informatics für studium
From: "Susanne Müller" <susannemuller99@hotmail.com>
Date: Sun, 16 May 1999 18:22:26 +0200
Links: << >>  << T >>  << A >>
Bitte unter susannemuller99@hotmail.com melden



Article: 16327
Subject: Re: Trade-In Offer - ABEL, MINC & Synario Users in Europe
From: Steve@s-deweynospam.demon.co.uk
Date: Sun, 16 May 99 17:18:25 GMT
Links: << >>  << T >>  << A >>
Oh no, not again...

I'll just repeat my personal experience with CUPL, but first some questions for
Euro-EDA: 

Why did Stag Programmers stop importing it into the U.K. ? 
Why did Microcall stop retailing it in the U.K. ?

In article <fGIc7EA27uO3Uw3q@czar.co.uk> info@euro-eda.com "info" writes:
> 
> The new 32-bit version of CUPL allows design entry by schematics,
> graphical state diagrams, high-level equations or VHDL and includes
> powerful design simulation and partitioning capability. CUPL provides
> comprehensive support for many leading programmable device technologies
> and manufacturers.
> 
How extensive is the VHDL support, is it the '87 or '93 varient ?
Can it partition a design into two Altera 10k20's ?
What formal agreements do you have with the PLD vendors ?
What predefined LPMs/Logiblox type macros do you supply ?
	-any multipliers or counters, for instance ?
Is there in fact any support for hierarchy at all ?
	-any ability to call a pre-defined function and pass parameters to it ?
How do you support RAM in Altera Flex or Xylinx 4K devices ?
Can you define counters automatically without the pre-processor defining a
state for EVERY counter value ?
Can you guarantee that every example in your documentation will compile ?
Can you nest the $REPEAT structure ?

Here is my experience, as posted here in May 1998, with comments from an 
ex- Logical Devices employee :


Well I am a pissed off ex-employee of Logical Devices, I was a software engineer on
the CUPL package, and here are my views of the Product (Fairly good) and the company
(You will want to read this section).


xxx  wrote:

> In article <6jvgs7$ngc$1@gte1.gte.net> jflan@gte.net "Jim Flanagan" writes:
>
> > I would appreciate anyone's opinion on Logical Device's CUPL software
> > for designing GALS,etc.  I'm not a big user of PALs, but from time to
> > time I use one for various projects and have been using the freeware
> > PALASM.  I've been thinking of using CUPL (I have the free starter kit)
> > and was curious as to the opinions, good or bad, concerning this tool.
> > Thanks.. Jim
> >
> >
> CUPL is complete bollocks. Here's why (from memory of V4.7 circa 1996) :
> (points 8 to 11 are the killers for serious design)
>
> 1.      We ordered Total Designer back in 96. Received 4.6, followed after
>         some complaints by 4.7.

You definitely will not get a free update if you don't complain.

> 2.      Documentation was crap. Examples in the documentation did not compile.
>         Information spread over about 6 different manuals.

You are right, the documentation that was shipped with the product was basically a
collection of 13 manuals, thrown into 6 manuals.  The only book you really needed
was the Universal Compiler for Programmable Logic Manual (The big book).  While it
was poorly written, it did contain all the information needed to use the program,
and all the common problems people would call me about.  (Such as the most common
complaint, the range "bug" ... Range Addr = [addr14..18]; CS = Addr:'h'F --- My
signals are completely removed.)

In version 4.8/4.7 all the examples compiled, as long as you didn't select Best for
Polarity and Quine McClusky, some others needed a option set.  The memory management
in the product was terrible.  It was designed around a DOS platform and was never
really made it to windows status.

In version 5.0 (I don't know if they have released that one yet...) Everything
compiles with any option.  I know because I had the mundane task of doing it.  They
may not have fit into the device with some options set, but they did not crash the
compiler

>
>
> 3.      Messages when a design had failed to fit were unclear.

If you were targeting a device handled internally, the messages were usually enough
to fix the problem, if you were using a device that required an external fitter,
that is a real pain.  It just seems that Silicon Vendors did not design the Fitters
with the thought of connecting them to a Windows Application and receiving error
messages correctly.  For the Companies that did design Windows Fitters - other
priorities at LDI prevented implementing the code modifications that would allow
CUPL to call them.  But I agree 0011ck - Failed to fit device  - is a very bad
message.

> 4.      Total Designer was supposed to ship with a device finding utility that
>         would find the smallest device that would fit your design. But it would
>         only target small pld devices.

We told marketing to remove that claim a long time ago, and we told all of the sales
men to stop selling the package based on that utility (Do either of these
departments ever listen?).  The source code for that program was lost before I
started working there.  If the user spends 40 hours or so in the setup phase of the
program, he can add all of the variables required to select larger devices. (It just
is not worth it - It is an old DOS based utility)

> 5.      Supposed to ship with a partitioner to split large designs to fit into
>         small chips. Again, only capable of targetting PLDs

The emergence of CPLD obsoleted this product from a marketing point of view.  There
was just no reason to advance this product, but marketing also decided that we still
needed to ship this with the package.  Again, the uses can spend about 100 hours to
set up this program to work with CPLDs

> 6       This is despite the CUPL brochure showing fitting to FPGA & CPLD after
>         partition. [for what it's worth this is a non issue; who uses
>         partitioners when e.g. Altera make it so easy to just step up a family?]
>

Boy I really love a when you need to look in the latest EDN to find out what the
product is supposed to do.

> 7       One of the reasons we brought CUPL was that it claimed to be able to
>         target most manufacturer's devices. In practice, you have to design to
>         the target macrocell architecture in such detail that you have to choose
>         your device family before you begin. No chance of moving from Vantis
>         CPLD to Xylinx FPGA when the design gets too big.
>

Not true.  You can do it, it just is not efficient.  A MACH221 design will fit into
a XC4020 I guarantee it(ha ha) .  CUPL is a Sum of Products compiler, not good for
FPGA architecture if you use any advanced functionality of the CUPL language.  A
normal 5 PT equation will take one register in a CPLD.  In an FPGA it will take up
to 5 times the number of signals on the and term divided by 4 or 5, depending on the
architecture, cells.  Of course you can usually rewrite these equations to work with
FPGA architecture, but look at the inability to get windows fitters integrated and
you can wonder how long it will take to actually make these core changes to the
internal data structures of the program.

Going from Atmel ATF1508 to MACH device or Xilinx 95XX you really did not need to
change the code.

> 8.      The way you implement counters is very messy; you have to implement a
>         state machine with a state for every counter state if you do not want
>         to wire it up by hand. This means that a 8 bit counter generates 256
>         explicit state declarations after the pre-processor has run. 10 bits is
>         the limit - it won't accept more than that.
>

I agree here, at logical the other CUPL software engineer was working on added the
signal = signal +1 for counters, but never finished it.

> 9.      No concept of hierarchical design. You can define a few macros and
>         include files, but that is it.
>

I don't know how many times I made statements that you NEED this functionality to
compete.  But I guess my opinion was not worth the bosses time.

> 10.     $REPEAT ... $REPEND cannot be nested.
>

I think this was corrected in version 4.8 but I could be wrong.  Stupid me forgot to
steal copies of the software they produced so I can not test it.

> 11.     A design of ours with about 10 8 bit counters _always_ crashed the
>         compiler with no sensible error message.
>

I don't doubt it ... another one of those fun memory errors.

> 12.     We sent back the CUPL package as being "Unfit for Purpose". After
>         our lawyers got involved, and the reseller attempted and failed to
>         demonstrate correct operation of the software, the reseller accepted
>         our position. The reseller subsequently ceased selling the software.
>

You are lucky, if you would of bought it directly from LDI, you never would have
gotten your money back.

> 13.     We would have purchased "Keep Current" maintenance. I noticed on their
>         web site several months ago that they had recompiled for 32 bit. Even
>         those on maintenance were expected to shell out US$ 300 (instead of
>         US$ 600) for the upgrade.
>

I never did agree with the bosses idea of how to market software.  I do believe if
you had the maintenance, you should get the software free.  The end users do not
care that you had to contract outside of the company to find somebody who could
convert the code to 32-bit, and then care even less that the boss personally lead
the development team for the Visual Basic front end.

> 14.     The fitters that came with it seemed to be mostly those that you could
>         get free or very cheaply from the manufacturers.
>

The were all free from manufacturers.  We did not have agreements with any of the
Silicon Vendors.

> 15.     I gained the impression, judging from the limitations and the way that
>         it was only the front end that seemed to get updated that this is one
>         of those cases where the person who wrote and understood the software
>         left many years ago, and it is only momentum and marketing b*****t
>         that keeps it going.
>

If you are referring to CUPL 5.0 - all of the DLLs went to 32-bit, and the memory
errors are for the most part gone.  You can compile a large design, and it may take
10 hours, but it will compile.  As far as the front end is concerned.  I wish I had
a tap in the office of all the engineers who bought it when they get the Visual
Basic Run-Time Error message. (See below)

> Compare functionally to Altera's MaxPlus, their AHDL language and completly
> wonderful Library of Paramterised Megafunctions. A vastly superior product,
> even if it does tie you into their devices. However they produce a wide range,
> and as I stated above, migrating from one family to another can be as simple as
> changing the device assignment.
>
>
> Let the flame war begin...
>
>

The following is a re-post of what the ex-LD employee stated :

I would just have to say that CUPL is one of the best programs for targeting simple
PAL/GALs, It is all right for targeting CPLDs, and great for creating "Black Boxes"
in larger design where the black box designs contain a State Machine or Look Up
Table.  Some people recommend using VHDL for all programmable logic, but there is a
small problem with this approach, it just takes too much time.  Several times at
conferences I would give the example of a simple program in VHDL code, and the
corresponding CUPL code.  The VHDL code is usually 3-4 pages and the corresponding
CUPL code fit onto one page.  Remember here I am referring to Simple GALs and PALs.
VHDL has a place, and under 44 pin devices is not the place.As far as Logical
Devices is concerned >>>>>>>>>>  Here is the Flame about the company

The company is run by a self admitted mad man David xxx.  He wouldn't let me
implement my ideas about network security, so I copied his personal AOL e-mail to
the X-fer drive.  You learn a lot about a person from there personal e-mail.  In one
particular e-mail message he tells his mother that he is losing his memory and it is
starting to scare him.  In another  message he invited a girl from california to
come out to Colorado and she replies that she is only 15 years old, He replies and
says that's OK and makes the offer again.

I took the job at Logical Devices because I had a strong interest in Programmable
Logic, a fairly good Programming Background (Contract work for DOD) and it was an
opportunity to learn.  I had dreamed about programming and working with microchip
since I was a kid.  I admitted that I did not have never programmed in Windows
before and they said they would train me in that field.  I though it was a real
company.  This was a dream job.  As Waylon Jennins said - 'Wrong'.

The second day of work showed me the anger of Davit Mot.  He got involved in a
Yelling match (every other word was f*ck) with the production manager.  That
afternoon the PM quit.  It only took me about 1 month to have him yelling at me, and
1 more month to yell back using colorful metaphors.

The company started selling UV erasers in the early 80's.  They were toy ovens
bought from K-mart with a UV bulb, and a paint job.  They were assembled in Miami by
illegal aliens from Cuba.  Later David got into the Prom programmer market.  And the
company seemed to take off.

When the Allpro 40 was introduced, it was a big hit.  Nobody knows why it was
selling like hot cakes, but the company was now a major competitor in the programmer
market.  This was the high point of the company.  After this point, everything is
down hill. David has delusions of greatness, and thinks he is a King of the empire.
Because of this success he believes that he can do anything a make money.

LDI acquired CUPL from P-Cad and rewrote it generating version 3.0 of CUPL.
Everybody who worked on the program did not know anything about programmable logic
when they started.  Most did not even know how to use structured programming
techniques.  One of the more famous quotes from the original programmers "What would
a real Flip flop do in this situation ... you know a 7474".

When I started with the company in 1995 there was around 60 employees, only 2 in the
CUPL department.  With-in a year the company was down to 30 employees and LDI was
losing money.  David would walk in, take you off a project and place you on a new
project, then the next day would yell at you because you were not done with the
first project.  I was now in the CUPL development team/Technical Support for
CUPL/Webmaster/Network manager/etc...  It was around this time that David decided
that everything that was developed had to be developed using tools and techniques
that he understood.  The new standard for programming language was Visual Basic.
All new programmer software and the new CUPL interface would be designed by David
Mot and modifications and hardware connections would be the programmers
responsibility.  If David did not understand the circuit or Code that you wrote, you
could not use it (David did not like the underscores ( _ ) in C and therefore you
could not use that language.)

Sales really started dropping due to the lack of advertising and most people who
bought a programmer wanted a refund because they could not use the programmer in
Windows 95.  The price David was selling the Allpro 88 at was lower then what it
cost to build it, and 3rd party sales was taking over a majority of the sales
figures.  David would not refund anybody because the money was already spent before
the product shipped.  The accountant for the company (a engineering student) made a
miscalculation and all of the sudden the company was bouncing checks to everybody.
David ended up selling one of his houses to recover from this error.  What does he
expect when he places people who know next to nothing about accounting in the
accounting department.  All of David's assets are purchased from Logical Devices
accounts and he doesn't ever pay the taxes on them.  Boy the IRS would have fun
auditing that company.

By the middle of 1997, the company was down to 1 real hardware engineer, 2 support
engineers for the programmers, 2 software engineers and 2 techs in the development
side.  The engineers were not allowed to talk to the techs.  I was told I had to
implement EDIF 3.0.0 in the CUPL software, but David Mot would not allow me to buy
the IEEE documentation for it because we didn't have the money.  Finally heard that
almost everyone was getting laid off (And I did not make the essential personal list
this time) so I pretty much dropped everything and started playing games at work for
the next 2 day.

When that day came, David came of with the "Idea that would save the company".  He
was going to buy programming Handlers from a company for $60K, and sell them to
programming houses for $150K (If the programming house knew about the Handler
company, they could buy the handler directly from them).  I already had a few
interviews set up and couldn't believe the words I was hearing come out of David's
mouth.  All other development would stop immediately and everybody would be sales
men in this new department.  Monday morning I got into a yelling match with David
and he said maybe it would be better if I wasn't working here anymore and this time
I did not argue, but packed my bags and went to a real job interview.

One engineer at LDI says "We were in the fast food business.  Our job is to provide
food for David's Ego, not build products."  Another engineer of LDI stated that he
thought the company was a money laundering operation for the first 2 years he was
there.

A work of advice for anybody who considers buying Logical Devices products.  Make
sure you purchase it from a Local Sales rep, and make sure that the programmer does
what you need it to do.  Do not expect updates, and you will need to go to court if
you want a refund.  The products they have are decent, but the business practices
and marketing are not. (Bait and switch is very common there).

Well my rant has lasted long enough.  If any other X-employees of LDI read this,
please realize I never had a problem with any other co-worker there so do not take
this personally if you see your quote.



Let the flame war begin...



In article <fGIc7EA27uO3Uw3q@czar.co.uk> info@euro-eda.com "info" writes:

> EuroEDA Limited and Logical Devices Inc. are pleased to announce an
> attractively priced trade-in offer for users of ABEL, MINC or Synario
> wishing to upgrade to V5.0 of the popular, low-cost universal PLD, CPLD
> & FPGA design tool CUPL.
> 
> The new 32-bit version of CUPL allows design entry by schematics,
> graphical state diagrams, high-level equations or VHDL and includes
> powerful design simulation and partitioning capability. CUPL provides
> comprehensive support for many leading programmable device technologies
> and manufacturers.
> 
> Email info@euro-eda.com for full details, or visit the "PLD & FPGA
> Design Software" page of our web site at http://www.euro-eda.com
> -- 
> EuroEDA Limited
> 
> Phone: +44 (0)1933 676373
> Fax:   +44 (0)1933 676372
> Email: info@euro-eda.com
> Web:   http://www.euro-eda.com
> 


Article: 16328
Subject: Verilog PLI website
From: Swapnajit Mittra <mittra@my-dejanews.com>
Date: Sun, 16 May 1999 17:33:08 GMT
Links: << >>  << T >>  << A >>


   Project VeriPage: http://www.angelfire.com/ca/verilog/

   I. What's new ?

   1. Couple of new examples have been added to the
   Free Examples section.
   2. The front page has got a face lift.
   3. A sitemap has been added for easy surfing.

   II. About Project VeriPage:

   This is a free informative site on Verilog PLI
   with a growing number of articles on Verilog in
   general. Although there are few sites available for
   Verilog related information, this is the only site
   in my knowledge, which has been focussed on Verilog
   PLI. It has a number of resources on the subject
   including a FAQ, a tutorial and several examples
   on Verilog PLI. If you are a novice, take a look
   if it can help you in breaking the ice; if you are
   a guru, stop by and impart your knowledge to others.

--
=-=-=-=-=-= 100% pure Verilog PLI - go, get it ! =-=-=-=-=-=
     Principles of Verilog PLI -By- Swapnajit Mittra
     Kluwer Academic Publishers. ISBN: 0-7923-8477-6
     http://www.angelfire.com/ca/verilog/


--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---
Article: 16329
Subject: Altera to Clear Logic Conversion
From: Keyvan Irani <irani@we.mediaone.net>
Date: Sun, 16 May 1999 13:22:44 -0700
Links: << >>  << T >>  << A >>

Hello:

Has any one had any experiences with Clear Logic services to convert
Max7000
devices to Clear Logic ASICs? For low volumes, their price seems very
competitive
but I can't just see how Altera would lose market share to them on their
very
popular MAx7000 devices.

thanks,
K. Irani

Article: 16330
Subject: Re: Synchronizer design?
From: "Alvin E. Toda" <aet@lava.net>
Date: Sun, 16 May 1999 12:35:45 -1000
Links: << >>  << T >>  << A >>
On Fri, 14 May 1999, Mark Summerfield wrote:

> Peter Alfke wrote:
> > Any young engineer who hasn't dreamt up a circuit to overcome metastability,
> > lacks imagination. Any experienced engineer who still dreams of one, has no
> > brains.
> 
> ;-)
> 
> The discussion in that other thread suggests that there are plenty of 
> imaginitive engineers with no brains -- otherwise *why* aren't more
> people asking for metastability parameters?  As Paul Walker has pointed
> out, just about everybody *needs* them, they just don't know (or care?)
> that they need them.
> 
> On the other hand, I know very few engineers of any age who are 
> socialists...
> 
> Mark
> 
> 

The implication is that the socialists have imagination, brains,
and care? I think it's true that many beginning students
have thought about this problem even with multiple clocking (3).
But just as many don't even care and aren't interested in the
basic causes in this problem. They really just want something
that works--never mind why. 

Maybe this is why so many aren't socialists? Problem is that 
metastability problems will come up and bite you-- especially 
for that
engineer that thinks he/she can save a clock cycle by removing
what seems to be an unnecessary flip flop from the design, or
by ignoring metastability parameter changes with new fabrication
processes of piece parts.

--al

###########################################################
Alvin E. Toda              aet@lava.net
sr. engineer               Phone: 1-808-455-1331
2-Sigma          WEB: http://www.lava.net/~aet/2-sigma.html
1363-A Hoowali St.
Pearl City, Hawaii, USA

Article: 16331
Subject: Re: How synthesize tools concern with size of the design?
From: "Austin Franklin" <austin@dark88room.com>
Date: 17 May 1999 01:43:59 GMT
Links: << >>  << T >>  << A >>
<lots of stuff snipped>

I really believe, and am further convinced, it MUST be so much easier to do
datapath with schematics...

;-)

Article: 16332
Subject: Re: Xilinx demo board
From: "Ken Yasui" <yasui149@ainet.oki.co.jp>
Date: Mon, 17 May 1999 11:35:20 +0900
Links: << >>  << T >>  << A >>
If you installed dyna text format documen, lets check "Hardware User Guide".
And sample design will be in next directory
  ${XILINX}/mentor/tutorial
  ${XILINX}/cadence/tutorial

But, M1 does not support XC4xxxA device(OLD device).
So I think you should replace XC4xxxA with XC4xxxE.



Davide Falchieri wrote in message <373AEF3F.167EB0E7@bo.infn.it>...
>Hi,
>  I have bought the Xilinx demo board containing two FPGAs: one XC3020A
>and XC4003A. I haven't received any sample LCA design to try on it: on
>the manual "Hardware.pdf" I found at the Xilinx Web site I'm asked to
>find it in : \xact\examples\core\xchecker directory. 
>I have recently installed a copy of Alliance 1.5 and can't find nothing
>similar: can you tell me where may I find something similar ?
>
>Thank you very much.
>
>Davide


Article: 16333
Subject: Re: Fancy Dram problem
From: bunnyboy@cats.ucsc.edu (bunnyboy)
Date: Sun, 16 May 1999 20:37:05 -0700
Links: << >>  << T >>  << A >>
In article <373C03FF.A9B44850@Sun.COM>, roman pollak
<roman.pollak@Sun.COM> wrote:

> Hi Georg,
> 
> This could be the reason as well. However, do you know any source how
> exactly DRAMS works ?
> Especially about the timing what the dram does to any specific time? 
> I actualy didn't know, after selecting the correct address (ras/cas),
> the dram selects a line and modify only particular bit on the line.
> After this it writes it back to the array. But some how it make perfect
> sense.
> 
> regards roman


good dram site is: http://www.abraxis.com/incr/dram/olmstead.html
it has info about timing and refresh for dram simms.

Brian Parker
Article: 16334
Subject: Glue logic
From: wannarat <ksuwanna@kmitl.ac.th>
Date: Mon, 17 May 1999 13:53:58 +0700
Links: << >>  << T >>  << A >>
-  Glue Logic mean ?
Regard
wannarat  (ksuwanna@kmitl.ac.th)
 
 
 

Article: 16335
Subject: Re: Synopsys DC & Modelsim
From: Alan Fitch <alan@doulos.com>
Date: Mon, 17 May 1999 10:12:03 +0100
Links: << >>  << T >>  << A >>
In article <37370ED0.12DDF8E5@usa.com>, asap <asapd@usa.com> writes
>Hi all,
>
>I'm trying to do a post-synthesis
>simulation with Modelsim EE 5.2,
>using the VITAL lib of my ASIC vendor.
>I keep getting errors that some instances
>do not have one or two generics (e.g.: tpd_c_q_posedge).
>(I do not have errors of missing instances...)
>I don't think there is any error on the top instance
>I apply the sdf file, nor similar things...
>However, I don't know if i produce wrongly the sdf/vhdl files
>from Synopsys DC v1999.05 (I use the SDF v2.1 format).
>Is there any chance that the vendor ASIC VITAL models
>are not 100% VITAL compatible, as mentioned on the
>Modelsim user manual?
>
>Thanks,

I've seen this problem twice at two different customers when we were
running the Design Flow exercise in our Comprehensive VHDL training
course.

The customers both told me that it was a problem with Synopsys writing
out SDF. However I have no proof of this.

Unfortunately as I was on customer sites, I could not take away the log
files. I cannot reproduce the problem back in the office, as we haven't
got VITAL compliant ASIC libraries, so I haven't reported it to Synopsys
yet.

Both the customers had other routes to create SDF files which were then
compatible with Modelsim, which is why I suspect Synopsys. However I
must stress that I have no proof of this, and it is certainly possible
that the respective ASIC libraries were in error.

kind regards,

Alan

P.S. If anyone knows of a VITAL compliant ASIC library that we could use
on our public training courses, we should be eternally grateful!

-- 
Alan Fitch
DOULOS, Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK
Tel: +44 (0)1425 471 223                          Email: alan@doulos.com
Fax: +44 (0)1425 471 573             
**               Visit THE WINNING EDGE  www.doulos.com               **

Article: 16336
Subject: Re: Fancy Dram problem
From: Matthias Monhart <m.monhart@octopus.ch>
Date: Mon, 17 May 1999 11:43:19 +0200
Links: << >>  << T >>  << A >>
Just download the datasheet of the specific ic at the manufacturers homepage
and of some 2nd source vdrams. The timing diagrams helped me most to
understand how they work. The possibilities of vdrams are different to each
other.
Your effect that only particular bits changed might be (if your board has no
electrical problems) that you unintended wrote to the mask register of your
vdram during startup sequence or while attaching all signals. Most vdrams may
be masked, means you can set a "mask register" that only allows to modify
certain bits while all others stay constant during a write cycle. Once set
the mask register keeps its content until reprogrammed.

Matthias



bunnyboy schrieb:

> In article <373C03FF.A9B44850@Sun.COM>, roman pollak
> <roman.pollak@Sun.COM> wrote:
>
> > Hi Georg,
> >
> > This could be the reason as well. However, do you know any source how
> > exactly DRAMS works ?
> > Especially about the timing what the dram does to any specific time?
> > I actualy didn't know, after selecting the correct address (ras/cas),
> > the dram selects a line and modify only particular bit on the line.
> > After this it writes it back to the array. But some how it make perfect
> > sense.
> >
> > regards roman
>
> good dram site is: http://www.abraxis.com/incr/dram/olmstead.html
> it has info about timing and refresh for dram simms.
>
> Brian Parker

Article: 16337
Subject: Re: Synopsys DC & Modelsim
From: Laurens Drost <drost@synopsys.com>
Date: Mon, 17 May 1999 14:31:50 +0100
Links: << >>  << T >>  << A >>
asap, Alan, others,

The Constructs used to write out SDF depend somewhat on the
actual technology library you use, and might depend on the
version of our software. The SDF we write out is 2.1 compliant,
but VITAL level 0 (perhaps 1 as well) has not necessarily a
one on one relationship with the SDF: Your VITAL lib might
not fully support SDFv2.1.

Please send me an email if you require further info.

Kind REgards,
  Laurens Drost


-- 
Laurens Drost                              drost@synopsys.com
Synopsys (Northern Europe) Ltd.      
Imperium, Imperial Way                
Reading RG2 0TD, UNITED KINGDOM       http://www.synopsys.com
     VERA - EDA innovation of the year - EDN magazine
 http://www.ednmag.com/ednmag/reg/1999/030499/05innov.htm
Article: 16338
Subject: Dual Port mem
From: "J. Khatib" <khatib@ieee.org>
Date: Mon, 17 May 1999 16:34:55 +0300
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------8843C82D369D3B65550CEFF0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi
Please is there any problem with this dual port memory VHDL code?
--------------8843C82D369D3B65550CEFF0
Content-Type: application/x-unknown-content-type-vhd_auto_file;
 name="mem.vhd"
Content-Transfer-Encoding: base64
Content-Disposition: inline;
 filename="mem.vhd"

LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQotLSBEdWFsIHBvcnQgTWVtb3J5IGNvcmUKLS0g
OCBiaXQgd29yZCBzaXplCi0tIDI1NiBieXRlIHdpZHRoIAotLQotLSBUaGlzIFZIREwgZGVz
aWduIGZpbGUgaXMgYW4gb3BlbiBkZXNpZ247IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFu
ZC9vcgotLSBtb2RpZnkgaXQgYW5kL29yIGltcGxlbWVudCBpdCB1bmRlciB0aGUgdGVybXMg
b2YgdGhlIE9wZW5pcCBHZW5lcmFsIFB1YmxpYwotLSBMaWNlbnNlIGFzIGl0IGlzIGdvaW5n
IHRvIGJlIHB1Ymxpc2hlZCBieSB0aGUgT3BlbklQIE9yZ2FuaXphdGlvbiBhbmQgYW55Ci0t
IGNvbWluZyB2ZXJzaW9ucyBvZiB0aGlzIGxpY2Vuc2UuCi0tIFlvdSBjYW4gY2hlY2sgdGhl
IGRyYWZ0IGxpY2Vuc2UgYXQKLS0gaHR0cDovL3d3dy5nZW9jaXRpZXMuY29tL1NpbGljb25W
YWxsZXkvUGluZXMvNjYzOS9vcGVuaXAvbGljZW5zZS5odG1sCi0tCi0tIAotLSBDcmVhdG9y
IDogSmFtaWwgS2hhdGliCi0tIERhdGUgMTQvNS85OQotLQotLSB2ZXJzaW9uIDAuMQotLSBV
bnRlc3RlZCB2ZXJzaW9uCi0tCkxJQlJBUlkgaWVlZTsKVVNFIGllZWUuc3RkX2xvZ2ljXzEx
NjQuQUxMOwoKCgpFTlRJVFkgZHBtZW0gSVMKCiAgUE9SVCAoCiAgICBjbGsgICAgICA6IElO
ICBzdGRfbG9naWM7ICAgICAgICAgICAgICAgICAgICAgLS0gd3JpdGUgY2xvY2sKICAgIHJl
c2V0ICAgIDogSU4gIHN0ZF9sb2dpYzsgICAgICAgICAgICAgICAgICAgICAtLSBTeXN0ZW0g
UmVzZXQKICAgIFdfYWRkICAgIDogSU4gIGludGVnZXIgUkFOR0UgMCBUTyAyNTU7ICAtLSBX
cml0ZSBBZGRyZXNzCiAgICBSX2FkZCAgICA6IElOICBpbnRlZ2VyIFJBTkdFIDAgVE8gMjU1
OyAgLS0gUmVhZCBBZGRyZXNzCiAgICBEYXRhX0luICA6IElOICBzdGRfbG9naWNfdmVjdG9y
KDcgRE9XTlRPIDApOyAgLS0gaW5wdXQgZGF0YQogICAgRGF0YV9PdXQgOiBPVVQgc3RkX2xv
Z2ljX3ZlY3Rvcig3IERPV05UTyAwKTsgIC0tIE91dHB1dCBEYXRhCiAgICBXUiAgICAgICA6
IElOICBzdGRfbG9naWM7ICAgICAgICAgICAgICAgICAgICAgLS0gV3JpdGUgRW5hYmxlCiAg
ICBSRSAgICAgICA6IElOICBzdGRfbG9naWMpOyAgICAgICAgICAgICAgICAgICAgLS0gUmVh
ZCBFbmFibGUKRU5EIGRwbWVtOwoKQVJDSElURUNUVVJFIGRwbWVtX3YxIE9GIGRwbWVtIElT
CgpCRUdJTiAgLS0gZHBtZW1fdjEKClRZUEUgZGF0YV9hcnJheSBJUyBBUlJBWSAoaW50ZWdl
ciByYW5nZSA8PikgT0Ygc3RkX2xvZ2ljX3ZlY3Rvcig3IERPV05UTyAwKTsKICAgICAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIC0tIE1lbW9yeSBUeXBlClNJR05BTCBk
YXRhIDogZGF0YV9hcnJheSgwIFRPIDcpOyAgICAgICAtLSBMb2NhbCBkYXRhCgoKUFJPQ0VT
UyAoY2xrLCByZXNldCkKICAgIFZBUklBQkxFIHJlc3VsdF9kYXRhIDogc3RkX2xvZ2ljX3Zl
Y3Rvcig3IERPV05UTyAwKTsgIC0tIGhvbGRzIHRoZSBpbnRlcm5hbCBkYXRhIG9mIG91dHB1
dCBkYXRhCgkKQkVHSU4gIC0tIFBST0NFU1MKICAgIHJlc3VsdF9kYXRhIDo9IChPVEhFUlMg
Wik7ICAJLS0gRGVmdWFsdCB2YWx1ZQogICAgCiAgICAtLSBhY3Rpdml0aWVzIHRyaWdnZXJl
ZCBieSBhc3luY2hyb25vdXMgcmVzZXQgKGFjdGl2ZSBsb3cpCiAgICBJRiByZXNldCA9ICcw
JyBUSEVOCglyZXN1bHRfZGF0YSA6PSAoT1RIRVJTIFopOwoJCiAgICAtLSBhY3Rpdml0aWVz
IHRyaWdnZXJlZCBieSByaXNpbmcgZWRnZSBvZiBjbG9jawogICAgRUxTSUYgY2xrJ2V2ZW50
IEFORCBjbGsgPSAnMScgVEhFTgoJSUYgUkUgPSAnMScgVEhFTgoJICAgIHJlc3VsdF9kYXRh
IDo9IGRhdGEoUl9hZGQpOwoJRU5EIElGOwoKCUlGIFdSID0gJzEnIFRIRU4KCSAgICBkYXRh
KFdfYWRkKSA6PSBEYXRhX0luOwoJRU5EIElGOwogICAgRU5EIElGOwoKICAgIERhdGFfT1VU
IDw9IHJlc3VsdF9kYXRhOwogICAgCkVORCBQUk9DRVNTOwoKRU5EIGRwbWVtX3YxOwo=
--------------8843C82D369D3B65550CEFF0--

Article: 16339
Subject: Re: Glue logic
From: "Peter Schulz" <p.schulz@signaal.de>
Date: Mon, 17 May 1999 15:48:09 +0200
Links: << >>  << T >>  << A >>
means usually some interfacing logic between standard
components (i.e. address decoder between a CPU and RAM, ROM etc.)
This logic "glues" the standard components together.

Peter

wannarat schrieb in Nachricht <373FBD06.206C9860@kmitl.ac.th>...
>- Glue Logic mean ?
>Regard
>wannarat (ksuwanna@kmitl.ac.th)
>
>
>
>


Article: 16340
Subject: Re: Synchronizer design?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 17 May 1999 08:35:09 -0700
Links: << >>  << T >>  << A >>
I started this, so I might as well clarify it.
Maybe I was too subtle and assumed too much.

Many decades ago, before Stalin and Hitler, it was said:

If you are under twenty and are NOT a socialist ( communist ), you have no
heart.
If you are over thirty and still a socialist ( communist ), you have no brains.

That's what I was paraphrasing.
Maybe showing my age, or my European education.
Let's not start a thread about socialism here !!

Peter Alfke
==========================================

Magnus Homann wrote:

> Mark Summerfield <m.summerfield@ee.mu.oz.au> writes:
>
> [...]
>
> > On the other hand, I know very few engineers of any age who are
> > socialists...
>
> I know quite a few who are...
>
> What was your point again?
>
> Homann
> --
>    Magnus Homann  Email: d0asta@dtek.chalmers.se
>                   URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
>   The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html

  

Article: 16341
Subject: 4062XL problems and solutions
From: Bill Kury <wjk@datum-telegraphic.com>
Date: Mon, 17 May 1999 16:16:12 GMT
Links: << >>  << T >>  << A >>
Hi!  I just finished a project using a 4062XL from Xilinx and I would
like to get some feedback on some of the problems that I ran into.  A
little info, this device was running on a 80 Mhz clock with most of the
internals stepped down to 40 Mhz.  Utilization was about 25% of the
device.  Yes, I agree that the part should be smaller but, there will be
more added in the future.  Everything was coded in Vhdl using Aldec
tools and Fpga express.

Problem #1 - Clock enable
  The biggest problem I ran into was routing getting the clock enable to
the logic to slow it down to 40 Mhz.  In order for the clock enable to
work properly, it has to be there in 1 80Mhz cycle = 12.5 ns. I found
that using a bufg or bufgls did not work for especially for the iobs.
The solution for me was to route the problem locally through another
flop by reclocking the clock enable.

Problem #2 - Vhdl and Clock enable
  Has anyone run into the problem where they want to slow the logic in
their design down using a clock enable but have been unable to get the
tools to do what you want?  I had alot of trouble especially with state
machines to get the clock enable routed to the ce pin on the clb.  My
solution was to write my vhdl like palasm (Gack! I know this shows my
age but go easy on me :)) in order to get it to do what I wanted.

Problem #3 - High speed visibility
  This isn't so much a problem but a question to ask how you do it.
When running at high speed internal to your fpga, how do you get
visibility into the device without changing the routing?  I know you can
check the static timing and this will resolve 99.99% of your problems.
What I did was allowed some extra pins on the design to route signals
out to so that I could take a look.  This worked well but, at the high
speeds, routing to pins will change your internal routing delays and
possibly mask the problem.  Are there any other solutions out there?

Bill


--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---
Article: 16342
Subject: Post route simulation: EDIF or VHDL?
From: micheal_thompson@my-dejanews.com
Date: Mon, 17 May 1999 17:16:40 GMT
Links: << >>  << T >>  << A >>
I'm doing a timing simulation on a design fitted to an Altera Max7000
device. I've used Altera's Maxplus2 for routing and have Viewlogic's
tools for simulation.
MaxPlus2 has given me a choice of output files: EDIF or VHDL. And this
therefore gives me a choice of Viewlogic simulation tools: Viewsim
(EDIF) or Speedwaves (VHDL).
So, is there an obvious better choice or should I expect to get
identical results from both simulations?
Right now I am not getting identical or even functionally similar
results so I suspect I have screwed up a bit on my part. What I have
noticed in favour of the VHDL simulation though is that I am getting
run-time messages about set up and hold violations etc whereas the EDIF
runs don't ever specify errors as explicitly. Is this true in general?
Thanks in advance
Mike


--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---
Article: 16343
Subject: Re: Fancy Dram problem
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 17 May 1999 10:58:34 -0700
Links: << >>  << T >>  << A >>
Phil Short wrote in message <373CBABF.768BD300@nospam.ix.netcom.com>...
>Andy Peters wrote:
>> Also register the address bus outputs.  That's a lesson learned the hard
>> way, too.
>
>In general, I disagree with this one.  Setup and hold times for address
>WRT RAS and CAS will generally require extra delay in the asynchronous
>DRAM access cycle.  I suspect that there were better solutions to
>whatever problem that you were trying to solve.  There are, I am sure,
>cases where registering the address lines is a useful technique, but I
>would never suggest this as a general solution.

Now that I think of it, the one time I did not have the address registered
and had problems was when I used a Xicor (async) NVRAM.  The address bus was
muxed inside an Altera EPLD whose output drove the NVRAM.  Only one load and
not too fast, either; I think it was 20 MHz.

>But in any case, I strongly suggest the use of an oscilloscope to
>actually observe the circuit in action.

With the NVRAM circuit, I looked at everything with an HP16500 logic
analyzer.  I had memory corruption even with the write line tied permanently
high.  Address and data lines were settled *weeks* before the read strobe.
The only thing that fixed it was to simply register the address lines.  (And
to look at the timing and make sure setup and hold requirements are still
met.)

-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"Space, reconnaissance, weather, communications - you name it. We use space
a lot today."
-- Vice President Dan Quayle



Article: 16344
Subject: Re: Synchronizer design?
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 17 May 1999 11:04:24 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote in message <37403605.6A3895B@xilinx.com>...
>I started this, so I might as well clarify it.
>Maybe I was too subtle and assumed too much.
>
>Many decades ago, before Stalin and Hitler, it was said:
>
>If you are under twenty and are NOT a socialist ( communist ), you have no
>heart.
>If you are over thirty and still a socialist ( communist ), you have no
brains.
>
>That's what I was paraphrasing.
>Maybe showing my age, or my European education.
>Let's not start a thread about socialism here !!


Time to invoke the Usenet Rule about Hitler: if Hitler is mentioned in a
thread, the thread is dead.


-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"Space, reconnaissance, weather, communications - you name it. We use space
a lot today."
-- Vice President Dan Quayle



Article: 16345
Subject: Looking for VHDL Phase Locked Loop design
From: "mta" <mta@lucid.globalnet.co.uk>
Date: Mon, 17 May 1999 20:05:45 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0033_01BEA0A0.A63BC8E0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

Hi,

Can anyone point me to some VHDL describing a digital phase locked loop?

Thanks

MTA

------=_NextPart_000_0033_01BEA0A0.A63BC8E0
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2014.210" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY>
<DIV><FONT size=3D2>Hi,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Can anyone point me to&nbsp;some VHDL describing a =
digital=20
phase locked loop?</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Thanks</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>MTA</FONT></DIV></BODY></HTML>

------=_NextPart_000_0033_01BEA0A0.A63BC8E0--

Article: 16346
Subject: Re: Virtex based PCI cards
From: Steven Casselman <sc@vcc.com>
Date: Mon, 17 May 1999 13:26:23 -0700
Links: << >>  << T >>  << A >>
We (VCC) will offer a Virtex daughter board
for our HOT2 product in about 6 weeks.
We will sell the HOT2 with a Spartanxl and
daughter board with the V300 for $2K and
the V800 for about $5K. The board has two
buses comming up from the HOT2 board and
2 independent banks of 32-bit SRAM. The
Virtex is in the 240 pin package to keep the
price down. One of the I/O banks is broken
out with various little jumpers so you can play with
the VCCO and input threshold stuff. The 12 pins
from the I/O bank go to a little header for
experimentation. The V300 version will have
1 Meg of Sram and the V800 will have 4 Meg.
The board will have a configuration cache manager
which will support partial configuration as well as
full speed configuration and fast readback.

Keep your eye on the website
http://www.vcc.com
We will make an "offical" announcement
in the near future.

alfred fuchs wrote:

> I've just finished the design of a CompactPCI board (6U) with one Virtex1000
> and two synchronous SRAM-modules (2Mx72). It mainly uses rear-panel-I/O
> (more than 100 signals) and is therefore open for various applications. The
> PCI-IF is a PLX9054, the FPGA is configured by the PCI-master.
> Pricing is TBD, but we tend to be expensive.
>
> Alfred Fuchs
> Siemens Austria
> PSE PRO LMS2
> +43/1/1707-34113
>
> Atif Zafar schrieb:
>
> > Hello:
> >
> >     Does anyone know of any development boards (PCI) that use the Virtex
> > FPGA? I am interested in a board with preferably several XV800 or XV1000
> > devices along with RAM for prototyping a custom graphics pipeline. I
> > have heard of the PCI Pamette board, but to my knowledge this does not
> > have Virtex silicon. Thanks for any info.
> >
> > Atif Zafar
> > Regenstrief Institute
> > Zafar_A@regenstrief.iupui.edu

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 16347
Subject: Re: Synchronizer design?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 17 May 1999 23:27:02 -0400
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
...snip...
> Luckily, most asynchronous interfaces do not run at a 200 MHz clock rate.
> Whenever they do, watch out!  Asynchronous interfaces are often between slower
> peripherals running at inherently more modest rates, where metastability has
> become less of an issue.
...snip...
> Peter Alfke, Xilinx Applications

I have been away from the group for a couple of months. My new (now my
former) ISP couldn't seem to figure out how to provide posting to
newsgroups. 

I thought that this issue had been thoroughly beat to death a couple of
months ago. It would appear that all the same people are posting about
it again. 

I recall that Peter posted enough information for everyone to agree that
unless you were running very fast (>50MHz) asynch signals into a very
fast clock, you had little to worry about even without the standard two
FF synchronizer. But by adding the two FF synchronizer, you were
protected until the Y3K problem rose it's head. 

Am I remembering correctly?


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.
Article: 16348
Subject: Re: Synchronizer design?
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Tue, 18 May 1999 07:54:38 +0200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> I started this, so I might as well clarify it.
> Maybe I was too subtle and assumed too much.
> 
> Many decades ago, before Stalin and Hitler, it was said:
Besides, it was Kurt Tucholski, who wrote this.


> 
> If you are under twenty and are NOT a socialist ( communist ), you have no
> heart.
> If you are over thirty and still a socialist ( communist ), you have no brains.
> 
> That's what I was paraphrasing.
> Maybe showing my age, or my European education.
In this case maybe the German one.

Andreas

-- 
---------------------------------------------------------------
                        Andreas C. Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                        D-23538 Luebeck Germany

		        Tel.: +49 451 500-3741, Fax: -3687
		        Email: doering@iti.mu-luebeck.de
                        Home: http://www.iti.mu-luebeck.de/~doering 
                             quiz, papers, VHDL, music

"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 16349
Subject: Re: Post route simulation: EDIF or VHDL?
From: yves@px.uk.com (Yves Tchapda)
Date: Tue, 18 May 1999 08:02:15 GMT
Links: << >>  << T >>  << A >>
On Mon, 17 May 1999 17:16:40 GMT, micheal_thompson@my-dejanews.com
wrote:

>I'm doing a timing simulation on a design fitted to an Altera Max7000
>device. I've used Altera's Maxplus2 for routing and have Viewlogic's
>tools for simulation.
>MaxPlus2 has given me a choice of output files: EDIF or VHDL. And this
>therefore gives me a choice of Viewlogic simulation tools: Viewsim
>(EDIF) or Speedwaves (VHDL).
>So, is there an obvious better choice or should I expect to get
>identical results from both simulations?
>Right now I am not getting identical or even functionally similar
>results so I suspect I have screwed up a bit on my part. What I have
>noticed in favour of the VHDL simulation though is that I am getting
>run-time messages about set up and hold violations etc whereas the EDIF
>runs don't ever specify errors as explicitly. Is this true in general?

Hi Mike,
My own advice is to stick with VHDL. When you've placed and routed a
design using MAXPLUS2, you have a choice of VHDL outputs: you can
either select a VHDL output with timing included or you select the
gate-level VHDL with no timing and you backannotate your timing
through the SDF file. the latter is the standard way that I would
recommend if your simulator is VITAL compliant. I use Modelsim and I
do not have any problems. The whole idea of post layout simulation is
to verify that the design is still functinally correct as well as
satisfying the timing requirements. A very important point to note is
that if the static analyser did not report any violation and when you
run your old testbench on the gate-level VHDL, any setup and hold
violation is certainly caused by the way you drive your signals from
your testbench. The way I do it is, if the design samples on the +ve
edge of the clock, I drive signals on the -ve edge from my testbench
and samples the results on the -ve edge as well. This will avoid
violating the setup and hold time of  the registers in your design.

I hope his clarifies your situation

Dr Yves Tchapda
ASIC and Protocol Design Engineer
Power X
England


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search