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Messages from 15575

Article: 15575
Subject: Re: virtex partial reconfiguration
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 31 Mar 1999 09:08:01 -0800
Links: << >>  << T >>  << A >>
In article <3701F050.DCF70028@irisa.fr>,
Steven Derrien  <sderrien@irisa.fr> wrote:
>I was wondering if such an operation requires the download of a whole
>frame to the Virtex  ? It it is the case, this leads to a significant
>reconfiguration overhead ,  (a few hundred microseconds ) Am I right?
>

It's much faster than that. Each Virtex device has a different frame
size with the popular V300 device having a frame size of 672 bits.
Loading just the frame data in the SelectMAP mode (8-bits) @ 50MHz
would only take 1.68uS (672/8*20ns). 

Ed
Article: 15576
Subject: Re: FPGAs with ECL-compatible I/Os
From: Tom Burgess <tom.burgess@hia.nrc.ca>
Date: Wed, 31 Mar 1999 11:49:57 -0800
Links: << >>  << T >>  << A >>
Thanks for the Rockwell link. 

Have you looked at the Maxim 3885? 2.5 GBps  1-16 demux,
Single 3.3V supply, LVDS out, only 660 mW. Price is right, too!
http://209.1.238.246/1st_pages/1905.htm
(via) http://www.maxim-ic.com/Datasheets.htm

One of our major challenges in using this part has been
coming up with a way to sychronize multiple 3885s without
embedded framing information in the data. It's possible, but
not pretty.

NEL Japan has some (relatively expensive) demux parts
good up to 10 GHz.
(slow) http://www.nel.co.jp/uhe/index.html
It looks like they are trying to get data sheets online, without
much success so far.

Here's the GIGA link. Only 622 MBps - too slow for me (same for the
Fujitsu part).
http://www.giga.dk/

As for the Altera LVDS speed question, the data sheet is silent
on this issue but the press release claims 622 MBps, which is
probably much higher than the useful system clock rate of the
chip anyway. 

http://www.altera.com/html/products/apex.html

regards, Tom

Stephen King wrote:
> 
> I have recently been looking at this problem and have come across the
> following devices. Not having used them I can not speak as to their
> suitability or availability.
> 
> GIGA GD16333 4:32 demux
> 
> Fijitsu FMM4005EK 2:16 demux
> 
> Rockwell 5:64 demux ?????
>     www.rsc.rockwell.com/converters/tech_8-64.htm
> 
> Hope that this is of some help.
> 
> If you know of any other integrated solutions to this problem I would be
> interested to know. In addition does any one know how fast the LVDS inputs
> on the Altera 20KE are likely to work?
> 
> Stephen King
> CRL
> sking@crl.co.uk
> 
> Pierre Langlois wrote:
> 
> > All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750,
> > HI116, etc.).
> >
> > With FPGAs able to do process data at such high data rates, the
> > difficulty now seems to get the data to the FPGA.  Level translators are
> > available on the market, but seriously complicate system timing
> > especially if multiple chips must be used.
> >
> > Does anyone know of FPGAs with ECL-compatible inputs?  Any plans to
> > bring some to market in the near future?
> >
> > Alternatively, does anyone have any comments on their experience
> > interfacing FPGAs to fast ADCs?
> >
> > Thanks in advance.
> >
> > ===============================================
> > Pierre Langlois
> > Département de mathématiques et informatique
> > Collège militaire royal du Canada
> > langlois-p@rmc.ca
> > ===============================================

-- 
Tom Burgess
 
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

Email:        tom.burgess@hia.nrc.ca
Office:       (250) 490-4360 
Switch Board: (250) 493-2277
Fax:          (250) 493-7767
Article: 15577
Subject: Re: vcc virtex workbench
From: Steve Casselman <sc@vcc.com>
Date: Wed, 31 Mar 1999 13:07:00 -0800
Links: << >>  << T >>  << A >>
Daryl Bradley wrote:

> I've almost got to the point of giving up trying to ask VCC for advice
> before our lab purchase some of their virtex virtual workbench
> development boards. Hopef ully someone here may be able to help me with
> the following
>
> The Virtual workbench is a stand alone board - does anyone know if cable
> to connect to the pc to download the configuration (sorry not too hot on
> the terminology - that's why we want the boards  - to learn!) are
> supplied, or if not, why type needs to be purchased.
>
> I have also been advised that the foundation software should be one of
> the most appropriate for us to use - any comments on this?
>
> I certainly hope someone can help me as the funding we have has to be
> used very soon otherwise we lose it!
>
> Many thanks for any advice anyone can give
>
> Daryl Bradley

The download cable must be purchased separately.
The board supports  any download cables designed for
use with the Virtex.
--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 15578
Subject: Re: vcc virtex workbench
From: Daryl Lee Specter <daryl_specter@ins.memec.com>
Date: Wed, 31 Mar 1999 13:19:36 -0800
Links: << >>  << T >>  << A >>
Daryl Specter here from Insight Electronics, LAX, USA

The product you are referring to will be available very shortly from both
Virtual Computer Corp in Reseda, Ca, USA as a standalone product, or
additionally from Insight Electronics in the USA, Canada, & Mexico as well
as from MEMEC in Europe.  Insight / MEMEC will be offering the board
standalone as well as coupled with Tools (Alliance Series, if you already
have a front-end tool like Synplify; and Foundation Series, if you need al
the tools to capture and compile a design). that come with the necessary
download cable to load the part.

Daryl Specter
ps: I also find it useful to have the X-Checker cable that Xilinx sells
(Avail throught the same channels) as it is faster when downloading.  The
board also contains a flash memory that you can reporgram in your favorite
programmer (stay tuned, one of the applications being looked at is the
ability to reprogram the flash on board) and will be supported via a web
page soon to be released to the public as a subpage of Insights WEB page
(www.insight-electronics.com)


Daryl Bradley wrote:

> I've almost got to the point of giving up trying to ask VCC for advice
> before our lab purchase some of their virtex virtual workbench
> development boards. Hopef ully someone here may be able to help me with
> the following
>
> The Virtual workbench is a stand alone board - does anyone know if cable
> to connect to the pc to download the configuration (sorry not too hot on
> the terminology - that's why we want the boards  - to learn!) are
> supplied, or if not, why type needs to be purchased.
>
> I have also been advised that the foundation software should be one of
> the most appropriate for us to use - any comments on this?
>
> I certainly hope someone can help me as the funding we have has to be
> used very soon otherwise we lose it!
>
> Many thanks for any advice anyone can give
>
> Daryl Bradley




Article: 15579
Subject: Re: IP cores and software industry
From: Jamil Khatib <mkhatib@Hplanet.planet.edu>
Date: Thu, 01 Apr 1999 00:21:32 +0300
Links: << >>  << T >>  << A >>
It seems that there are lot of people interested in the idea of free
hardware cores just like me.

I have lot of links on IP cores and free circuit project at my site at
Links to IPCores
http://www.geocities.com/SiliconValley/Pines/6639/ip/

free circuit projects
http://www.geocities.com/SiliconValley/Pines/6639/freecir/free_circuit.html


I also try to contact those people who like this idea in order to
establish a project that can design both hardware cores and software
tools.
 if you like to join me please send me an email so as to organize our
selves with other people on the net

Article: 15580
Subject: Re: IP cores and software industry
From: "Alvin E. Toda" <aet@lava.net>
Date: Wed, 31 Mar 1999 11:55:47 -1000
Links: << >>  << T >>  << A >>
On Mon, 29 Mar 1999, Mark Rogers wrote:

> I suspect that ultimately the IP industry will evolve until it very closely
> matches the software industry.  A few power house companies supplying the
> bulk of the IP, weekenders and college students cranking out shareware IP,
> and then some huge open source products being developed over the web.
> 
> Anyway, food for though...
> 
> Mark

Are there any sources of sharware IP now? This sounds like a good idea
for retired people too.

--alvin
Article: 15581
Subject: Re: Schematic Capture & FPGA synthesis
From: Richard Guerin <guerin2@home.com>
Date: Thu, 01 Apr 1999 01:00:18 GMT
Links: << >>  << T >>  << A >>
Evan Samuel wrote:
> 
> I'm looking for an affordable package for schematic capture, VHDL systhesis
> & FPGA systhesis.  I work at home and do not have the resources of a large
> company.  If any one can help me identify any sources please reply to the
> post or email: evansamuel@earthlink.net.


Do you have preferences toward any particular FPGA vendor(s) ?

Article: 15582
Subject: Re: Schematic Capture & FPGA synthesis
From: "Evan Samuel" <evansamuel@earthlink.net>
Date: Wed, 31 Mar 1999 19:23:14 -0600
Links: << >>  << T >>  << A >>

Richard Guerin wrote in message <3702C58A.25A4F025@home.com>...
>Evan Samuel wrote:
>>
>> I'm looking for an affordable package for schematic capture, VHDL
systhesis
>> & FPGA systhesis.  I work at home and do not have the resources of a
large
>> company.  If any one can help me identify any sources please reply to the
>> post or email: evansamuel@earthlink.net.
>
>
>Do you have preferences toward any particular FPGA vendor(s) ?

I have worked with Xilinx, and some with Altera. I, however, do not have a
particular preference.
I was hoping to obtain a schematic capture or VHDL software with portable
outputs to
the FPGA vendors synthesis tools.



Article: 15583
Subject: Reconfigurable Computing
From: Mandeep Singh <msingh@ececs.uc.edu>
Date: Wed, 31 Mar 1999 23:19:31 -0500
Links: << >>  << T >>  << A >>
Could someone please recommend a website or a book for a general
introduction to Reconfigurable Computing?

Thanks

Paul

Article: 15584
Subject: Re: Schematic Capture & FPGA synthesis
From: "Anthony Ellis - LogicWorks" <aelogic@iafrica.com>
Date: Thu, 1 Apr 1999 06:20:49 +0200
Links: << >>  << T >>  << A >>
Actel has the best "free" tools - if you like OTP parts.
Evan Samuel wrote in message <7dtk20$iqd$1@fir.prod.itd.earthlink.net>...
>I'm looking for an affordable package for schematic capture, VHDL systhesis
>& FPGA systhesis.  I work at home and do not have the resources of a large
>company.  If any one can help me identify any sources please reply to the
>post or email: evansamuel@earthlink.net.
>
>Thanks,
>Evan Samuel
>
>
>


Article: 15585
Subject: Re: Reconfigurable Computing
From: "Ian St John" <istjohn@spamcop.net>
Date: Thu, 1 Apr 1999 00:41:07 -0500
Links: << >>  << T >>  << A >>

Mandeep Singh <msingh@ececs.uc.edu> wrote in message
news:3702F3D3.1B4EC598@ececs.uc.edu...
> Could someone please recommend a website or a book for a general
> introduction to Reconfigurable Computing?


www.vcc.com


Article: 15586
Subject: Re: Schematic Capture & FPGA synthesis
From: Ray Andraka <randraka@ids.net>
Date: Thu, 01 Apr 1999 01:23:13 -0500
Links: << >>  << T >>  << A >>
How many designs do you turn around in a year?  If the answer is many for
different clients, you will probably find you'll need to spring for something
that is more mainstream than you would perhaps otherwise need to do.  I
maintain unrestricted licenses for viewlogic and synplicity, plus Altera and
Xilinx tools among others.  I find that using the vendor independent tools
helps with the changing gears from project to project and customer to
customer.  I hate to think of the crossed control keys I'd be getting if I were
using each vendor's capture packages too.

If this is for a hobby or once in a while use, I wouldn't spend the $ on those
tools.  The programs packed in the vendor tools are adequate for occasional
use, and far cheaper.

Evan Samuel wrote:

> I'm looking for an affordable package for schematic capture, VHDL systhesis
> & FPGA systhesis.  I work at home and do not have the resources of a large
> company.  If any one can help me identify any sources please reply to the
> post or email: evansamuel@earthlink.net.
>
> Thanks,
> Evan Samuel



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15587
Subject: Re: virtex partial reconfiguration
From: Steven Derrien <sderrien@irisa.fr>
Date: Thu, 01 Apr 1999 09:44:24 +0200
Links: << >>  << T >>  << A >>
Ed McGettigan wrote:

> In article <3701F050.DCF70028@irisa.fr>,
> Steven Derrien  <sderrien@irisa.fr> wrote:
> >I was wondering if such an operation requires the download of a whole
> >frame to the Virtex  ? It it is the case, this leads to a significant
> >reconfiguration overhead ,  (a few hundred microseconds ) Am I right?
> >
>
> It's much faster than that. Each Virtex device has a different frame
> size with the popular V300 device having a frame size of 672 bits.
> Loading just the frame data in the SelectMAP mode (8-bits) @ 50MHz
> would only take 1.68uS (672/8*20ns).
>
> Ed

Does a frame corresponds to the global reconfiguration of a small area of
the Virtex (CLB logic and Routing), or are there different types of
frames ? For example some frames for routing configuration and some
others for CLB/IOB ?

According to the virtex datasheet, a  XCV300 has a 32x48 CLB matrix, the
whole device needs 1,700,000 bits to be reconfigured, This means that the
"average"
configuration data for a CLB plus routing is 1,100 bit i.e 2 frames.

I I'm not wrong, this is much more interesting than I expected, as I
understood that only a whole column of the Virtex could be reconfigured
at a time ...

By the way ,does someone can tell me about the availability of the JBit
API ?
(Xilinx Web site says Q1 1999) but there is not much informations about
it.

Thank you,

Steven Derrien


Article: 15588
Subject: Re: IP cores and software industry
From: seamang@wmin.ac.uk
Date: Thu, 01 Apr 1999 10:01:24 GMT
Links: << >>  << T >>  << A >>
In article <Pine.BSI.3.96.990331115256.1213A-100000@malasada.lava.net>,
  "Alvin E. Toda" <aet@lava.net> wrote:
> On Mon, 29 Mar 1999, Mark Rogers wrote:
>
> > I suspect that ultimately the IP industry will evolve until it very closely
> > matches the software industry.  A few power house companies supplying the
> > bulk of the IP, weekenders and college students cranking out shareware IP,
> > and then some huge open source products being developed over the web.
> >
> >
> > Mark
>
> Are there any sources of sharware IP now? This sounds like a good idea
> for retired people too.
>
> --alvin
>
There are some, but its rather scattered. The following sites have
some (rather VHDL biased; does anyone know equivalent sites dealing
mainly with Verilog?)
http://www.vhdl.org/vi/fmf
http://umunhum.stanford.edu/PAM-Blox
http://erm1.u-strasbg.fr/db/
http://freecore.com
http://tech-www.informatik.uni-hamburg.de/vhdl/

Is there enough interest to set up a mailing list on this topic?

Graham


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Article: 15589
Subject: Re: HELP NEEDED: FPGA and Neural Networks
From: "De Valck Joeri" <jfdvalck@info.vub.ac.be>
Date: Thu, 1 Apr 1999 13:17:55 +0200
Links: << >>  << T >>  << A >>
I already have those papers, but they are no good. I am looking for a
bitparallel implementation, not bitstream.  All the articles they present
are pretty much all the same :)
Does anyone have experience with this ?

Alex Rast wrote in message <37001f6e@news.nwlink.com>...

>Yes. Check out:
>M. Gschwind, V. Salapura, O. Maischiberger,"A Fast FPGA Implementation of a
>General Purpose Neuron", FPL '94 Proceedings, Springer-Verlag 1994,
>ISBN# 3-540-58419-6
>
>And also see their paper "A Generic Building Block for Hopfield Neural
>Networks with On-Chip Learning".
>
>Indeed, many of their papers, and plenty of other useful references, are at
>
>http://www.vlsivie.tuwien.ac.at/mike/custom-computing.html
>


Article: 15590
Subject: Re: virtex partial reconfiguration
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 1 Apr 1999 08:40:36 -0800
Links: << >>  << T >>  << A >>
In article <370323D8.68D63B6F@irisa.fr>,
>Does a frame corresponds to the global reconfiguration of a small area of
>the Virtex (CLB logic and Routing), or are there different types of
>frames ? For example some frames for routing configuration and some
>others for CLB/IOB ?
>
A Virtex frame contains a sequence of bits that spans the entire height 
of the device with multiple frames per column. 

>According to the virtex datasheet, a  XCV300 has a 32x48 CLB matrix, the
>whole device needs 1,700,000 bits to be reconfigured, This means that the
>"average" configuration data for a CLB plus routing is 1,100 bit i.e 2 
>frames.
>

You're forgetting the IOB configuration and the Block SelectRAM
configuration space as well as configuration overhead.

>If I'm not wrong, this is much more interesting than I expected, as I
>understood that only a whole column of the Virtex could be reconfigured
>at a time ...

To reconfigure all bits in a CLB column including CLB configuration,
LUT equation and routing requires 48 frames.  However you do not need
to write all 48 frames and this can lead to some interesting uses.  

>
>By the way ,does someone can tell me about the availability of the JBit
>API ? >(Xilinx Web site says Q1 1999) but there is not much informations 
>about it.
>

I do not have information on the Virtex version of JBit (AKA JavaBits).
But obviously we have missed the deadline for 1Q99. 

Ed 

Article: 15591
Subject: Re: Reconfigurable Computing
From: Michael Barr <info@netrino.com>
Date: Thu, 01 Apr 1999 17:47:57 GMT
Links: << >>  << T >>  << A >>
Mandeep Singh wrote:
> 
> Could someone please recommend a website or a book for a general
> introduction to Reconfigurable Computing?

Barr, Michael. "A Reconfigurable Computing Primer" 
    Multimedia Systems Design, September 1998, pp. 44-47.

Also available online at:

	http://www.netrino.com/Articles/RCPrimer/

Cheers,
	Michael
Article: 15592
Subject: Does any one want to talk about Dynamic Configuration?
From: "Bourguiba Riad" <bourguiba@ensea.fr>
Date: Fri, 2 Apr 1999 00:39:11 +0200
Links: << >>  << T >>  << A >>
Does any one want to talk about Dynamic Configuration?

Here is my ICQ # : 33301195

Contact me.

Riad Bourguiba


Article: 15593
Subject: Does any one want to discuss about dynamic configuration?
From: "Bourguiba Riad" <bourguiba@ensea.fr>
Date: Fri, 2 Apr 1999 00:51:33 +0200
Links: << >>  << T >>  << A >>
here is my ICQ # 33301195

Riad Bourguiba


Article: 15594
Subject: Spam Free ? 3815
From: wddwkq@GetResponse.com
Date: 2 Apr 1999 01:53:59 GMT
Links: << >>  << T >>  << A >>
At Last! A Truly Moderated Safe Email list!
Get your message out to thousands without spamming! Lucrative two tier reseller option.
http://dalesafe.com/index.cgi/AK1433

udhdusuvdtbptxhsdzzcmubswdvifclgmlgplr

Article: 15595
Subject: Re: Schematic Capture & FPGA synthesis
From: Richard Guerin <guerin2@home.com>
Date: Fri, 02 Apr 1999 02:53:07 GMT
Links: << >>  << T >>  << A >>
If you'd like to maintain some sort of vendor independence then the next
obvious question is what do you consider affordable ?

If you're a power user and have a power budget (approx  $12K) ....
IMHO,  Mentor Graphic's Packaged Power suite (Renior, ModelSim, Exemplar
Leonardo Spectrum) is a tough value to beat.

	http://www.packagedpower.com/mgc/
 
Alternatley, I agree with a previous post that Actel presently has the
very best FREE tools ( VeriBest, Synplify-Lite, Designer-Lite ... until
Jan 2000). Checkout:

	http://www.acteldesktop.com/

For other FPGA software links check out:

	http://www.optimagic.com/lowcost.shtml

Article: 15596
Subject: Re: FPGAs with ECL-compatible I/Os
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Thu, 1 Apr 1999 20:37:57 -0800
Links: << >>  << T >>  << A >>
Speaking of high speed serializer/deserializer interfacing to FPGAs...

Can somebody tell me what the Fibre Channel folks were thinking when they
came up with the standard that said that all these little PQFP-64 gigabit
serializer/deserializer chips (e.g., AMCC S2070 and the bazillion clones
thereof) should have 2 ~50MHz clock outputs (with 10 bit encoded parallel
outputs) instead of 1 ~100MHz clock output?  Given that the same 8B/10B
encoding is used with gigabit Ethernet, all the SerDes vendors optimized
their chips for it's 125MHz clock rate and kept the same interface to boot.
Grrrr...

We're going through some effort at the moment to get back to one 100MHz byte
stream.  Since the transmitter side of the SerDes chips want 1 100MHz clock
with a bytewide input, my only guess is that the Fibre Channel guys thought
you'd design something along the lines of:

-- 50MHz dual (parallel) 8B/10B encode of 16 bit data followed by  a simple
mux running at 100MHz.  Since the encoding consumes a significant amount of
logic, presumably it was hard at some point to build a 100MHz encoder but
not so hard to build a 100MHz mux.
-- 50MHz dual 10B/8B decode, and we're just going to assume your system
interface is 16 or 32 bits wide anyway so there's no need to get a 100MHz
clock back.

The deserializers go to some effort to guarantee that commas show up on a
particular clock phase, so I'm tempted to think my guess here is a good one.

---Joel Kolstad



Article: 15597
Subject: Re: Does any one want to talk about Dynamic Configuration?
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 00:46:59 -0500
Links: << >>  << T >>  << A >>
What about it?  I did a paper in '96 on a video processor that used
dynamic configuration for the frame processing.  You can get a copy of
that paper from my web site.

Bourguiba Riad wrote:

> Does any one want to talk about Dynamic Configuration?
>
> Here is my ICQ # : 33301195
>
> Contact me.
>
> Riad Bourguiba



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15598
Subject: Re: Schematic Capture & FPGA synthesis
From: Ray Andraka <randraka@ids.net>
Date: Fri, 02 Apr 1999 00:50:46 -0500
Links: << >>  << T >>  << A >>
Are you sure about that price?  Seems pretty low to me.

Richard Guerin wrote:

> If you'd like to maintain some sort of vendor independence then the next
> obvious question is what do you consider affordable ?
>
> If you're a power user and have a power budget (approx  $12K) ....
> IMHO,  Mentor Graphic's Packaged Power suite (Renior, ModelSim, Exemplar
> Leonardo Spectrum) is a tough value to beat.
>
>         http://www.packagedpower.com/mgc/



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15599
Subject: How to implement Matched Filter in FPGA?
From: batman2054@my-dejanews.com
Date: Fri, 02 Apr 1999 07:15:39 GMT
Links: << >>  << T >>  << A >>
Hello,	I have taken up a project to build a board as a CDMA baseband
receiver. Basically I am planning to use an Altera FLEX10K device to
implement it. A question I encountered is that how to build a Digital Matched
Filter in FPGA. (Maybe about 256 taps or more? Is this parameter too
difficult to realize?) I think the big barrier is that how to realize the
high-speed  parallel adder. (The chip rate is about 4M cps. The sample rate
for acquisition is 4M sps too.)

  Could anyone give me some hints on this? Any help is greatly appreciated. 
:) Thanks in advance.

Forest Niuman
niuman@263.net

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