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Does anyone have any experience developping Spartan solutions using the Memec Design 8250 core? I am currently experiencing difficulty with the core and the Memec tech support people have not replied to my requests for help. The problem am I having is that the 8250 refuses to communicate after a random amount of time. Communication usually last for 5 to 15 minutes and then then dies. Could anyone with experience with this core please contact me at geske@norscan.com. Thank you. Kyle Geske Hardware Design Norscan Instruments Winnipeg, MB CanadaArticle: 16726
Hi, just kidding, we have switched to the EPF6K and so we had the need to programm an EPC1. We decided to buy an Optima Light, manufactured by SMS (now a part of the Data I/O universe). First of all, I had some telephone call with SMS support to ensure the programmer could be used with a notebook running with WIN NT. Okay, this should work, so we bought the programmer. When the device arrived, the documentation told me, that the NT software would be in 'BETA' and that either the programmer driver or the printer driver could be installed (ridiculous, every time you'd like to programm an EPC1, you have to deinstall your printer)... Okay, called the support, got a link to the SMS ftp-Server to download a newer version. This version could co-exist with the printer drivers. But the programming times are incredible. We need about 5 min to programm a EPC1. The *.pof is very quick read, but then the blank check lasts just as long as the programming cycle and then the verification, it's a horror. Series production is not possible with 10 devices / hour :-( On the other hand I tried to program a normal 256KB (PLCC32 device). The result is that every time I start the programming I could reset my PC as the software causes NT (!) to crash completely ... Cu,CSArticle: 16727
Hi experts, I just installed Actel Desktop and it all works nicely except that I can't get Synplify to run - it complains that "the date on your machine appears to have been set back", which is not true! There are no other Synplicity installations on the machine, I followed all the rules for setting up the FlexLM environment strings on my Win95 machine, in fact I've generally been quite a good boy about it all. Actel say it's a Synplicity problem, Synplicity say it's an Actel license so it's not their problem, and I guess that's the sort of grief you get when you use freebie software. Anyone got any bright ideas? Pleeeeeeze? Jonathan BromleyArticle: 16728
-- Jeffrey L. Jensen Jensen Development Office: 303-443-3351 Fax: 303-443-3259Article: 16729
What and where is Leonardo?
David Hawke <dhawke@globalnet.co.uk> wrote in message
news:7j703e$aga$1@gxsn.com...
> You could always use Leonardo to read in the Altera EDIF and then retarget
> towards Xilinx.
> I use this quite a lot when I need a quick (but slightly dirty conversion)
>
> Regards,
>
> David Hawke.
> Xilinx.
>
> Bill Gates wrote in message <7j69in$9nf$1@tourist.gnt.net>...
> >Unfortunately the EDIF that Max+plus gave you uses parts available for
the
> >particular
> >chip family that was selected by the Max tools and the Xilinx part you
want
> >to use
> >does not have the same parts (i.e. AND1 for instance). If you get this
to
> >actually work
> >I would be amazed.
> >
> >If you have the original VHDL code (that is if you didnt use Max's AHDL
or
> >some
> >schematic entry) then I would use that instead by either compiling it in
> >Xilinx or some
> >"better" tool like leonardo or synplicity.
> >
> >Good luck... maybe someone else has a suggestion as to how to edit the
edif
> >file
> >or something to that nature.
> >
> >
> >Vitolo <setel@mx3.redestb.es> wrote in message
> >news:7j0s18$h9b29@SGI3651ef0...
> >> Hi, all:
> >>
> >> I need convert a ALTERA design(MAX+PLUSII) into a XILINX design
> >(Foundation
> >> F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist
into
> >> Schematic Editor of Foundation. I complet the design with the new
> >component
> >> (IBUF, OBUF, pads) and save. When i try export the netlist in a XNF
file,
> >> ihave a error message ("Missing AND1 model or library error") then i
> >export
> >> in a VHD file and have ("Cannot read pin descriptors for AND1") error.
> >>
> >> I want to generate a VHDL file (XILINX Foundation compatible) from a
EDIF
> >> ,or other, ALTERA file. How i can to do?
> >>
> >>
> >>
> >
> >
>
>
Article: 16730Did you pay for the core? If you not then there is an 'LFSR' counter embedded in the netlist that would caused it to stop functioning after the 'LFSR' counter reaches it saturated point. David - Kyle Geske wrote in message ... >Does anyone have any experience developping Spartan solutions using the >Memec Design 8250 core? I am currently experiencing difficulty with the >core and the Memec tech support people have not replied to my requests for >help. The problem am I having is that the 8250 refuses to communicate after >a random amount of time. Communication usually last for 5 to 15 minutes and >then then dies. > >Could anyone with experience with this core please contact me at >geske@norscan.com. > >Thank you. > >Kyle Geske >Hardware Design >Norscan Instruments >Winnipeg, MB >Canada > >Article: 16731
hi, i've installed this on a bunch of machines and got them all working ... although some of them didn't go so smoothly, depending on the machine, what is on it, what was on it, bleah, bleah, bleah. i think i have 4 systems running now with no more than moderately loud 'cussin. a few things to consider: 1. perhaps there's some residual junk laying around from a demo synplicity installation that you may have had. some of these programs (general statement) leave things hidden to make it tamper resistant. if you had some previous synplicity installations make sure you get rid of all the junk it put in, files, registry entries, any junk in autoexec.bat. i don't remember all the details but it sounds like it may be accessing an older license file and it thinks there's been some tampering. if i remember correctly (it's been a few months since i've done an install) it might have to read in the file with a form that pops up. the synplicity part has been the hardest of the desktop packages to install. 2. my systems (except 1) have viewlogic running on it. i think i just appended the synplicity license info to the end of the viewlogic license file which made things go better. perhaps the viewlogic experts can chime in, but iirc they changed the license file concatenation character for multiple licenses in one of the recent versions. i think just putting it all in one file helped me out on 1 or 2 of the installations. 3. which version of designer are you using? i have the full designer licenses but synplicity won't run unless you have the less capable designer lite (which got me you-know-where today). please don't ask me why, i don't know. but i did have to boot of r3-1998 (w/ the patches installed) and then install r3-1998 lite. 4. call or email their technical hotline (tech@actel.com). if you get stuck and need more info, i'll copy the config information from one of my machines and send it over for you to compare with yours. or if you send over exactly what you've done, i can repeat it over here on a machine and see if i can replicate the failure. good luck, rk p.s. i have 3 installations on win '95 and one on win nt. ---------------------------------------------------------------------------- Jonathan Bromley wrote: > Hi experts, > > I just installed Actel Desktop and it all works nicely except that > I can't get Synplify to run - it complains that "the date on > your machine appears to have been set back", which is not true! > There are no other Synplicity installations on the machine, > I followed all the rules for setting up the FlexLM > environment strings on my Win95 machine, in fact I've generally > been quite a good boy about it all. > > Actel say it's a Synplicity problem, Synplicity say it's an > Actel license so it's not their problem, and I guess that's > the sort of grief you get when you use freebie software. > > Anyone got any bright ideas? Pleeeeeeze? > > Jonathan BromleyArticle: 16732
On Fri, 4 Jun 1999 18:26:41 -0400, "David Tang" <dtang@springtidenet.comNOSPAM> wrote: >Kyle Geske wrote in message ... >>Does anyone have any experience developping Spartan solutions using the >>Memec Design 8250 core? I am currently experiencing difficulty with the >>core and the Memec tech support people have not replied to my requests for >>help. The problem am I having is that the 8250 refuses to communicate >after >>a random amount of time. Communication usually last for 5 to 15 minutes >and >>then then dies. >Did you pay for the core? If you not then there is an 'LFSR' >counter embedded in the netlist that would caused it to >stop functioning after the 'LFSR' counter reaches it saturated point. Which presumably counts received bytes, or something like that. Very nice income protection plan that I must remember for future designs - please, Mr Client, don't put that design into production until you paid my invoice and I tell you how to disable the time bomb :-) Jonathan BromleyArticle: 16733
On Fri, 04 Jun 1999 18:28:14 -0400, "Richard B. Katz" <rich.katz@gsfc.nasa.gov.NOSPAM> wrote: >hi, > >i've installed this on a bunch of machines and got them all working ... >although some of them didn't go so smoothly, depending on the machine, >what is on it, what was on it, bleah, bleah, bleah. i think i have 4 >systems running now with no more than moderately loud 'cussin. > >a few things to consider: <snip many good advices> Rich, many thanks for your ultra-prompt response. I have on the machine an ancient version of Synplify that came along with some old QuickLogic tools (that I paid for!) so maybe that's causing the trouble. No Viewlogic here at home - serious lack of $$$$$ ! I have the free Designer from Actel Desktop CD-ROM. I emailed tech@actel.com and was referred to Synplicity tech support in a prompt and courteous response. I emailed support@synplicity.com and was referred to Actel tech support in a prompt and courteous response. =(:-o) As usual when faced with this kind of infinite regress I fell back on comp.arch.fpga which - not for the first time - has come up with the goods. Thanks again. Jonathan BromleyArticle: 16734
Thankyou, Thankyou, Thankyou, Thankyou, :-) :-) :-) :-) Since I have complained in the past about some people who seem to continually spam the news group at the slightest opportunity to promote their products (APS/Richard Schwarz , VCC/Steve Casselman), I felt it would be inappropriate for me to do it :-) Of course, I am planning a bit of a e-news blitz once it is all officially released, in a week or two. I wasted about 4 hours a few days ago, adding the CD-R plus a new hard drive unsuccessfully to one of my machines. Why does this stuff never just go together correctly? Anyway a less ambitious upgrade did result in the creation of a test write and test read of a random CD that was lying around next to my computers. I mailed that CD with a label to you yesterday. You should get it Monday/Tuesday. Please have fun with my offsite backup. I did an install with it, and there was no www related install activity. Any news on U-2000 battery pack? Do you want me to pay for the KBD now, or wait for the battery pack and pay for both? Roberta from Xilinx wanted to send my email to her with your email/phone number to John Cooley. I told her to contact you for permission. This was for closure on the XXX web site that apparently you run, that she wrote about in Cooley's ESNUG newsletter. All the best and have a great week end. PhilipArticle: 16735
Tom and Ray, The EDIF file coming out of Coregen just contains the design itself (no initial values or the initial values are set to zero). That's why the COE file exists. When you run through NGDBUILD (Translate), all of your EDIF files get merged together. NGDBUILD also pulls in other files like the COE file. There is no need to specify this file in a UCF or NCF file. It gets pulled in if it's present in the design directory. After NGDBUILD, you have an NGD file, so run NGD2EDIF, NGD2VHDL, or NGD2VER to get the appropriate structural netlist that you need for functional simulation. This netlist should have all of the initial values for your memories b/c all of your input design files have been merged. Hope this helps... Regards, Hobson Frater Xilinx Applications Tom McLaughlin wrote: > Ray, > Thanks for the help. I did find the INIT property in the edif file, but they > were all set to zero! I have a .coe file with initial values and Coregen > generated the .mif file for simulation with the correct initial values, but > they are not in the edif file generated at the same time. Any suggestions??? > By the way, I am generating a single port RAM for Virtex using Coregen v1.5.2. > Any help would be appreciated. > > Regards, > Tom > > Ray Andraka wrote: > > > The initial values do indeed get passed through the edif file using the INIT > > property. If the initial values are all zero for a particular LUT, then the > > INIT property is not placed on that LUT. If it is missing, then the default > > of all zeros is used. You can see the initial values if you generate a RAM > > component using a COE initial values file. After generating it, go into the > > edif file with a text editor and do a search on the string "INIT". You will > > find lines similar to " (property INIT (string "0f03c0f0"))" which > > correspond to the initial values in the COE file. > >Article: 16736
Jonathan Bromley wrote: > On Fri, 04 Jun 1999 18:28:14 -0400, "Richard B. Katz" > <EngineerR> wrote: > > >hi, > > > >i've installed this on a bunch of machines and got them all working ... > >although some of them didn't go so smoothly, depending on the machine, > >what is on it, what was on it, bleah, bleah, bleah. i think i have 4 > >systems running now with no more than moderately loud 'cussin. > > > >a few things to consider: > > <snip many good advices> > > Rich, many thanks for your ultra-prompt response. I have on > the machine an ancient version of Synplify that came along with some > old QuickLogic tools (that I paid for!) so maybe that's causing > the trouble. No Viewlogic here at home - serious lack of $$$$$ ! > I have the free Designer from Actel Desktop CD-ROM. no problem ... installing cae software is never easy (why is that? and are we supposed to trust the output when it can't install itself cleanly?) so hopefully some of the pain i went through will help. please post your solution whatever it turns out to be as i'm sure i or someone else will hit the problem in the future. yeah, the viewlogic isn't quite free ... and unfortunately it isn't compatible with the full license viewlogic i have at day job, which makes it painful when i bring home schematics. one problem i'll be facing in the near term is when i get the synplicity for xilinx and mix it on the same system as the one from actel. anybody have any ideas on how not to get into a great deal of trouble? with the prices of machines dropping, it almost makes sense to solve a s/w problem with more h/w - 1/2 :-) ---------------------------------------------------------------------------------------------- > I emailed tech@actel.com and was referred to Synplicity tech > support in a prompt and courteous response. I emailed > support@synplicity.com and was referred to Actel tech > support in a prompt and courteous response. =(:-o) quick, patent it, i think you've got a perpetual motion machine! -------------------------------------------------------------------------------------- > As usual when faced with this kind of infinite regress > I fell back on comp.arch.fpga which - not for the first > time - has come up with the goods. Thanks again. no problem and good luck, rkArticle: 16738
As a little piece of advice I recommend to double - check your .pof file. Make sure you set up Mux Plus to compile specifically for EPC1. There is an option in "Global Device Attributes" to do this. By default this option is set to "AUTO", and the software may have other than EPC1 device in mind when it compiles .pof file. I had very similar problem with data I/O programmer which has dissapeared when I recompiled the design for EPC1 part. Hope this helps Leo. Nicolas Matringe wrote: > We have two lots of EPC1 PROMs, one we can program and one we cannot. > Would it be because of a change in the programmation algorithm made by > Altera without notice (I know the PROM makers often do that) ? Or maybe > the lot is defective? > > Maybe an older version of the ChipWriter would do with the old EPC1 ? > > Any help is welcome (we don't want to throw 30 EPC1 away like that) > > Nicolas MATRINGE DotCom S.A. > Conception electronique 16 rue du Moulin des Bruyeres > Tel 00 33 1 46 67 51 11 92400 COURBEVOIE > Fax 00 33 1 46 67 51 01 FRANCE > Mail reply : remove one dot from my addressArticle: 16739
FOR THE BEST FREE TEEN SEX PICTURES VISIT: http://freespace.virgin.net/eric.johnston/freepics.htm yqsgsogybqfqicijfppcqtwkqfjrwoolqhmujvxlwgdphttkytzmvyvtyzvpArticle: 16740
I am looking for RS enc/decoder in ABL or sch format, which is free if it is possible because I need it only for a hobby project. udv CsabaArticle: 16741
Terry Walters wrote in message >I picked up a used 14.4 modem for $5 at Goodwill Computer >Outlet, so I'm doing newsgroups AND email now. We had a 14.4 as our only modem. Bought a cheap 'no-mother-no-father' 33.6 at Hardly Normal superstore. No software, so I used the MS generic set-up. Hooked up to our ISP's 56k number. No speed improvement compared to the 14.4 on the same line. Miss Wonderful figured out it as a 'Maestro', so went to their web site. Downloaded the free software and set it up proper like. Now it runs like the clappers! Go figure. But I digress, welcome back Terry, we missed you. I made sure no-one said anything nasty about you before me. I mean, in front of me. I meant, if something rude was said about you, I was there. No, no, what I mean is .... Regards, David W. Varidel dvaridel@optusnet.com.au http://members.optusnet.com.au/~dvaridel <>< <>< <>< <>< <>< <>< <>< <>< <>< Be wary as you meddle in the affairs of dragons, for you are crunchy and taste good with a side salad.Article: 16742
On Fri, 4 Jun 1999, Ha Young Youl wrote: > Hello. > > I prepare a communication chip design project. > the communication chip functions SDLC, Bus interfacing, queuing. > I anticipate it will need about 40,000 ~ 50,000 gate. > FPGA design will be preceded. > > but final product should be low cost. > I am thinking Custum IC is one of them > > What can I do in order to convert FPGA design to Custum IC design > What do I need .. > or is there another method to be low cost > > help me! > > email to hayy@naracontrols.co.kr This is an interesting question because you seem to be expecting to sell the chip itself rather than a system. Do you have some system house to do beta testing for the part? But if you do systems, then it would make more sense to try to work with a parts manufacturer on a part that you can use. You would beta test the part. But maybe, my concept of "custom IC" is wrong here. BTW, for the part that you want, it seems that there may be some old, 2 micron fab lines that could be used. It's hard to estimate costs unless you can be fairly certain of your sales volume. Some comments follow. It's just my $.02 . Perhaps it might make more sense to do a gate array for the first part so that the chip package and pinout would not change even if you go to a custom chip. You could provide your beta site with gate array parts until the custom chip line would come to production. It seems that FPGA parts might be usefull for special boards for design validation and for your beta site to do some preliminary designs. However, if this is a second source to some standard part, then you would have an array of boards to tryout the part. But your FPGA package would need to conform to the standard unless you could fabricate an adaptor socket to the board. best regards, al toda ########################################################### Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 16743
Hello Kyle, I am an engineer with Memec Design Services in Phoenix and I did the bulk of the development on the XF8250 core. Our Design Coordinator forwarded your email to me last week on Wednesday or Thursday (I'm at home now, so I don't have the exact details in front of me) and I responded immediately. It seems you haven't received my response yet, so I will try again. First off, like all of our cores, the XF8250 does NOT have any sort of "time bomb" embedded within it. There is nothing in the core that stops its functioning after some sort of evaluation period. In my original email to you, I said that I had seen something similar to this with a 3.3V device (4005XL) used on a 2 layer ISA bus board (no ground plane). After a few seconds of operation, the Xilinx's internal global reset, GSR, apparently was activated and the internal logic went back to its reset state. After many experiments with the reset logic, we came to the conclusion that this was not a logic problem, but rather a signal integrity issue. By soldering a hefty ground wire from a couple of GND pins near the Xilinx to some of the ISA bus GND pins, the problem went away. It seems that using a 3.3V Xilinx in a poorly grounded ISA bus environment takes a little care. As I remember, your email didn't have a lot of detail as to the exact nature of the failure, so I asked you a lot of questions. I can't remember my original questions, so here's a new list: What Spartan device are you using? Speed? Package? Can you provide me a timing report (.TWR)? What tools are you using? Are you operating interrupt driven or polled? What baud rate are you using? With what number of data bits, stop bits, parity, etc. are you operating? When the core stops working... how do you get it started again? what is the serial data output pin, SOUT, doing? what is the baud rate generator output pin, BAUDOUT, doing? what is the software doing? Is it stuck in a polling loop or interrupt service routine? can you provide me a register dump? Especially the LSR, MSR, and IIR registers. can you still access the internal registers through the microprocessor interface? If you can email me answers to some of these questions, I will be glad to work with you to resolve this problem. -Rob -------------------------- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesign.com -------------------------- On Fri, 04 Jun 1999 22:32:15 GMT, jonathan@oxfordbromley.u-net.com (Jonathan Bromley) wrote: >On Fri, 4 Jun 1999 18:26:41 -0400, "David Tang" ><dtang@springtidenet.comNOSPAM> wrote: > >>Kyle Geske wrote in message ... >>>Does anyone have any experience developping Spartan solutions using the >>>Memec Design 8250 core? I am currently experiencing difficulty with the >>>core and the Memec tech support people have not replied to my requests for >>>help. The problem am I having is that the 8250 refuses to communicate >>after >>>a random amount of time. Communication usually last for 5 to 15 minutes >>and >>>then then dies. > >>Did you pay for the core? If you not then there is an 'LFSR' >>counter embedded in the netlist that would caused it to >>stop functioning after the 'LFSR' counter reaches it saturated point. > >Which presumably counts received bytes, or something like that. >Very nice income protection plan that I must remember for >future designs - please, Mr Client, don't put that design >into production until you paid my invoice and I tell you >how to disable the time bomb :-) > >Jonathan Bromley >Article: 16744
Visit http://www.jcpsoftware.com to check out a new digital filter design softare package. Download of demo software availabe from this WEB site. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16745
On Sun, 06 Jun 1999 07:31:33 GMT, rob_weinstein@memecdesign.nospam.com (Rob Weinstein) wrote: <snip> > I had seen something similar to this [random failure after a few minutes] > with a 3.3V device (4005XL) used on a 2 layer ISA bus board >(no ground plane). After a few seconds of operation, the Xilinx's >internal global reset, GSR, apparently was activated and the internal >logic went back to its reset state. After many experiments with the >reset logic, we came to the conclusion that this was not a logic >problem, but rather a signal integrity issue. This is interesting. A few years ago I had a similar problem with an ISAbus video capture card I was developing: it worked fine in some PCs, but in others it would stop working from time to time, Eventually the problem was traced to spurious assertion of internal resets in some of the FPGAs I was using (QuickLogic). It appeared that the ISAbus reset line was glitching with such narrow spikes that the rather fast FPGAs I was using were the only devices in the system to see it. I fixed it with a digital deglitcher, but never succeeded in tracing the real cause of the problem. I suspected dodgy logic in the motherboard chipset, but this was never proven. Mine was a 6-layer PCB with real genuine ground planes :-) but all the logic was good old 5V, mostly FTTL apart from the FPGAs.Article: 16746
Rich Walker <rw@shadow.org.uk> writes: > In message <7j2sld$f77$1@nnrp1.deja.com> > micheal_thompson@my-deja.com wrote: > > > Hi > > Does anyone know of bookstores in central London that are likely to > > have a decent selection of this 'light' reading. > > Dillons on Gower Street have some interesting stuff,ISTR... Foyles? Bound to have something worthwhile. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 16748
<micheal_thompson@my-deja.com> wrote in message news:7j2sld$f77$1@nnrp1.deja.com... > Hi > Does anyone know of bookstores in central London that are likely to > have a decent selection of this 'light' reading. The Modern Book Co. in Praed St., Paddington, used to have a good selection of VHDL books. I'd give them a ring first. Leon -- Leon Heller, G1HSM +44 (0) 181 428 7509 leon_heller@hotmail.com http://www.geocities.com/SiliconValley/Code/1835Article: 16749
Hi all
Why buy a Memec 8250 core ?
Look at ftp://ftp.xilinx.com/pub/applications/misc, you'll find a file
named rs-232.zip.
This is an old app note from Xilinx which describes a 8250 core designed
in schematics.
The schematics are included in Viewlogic format. The app note in
postcript format is also
included in the zip file. We have implemented it in a lot of design with
success,
at speed up to 155k bauds.
rs-232.zip :
------------
Longeur M‚thode Taille %comp Date Heure Nom
------ ------ ----- ----- ---- ---- ----
0 Archiv‚ 0 0% 19-02-98 12:09 8250/
0 Archiv‚ 0 0% 19-02-98 12:09 8250/sch/
7371 D‚flatN 2042 73% 29-01-93 10:00 8250/sch/8250.1
13168 D‚flatN 3511 74% 29-01-93 10:12 8250/sch/baud.1
6302 D‚flatN 1790 72% 29-01-93 10:15 8250/sch/busbox.1
2337 D‚flatN 757 68% 30-01-93 09:35 8250/sch/bustri3.1
2508 D‚flatN 799 69% 30-01-93 09:39 8250/sch/bustri7.1
2427 D‚flatN 756 69% 29-01-93 10:04 8250/sch/bustri8.1
5442 D‚flatN 1674 70% 29-01-93 10:13 8250/sch/c16bdp.1
5007 D‚flatN 1584 69% 29-01-93 10:13 8250/sch/c16bdpf.1
3230 D‚flatN 951 71% 29-01-93 10:01 8250/sch/control.1
7436 D‚flatN 2145 72% 02-02-93 15:11 8250/sch/errordet.1
8215 D‚flatN 2382 72% 30-01-93 13:23 8250/sch/interrup.1
8519 D‚flatN 2366 73% 01-02-93 14:47 8250/sch/lcr.1
15067 D‚flatN 3987 74% 29-01-93 10:14 8250/sch/modem.1
4173 D‚flatN 1237 71% 04-03-93 15:40 8250/sch/parity.1
2120 D‚flatN 665 69% 04-03-93 15:34 8250/sch/parityc.1
18762 D‚flatN 5125 73% 18-12-93 13:58 8250/sch/receiver.1
4982 D‚flatN 1295 75% 29-01-93 10:01 8250/sch/rsel.1
3890 D‚flatN 1206 69% 29-01-93 10:14 8250/sch/scratch.1
6622 D‚flatN 1967 71% 29-01-93 10:02 8250/sch/shifter.1
8014 D‚flatN 2377 71% 29-01-93 10:01 8250/sch/uart.1
14798 D‚flatN 4017 73% 29-01-93 10:04 8250/sch/xmit.1
14000 D‚flatN 3866 73% 02-02-93 12:17 8250/sch/xmit_sm.1
0 Archiv‚ 0 0% 19-02-98 12:10 8250/sym/
620 D‚flatN 247 61% 19-01-93 14:38 8250/sym/baud.1
348 D‚flatN 168 52% 28-01-93 10:33 8250/sym/busbox.1
353 D‚flatN 176 51% 30-01-93 09:36 8250/sym/bustri3.1
353 D‚flatN 172 52% 30-01-93 09:38 8250/sym/bustri7.1
353 D‚flatN 175 51% 27-01-93 18:51 8250/sym/bustri8.1
707 D‚flatN 259 64% 20-01-93 13:05 8250/sym/c16bdp.1
709 D‚flatN 259 64% 20-01-93 13:05 8250/sym/c16bdpf.1
1640 D‚flatN 424 75% 27-01-93 18:48 8250/sym/control.1
2391 D‚flatN 598 75% 15-01-93 17:34 8250/sym/errordet.1
1205 D‚flatN 358 71% 28-01-93 20:25 8250/sym/interrup.1
2068 D‚flatN 544 74% 28-01-93 20:49 8250/sym/lcr.1
1475 D‚flatN 407 73% 27-01-93 18:54 8250/sym/modem.1
1464 D‚flatN 400 73% 14-01-93 18:59 8250/sym/parity.1
941 D‚flatN 282 71% 14-01-93 16:36 8250/sym/parityc.1
1869 D‚flatN 481 75% 28-01-93 20:42 8250/sym/receiver.1
1391 D‚flatN 387 73% 28-01-93 20:23 8250/sym/rsel.1
436 D‚flatN 188 57% 21-01-93 15:46 8250/sym/scratch.1
1480 D‚flatN 412 73% 28-01-93 20:24 8250/sym/shifter.1
3091 D‚flatN 784 75% 28-01-93 10:33 8250/sym/uart.1
1454 D‚flatN 415 72% 28-01-93 20:40 8250/sym/xmit.1
1220 D‚flatN 378 70% 02-02-93 16:24 8250/sym/xmit_sm.1
18289 D‚flatN 6162 67% 17-03-93 13:09 8250/tree.ps
0 Archiv‚ 0 0% 19-02-98 12:10 addition/
2912 D‚flatN 697 77% 27-01-93 12:43 addition/txsm.abl
1038 D‚flatN 516 51% 17-03-93 12:25 addition/txsm.cmd
31088 D‚flatN 8748 72% 17-03-93 11:44 addition/txsm.ps
24010 D‚flatN 5148 79% 30-01-93 11:23 addition/txsm_r.ps
31598 D‚flatN 7794 76% 04-03-93 15:43 addition/txsm_sc.ps
0 Archiv‚ 0 0% 19-02-98 12:12 modules/
0 Archiv‚ 0 0% 19-02-98 12:13 modules/sch/
5908 D‚flatN 1721 71% 04-03-93 15:37 modules/sch/ed_app.1
4173 D‚flatN 1237 71% 04-03-93 15:40 modules/sch/parity.1
2120 D‚flatN 665 69% 04-03-93 15:34 modules/sch/parityc.1
17997 D‚flatN 4946 73% 18-05-93 10:52 modules/sch/receive.1
13528 D‚flatN 3660 73% 18-05-93 10:51 modules/sch/transmit.1
12242 D‚flatN 3476 72% 04-03-93 15:43 modules/sch/tx_sm_ap.1
0 Archiv‚ 0 0% 19-02-98 12:13 modules/sym/
2060 D‚flatN 545 74% 03-03-93 12:50 modules/sym/ed_app.1
1464 D‚flatN 400 73% 14-01-93 18:59 modules/sym/parity.1
941 D‚flatN 282 71% 14-01-93 16:36 modules/sym/parityc.1
1539 D‚flatN 417 73% 18-05-93 10:57 modules/sym/receive.1
1370 D‚flatN 391 72% 18-05-93 10:55 modules/sym/transmit.1
1140 D‚flatN 359 69% 03-03-93 12:27 modules/sym/tx_sm_ap.1
0 Archiv‚ 0 0% 19-02-98 12:13 print_ps/
106695 D‚flatN 31972 71% 21-08-95 20:24 print_ps/app_note.ps
39885 D‚flatN 9651 76% 18-05-93 11:02 print_ps/figure3.ps
15974 D‚flatN 4114 75% 04-03-93 15:41 print_ps/figure3a.ps
31598 D‚flatN 7794 76% 04-03-93 15:43 print_ps/figure3b.ps
51688 D‚flatN 12734 76% 18-05-93 11:01 print_ps/figure4.ps
19448 D‚flatN 4954 75% 04-03-93 15:37 print_ps/figure4a.ps
9578 D‚flatN 2594 73% 04-03-93 15:35 print_ps/figure4b.ps
26383 D‚flatN 6494 76% 04-03-93 12:11 print_ps/figure5.ps
18290 D‚flatN 6162 67% 21-08-95 20:25 print_ps/tree.ps
3456 D‚flatN 1056 70% 19-02-98 12:36 readme.txt
0 Archiv‚ 0 0% 19-02-98 12:14 table3_1/
1094 D‚flatN 353 68% 18-05-93 13:54 table3_1/ap_rx_op.bid
14929 D‚flatN 3427 78% 18-05-93 13:54 table3_1/ap_rx_op.lca
15578 D‚flatN 4019 75% 18-05-93 13:54 table3_1/ap_rx_op.rpt
18572 D‚flatN 2266 88% 18-05-93 12:48 table3_1/ap_rx_op.xnf
1753 D‚flatN 516 71% 18-05-93 13:48 table3_1/ap_rx_un.bid
23568 D‚flatN 5337 78% 18-05-93 13:48 table3_1/ap_rx_un.lca
14727 D‚flatN 3881 74% 18-05-93 13:48 table3_1/ap_rx_un.rpt
19246 D‚flatN 2438 88% 18-05-93 12:48 table3_1/ap_rx_un.xnf
1097 D‚flatN 343 69% 18-05-93 13:32 table3_1/ap_tx_op.bid
15042 D‚flatN 3368 78% 18-05-93 13:32 table3_1/ap_tx_op.lca
14038 D‚flatN 3752 74% 18-05-93 13:32 table3_1/ap_tx_op.rpt
17559 D‚flatN 2169 88% 18-05-93 13:29 table3_1/ap_tx_op.xnf
1444 D‚flatN 436 70% 18-05-93 13:43 table3_1/ap_tx_un.bid
20699 D‚flatN 4538 79% 18-05-93 13:43 table3_1/ap_tx_un.lca
14317 D‚flatN 3737 74% 18-05-93 13:43 table3_1/ap_tx_un.rpt
18209 D‚flatN 2317 88% 18-05-93 12:47 table3_1/ap_tx_un.xnf
0 Archiv‚ 0 0% 19-02-98 12:15 table3_2/
0 Archiv‚ 0 0% 19-02-98 12:15 table3_2/sch/
4648 D‚flatN 1311 72% 18-05-93 12:18 table3_2/sch/ap_rx_op.1
7075 D‚flatN 1811 75% 18-05-93 12:08 table3_2/sch/ap_rx_un.1
4331 D‚flatN 1269 71% 18-05-93 12:25 table3_2/sch/ap_tx_op.1
6394 D‚flatN 1698 74% 18-05-93 12:22 table3_2/sch/ap_tx_un.1
0 Archiv‚ 0 0% 19-02-98 12:15 table3_2/sym/
1539 D‚flatN 417 73% 18-05-93 10:57 table3_2/sym/receive.1
1370 D‚flatN 391 72% 18-05-93 10:55 table3_2/sym/transmit.1
------ ------ --- -------
923599 238496 75% 105
------------------------------------------------------------------------------
Thierry GARREL - tga@magic.fr
+----------------------------------------------+
| MATRA Défense Equipements et Systčmes (MDES) |
| 6 avenue des tropiques - BP 80 |
| 91943 COURTABOEUF CEDEX / FRANCE |
| Tel : (33) 1 69 86 85 00 |
| Fax : (33) 1 68 07 03 70 |
| Mail : ceo@matra-des.mgn.fr |
+----------------------------------------------+
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