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Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Rajesh Bawankule (Also Visit Verilog & EDA Page : http://www.angelfire.com/in/rajesh52/verilog.html ) -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16101
VHDL International Users Forum
(VIUF) Fall Workshop Õ99
"Soft-Cores, Reuse and Systems Integration"
Orlando, Florida
October, 1999
First Call for Papers
www.vhdl.org/viuf/conf/viuf99
The VIUF Fall Workshop is a forum traditionally dedicated to enable
engineers to discuss and present their work about all topics around VHDL
design, such as simulation, test, synthesis, modeling and design
experiences.
However, this year, the workshop is devoted to a very focussed matter:
Soft-Cores and Systems Integration. We consider the use of Hardware
Description Languages completely and successfully adopted by the industry
and we want to tackle real design problems faced today when trying to reuse
Soft-Cores (internally or externally) available in different applications,
probably using different CAD flows and target technologies.
The workshop will be composed by classical panel and paper presentation
sessions, together with parallel workshops introduced by a short
presentation, delegates then engage in moderated discussion, exploring the
ideas in the presentation and related ideas, and summarize by the scribes to
present the results in the general closing session.
Topics of interest include, but are not limited to:
Design for Reuse
Test & Functional Verification
Tool Environments and Prototype Systems
Impact on Programmable Logic
Domain Specific Applications
Systems Integration
Emerging Standards
Commercial & Business Issues
Information, Paper Submission and Deadlines:
Prospective authors from all around the world are invited to submit 10-page,
12-point font page in English for evaluation. Simultaneous submissions or
submissions of previously published papers will not be considered for
presentation at the workshop. The first page should include the title,
author(s) identification, author(s) affiliation, and abstract. Electronic
submission in PDF format via the workshop Web page is strongly recommended.
For additional inquires on submissions, please contact the program chair at
the address below.
Serafin Olcoz/SIDSA
olcoz@sidsa.es
Final versions of full papers will be published as two-column, 7-page
papers, workshop introductions will be published as two-column, 1-page
papers, following the IEEE Computer Society Press guidelines. Authors should
include complete address, phone/fax numbers and e-mail address, and
designate a contact person and a presenter. The Program Committee also
welcomes proposals for tutorials, panels, special topic sessions and
hands-on training.
Submission: May 21st, 1999
Notification of Acceptance: June 25th, 1999
Camera-Ready Deadline: July 8th, 1999
Organized and Sponsored by:
VHDL International, IEEE Computer Society (pending)
Co-Sponsored by:
RAPID, DESIGN & REUSE, ECSI, (VSI pending)
Published by:
IEEE Computer Society Press (pending)
General Chair:
Bob Klenke, Virginia Commonwealth University, USA
rhklenke@vcu.edu
Program Chair:
Serafin Olcoz, SIDSA, Spain
olcoz@sidsa.es
Publicity Chair:
Nanette Collins, USA
Nanette@nvc.com
Finance Chair:
Gabe Moretti, VeriBest, USA
gmoretti@veribest.com
Conference Organizer
Lee Wood, MP Associates, USA
lee@mpassociates.com
Program Committee (tentative):
Gauthier Barret Dolphin Integration
FR J. Bhasker Cadence, USA
Massimo Bombana Italtel, IT
Ian Bryant Actel, USA
Steve Carlson Escalade, USA
Praveen Chawla EDAptive Computing, USA
Todd Delong Univ. of Virginia, USA
Steve Drager U.S. Air Force, USA
Phil Dworsky Synopsys, USA
Wolfgang Ecker Infineon technologies, DE
Robert Hurley Doulos, UK
Mark-Eric Jones Rapid, USA
Serge Maginot Leda, FR
Jean Mermet ECSI, FR
Michael McKinney Texas Instruments, USA
Paul Menchini OrCAD, USA
Gabe Moretti VeriBest, USA
Greg Peterson FTL Systems, USA
Ian Philips ARM, UK
Patrick Pype CoWARE, USA
Gabriele Saucier Design and Reuse, FR
Ralph Seepold FZI, DE
Steve Z. Szirom HTE Research, USA
Eugenio Villar Univ. Of Cantabria, ES
Candace Worley Mentor Graphics, USA
Alex Zamfirescu ASC, USA
Altera, USA
VIUF Steering Committee:
Harold Carter Univ. Of Cincinnati
Praveen Chawla EDAptive Computing
Allen Dewey Duke Univerity
John Hines US Air Force
Stan Krolokoski Cadence
Article: 16102Check out Insight $349-$538 for XCV300 http://www.insight-electronics.com/cgi-bin/catalog.cgi?cart_id=6302490.26591&start=0&first=first&supplier=XIL&category=&keywords=xcv300&limit=10 and $1,720 - $2,769 for the XCV800 http://www.insight-electronics.com/cgi-bin/catalog.cgi?cart_id=6302490.26591&start=0&first=first&supplier=XIL&category=&keywords=xcv800&limit=10 We have been working with insight for a while and I can tell you they have VERY good FAEs in the field (and lots of them) that just specialize in Xilinx anything. Together with Insight-Memec they seem to offer the most added value of any of the xilinx distributors. (Just my opinion but Insight FAEs show up and help out where none of the other Distributors seem to show the same commitment to the present AND future --- Once again just my opinion). -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16103
Ray Andraka wrote: > The 8259 controller really isn't very complex. You should be able to roll > your own with relatively little effort. Alternatively, I believe Memec > has an 8259 Core available, although the price may be too high. > > I They have some 82xx cores all for $99, although I don't see the 8259. http://memecdesign.com/cdrom.htm Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16104
Ray Andraka wrote: > You can try memec, I think they may have an 8255 core for xilinx, > although I think it is probably schematics. The 8255 is not very > complicated. You could probably sit down and write one yourself in a > day or two. You'll have to find one of the old PC texts that describe > the detailed architecture of the 8255. > > The 8255 core is $99 (viewlogic foundation vhdl and verilog) http://memecdesign.com/cdrom.htm for details http://memecdesign.com/tr03004.htm -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16105
Jamil Khatib wrote: > Please where can I find Xilinx JBITs classes or they are not free? > > Thanks Email Steven Guccione <Steven.Guccione@xilinx.com> or Delon Levi <delon.levi@xilinx.com> -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16106
Instead of the OTP 17256 PROM for config, I was thinking of using an old 27256 EPROM. This way, an ordinary EPROM programmer could be used, yes? I was also thinking of an uC to translate into appropriate serial sigs. Has anyone done this before? Why the hell don't these manufacturers use standard I2C EEPROM? There has to be a reason! GaryArticle: 16107
Hi, I'm a student and I'm trying to learn about AHDL.
Does anybody know a good book about AHDL and max plus II software??
Thanks in advance (and sorry for my english)
D.Polo
mallacan@teleline.es
Article: 16108Yes, and you don't need a micro to do it. It can be done with a PLD containing an address counter and a simple state machine. I've used a lattice 1032 to do it in the past. Gary Desrosiers wrote: > Instead of the OTP 17256 PROM for config, I was thinking of using an old > 27256 EPROM. This way, an ordinary EPROM programmer could be used, yes? I > was also thinking of an uC to translate into appropriate serial sigs. Has > anyone done this before? > > Why the hell don't these manufacturers use standard I2C EEPROM? There has to > be a reason! > > Gary -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16109
Try support.xilinx.com Best Regards Terry Kirton Morris wrote: > > Does anyone have material or knows where to find material on the > advances in FPGA Technology. Please Email me at trini@wam.umd.eduArticle: 16110
Yes. I actually use the equivalent size RAM for a XC4005XL. See my sig below for details. Simon ========== On Mon, 3 May 1999 19:22:12 -0400, "Gary Desrosiers" <desrosi@pcnet.com> wrote: >Instead of the OTP 17256 PROM for config, I was thinking of using an old >27256 EPROM. This way, an ordinary EPROM programmer could be used, yes? I >was also thinking of an uC to translate into appropriate serial sigs. Has >anyone done this before? > >Why the hell don't these manufacturers use standard I2C EEPROM? There has to >be a reason! > >Gary > > Simon - http://www.tefbbs.com/spacetime/index.htmlArticle: 16111
We have the following problem concerning configuring Xilinx FPGA's (XC4000E): We have a pcb using one main LCA Xc4010 and an additional (optinonal) LCA device, which is only used and mounted in special cases. The devices are configured in slave daisy chain mode by a microcontroller, so the "dout" of the main LCA is connected to the "din" of the optinonal LCA and the other controll-lines (done, prog, cclk) are connected together and routed to one port of the mic. Until now, only the main LCA was placed on the pcb and so the mic saw only one device. However, when you use two devices in chain, the xilinx prom formatter builds *one* program mcs-file. But what we want to have are two independent files, so while the system startup is going on, the mic could decide weather to program only the main LCA, or -when present- build the data stream for the main and the optional LCA on its own and program the both devices. So we would link two independent mcs or binary LCA-files to our mic-code (firmware) Does anybody have an idea how to create the combined bitstream? Thx a lot Rolf Aengenendt _______________________________________________________________ Rolf Aengenendt, Lumino GmbH, Krefeld, Germany fon: +49-2151-8196-76 fax: +49-2151-8196-6676 mailto:raengen@lumino.de internet: http://www.lumino.deArticle: 16112
It is not as easy as just concatenating the two bitstreams. There is information at the beginning of the combined bitstreams that tell the first FPGA in the chain that it needs to continue clocking data after it is done and send the data to the second device. I believe that part of this is the length field in the first bitstream. I would suggest reading the Xilinx databook for your devices in particular the section on configuration and daisy chaining. Xilinx support should also be able to help. By the way, why not just always send the combined bitstream. If done properly the board can be wired so that the first FPGA doesn't care if the second one is there or not, just always spits out the data on the DOUT pin. Your only penalties are the increased time and memory requirements for the case of only one FPGA. Rolf Aengenendt wrote: > > We have a pcb using one main LCA Xc4010 and an additional (optinonal) LCA > device, which is only used and mounted in special cases. The devices are > configured in slave daisy chain mode by a microcontroller, so the "dout" of > the main LCA is connected to the "din" of the optinonal LCA and the other > controll-lines (done, prog, cclk) are connected together and routed to one > port of the mic. > > Until now, only the main LCA was placed on the pcb and so the mic saw only > one device. However, when you use two devices in chain, the xilinx prom > formatter builds *one* program mcs-file. But what we want to have are two > independent files, so while the system startup is going on, the mic could > decide weather to program only the main LCA, or -when present- build the > data stream for the main and the optional LCA on its own and program the > both devices. > > So we would link two independent mcs or binary LCA-files to our mic-code > (firmware) > > Does anybody have an idea how to create the combined bitstream? > -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 16113
Hello, I recently heard of someone who has made a web fitter. You mail your VHDL source to site and the fitted results are returned for a certain FPGA. I wonder if anyone heard about such a possibility for ASICs. You post your VHDL and a synthesis script on a web site and a netlist is returned to you automatically. I guess such a service could be quite profitable, since many small companies cannot afford an Asic synthesiser, because they only use it parttime. Does anyone know about any legal objectives to start a company providing this service ? regards, Peter -- Ir. Peter Beukelman VLSI system designer FEL-TNO Oude Waalsdorperweg 63 2597 AK Den Haag The Netherlands tel. +31 (0)703740375 fax +31 (0)703740653Article: 16114
Gary Desrosiers wrote in message ... >Instead of the OTP 17256 PROM for config, I was thinking of using an old >27256 EPROM. This way, an ordinary EPROM programmer could be used, yes? I >was also thinking of an uC to translate into appropriate serial sigs. Has >anyone done this before? Actually, Xilinx has an app note at http://www.xilinx.com/xapp/xapp079.pdf that does just what you ask - it's called VSPROM, written in ABEL. It targets the XC9536 and uses standard EPROMS. It also uses every macrocell in the 9536. I wrote a similar function in VHDL before I found the Xilinx app. Basically the same thing but with less address bits (I'm also using 27C256 EPROMS). My thing was that I take my system clock (25 MHz) and divide it by four externally (a 74F74) and get a 6-and-change-MHz clock that drives the 9536. What's weird is that it didn't work with the 6 MHz clock and 90 ns EPROMS (the configuration would hang, even tho the design was constrained to use a clock of 10 MHz and no timing constraint failures were reported; looking at all of the timing with a logic analyzer showed that it should have worked!) so I ended up using two spare pins and a flop in the 9536 to divide the clock again, and it configures the xc4005 just fine with a CCLK of 3-and-small-change MHz. -- andy ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "Space, reconnaissance, weather, communications - you name it. We use space a lot today." -- Vice President Dan QuayleArticle: 16115
Looking for a feedback of the tools listed above... Any feedback very appreciated. Igor F. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16116
Hello ! I am wondering how is possible to do Multi-cycle path analysis in MaxPlus II or any other design flow for Altera FPGA? How people doing it for Xilinx? Igor F. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16117
For new patents try http://www.patents.ibm.com/ (a truly amazing site) and search on 'FPGA'. Alun Kirton Morris wrote in message <7gikog$b3k$1@dailyplanet.wam.umd.edu>... >Does anyone have material or knows where to find material on the >advances in FPGA Technology. Please Email me at trini@wam.umd.edu > >Article: 16118
I had this brilliant idea (reconfigure on every clock cycle!) that would make me rich etc. but Xilinx have already patented it eg: http://www.patents.ibm.com/details?pn=US05787007__&language=en and also another very detailed patent I've lost the number of (use search on the home page of the above site) Alun Morris 101digital Italian Cowboy wrote in message <7gcmj7$15u$1@aquila.tiscalinet.it>... >I wouldn't mind talking about dynamic reconfiguration (I'm working on it, >actually). > >Guido Meardi > >Article: 16119
Keep up with the latest developments in programmable logic by visiting the 9th Annual Advanced PLD and FPGA conference and exhibition at Sandown Park on 12th May. Visit www.pldconf.com for further details on the conference programme, list of exhibitors and how to register on-line.Article: 16120
mcgett@xilinx.com (Ed Mcgettigan) wrote: >I can't think of an easy way to implement this in a 10K200E since >with two write ports you can't just add another EAB to get the increased >functionality. You could do this if you only needed a write and 2 reads >however. There may be some unique way of implementing this using time >slicing, but it would require extra logic and would surely destroy >your RAM performance by at least 50%. > >On the competitive side (I do work for Xilinx), the Virtex family >supports this function directly in the Block SelectRAMs. The CY7C132 >is a 2Kx8 dual read/write RAM, this can implemented with 4 blocks each >configured as a 2Kx2 with no extra logic. > >Ed that maybe true but it is irrelevant on two fronts. One is I have a board for 10K already and I am not getting the speed I need out of Virtex anyway. I tried v200fg456-4 part with my design and I got only 14.5 MHz with LeonardoSpectrum Level 3 (I don't have Synplify Xilinx mapper) whereas I get 22.5 MHz from 10K100ABC600-1. I need at least 20 MHz on this design. muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 16121
Hi all. I am working on an HDL school project and I am looking for sources for VHDL/Verilog code to use as examples in my project. Some of the types of things that I am looking for are UARTS, Multipliers, FIR Filters. Any help is appreciated.... Please reply to app01@aol.com Thanks, TonyArticle: 16122
Hi, > I am using the latest Altera compiler. Okay, let's have a look at the code: > .... > signal pulse_int : std_logic; > > begin > > pulse_chk: process (clk_0) > variable int_cnt : natural := 0; > begin > if rising_edge(clk_0) then > int_cnt := int_cnt + 1; > if int_cnt < 3000 then > pulse_int <= '0'; > else > pulse_int <= '1'; > int_cnt := 0; > end if; > end if; > end process pulse_chk; > ... > One thing I could imagine is, that perhaps you never use the 'pulse_int' signal in any other process or e.g. use it as an output. Altera compiler is very radical in reducing the logic, so if you generate the 'pulse_int' using the code above and do not use the 'pulse_int' anywhere in your design, the complete (above stated) code is ignored. As the variable 'int_cnt' is able to be counted to values greater 3000 the 'else' clause should execute, otherwise the process wouldn't do anything and would also be reduced to no code... Hope this helps, CarlhermannArticle: 16123
Hi Jeff, Jeff Christenson <jchrist@airmail-not.net> schrieb in im Newsbeitrag: 2E51EB3934753BFD.9E29146E6E814155.D1B5C73BFEC426E4@library-proxy.airnews.net ... > >pasquale wrote in message <371A1D1F.2E618F3C@zoran.com>... > >> > >>My altera flex10k200e design takes about 8 hours to place and route. > >>I needed to change one gate in my design (and inverter to a buffer) > >>and Altera tech support told me I had to start the place and route > >>(i.e. "recompile") from scratch. They said that there was no way > >>to make a minor change like this and that there was no way > >>to directly edit the LUT equations by hand. > >>They say that this capbility may be available by year end. > >> > >>Is this true? Try the 'Smart recompile' option in the Processing menu when in compiler window. This should reduce the compilation time when making minor changes. Works with the 8K and 6K family (as I am working with). The other extreme setting would be 'Total recompile'. Compilation times increases to 3 times in my designes when using 'total' and not 'smart' recompile. Ciao, CarlhermannArticle: 16124
why are you getting such poor performance? Are you bothering to design to the architecture even a little bit? muzo wrote: > that maybe true but it is irrelevant on two fronts. One is I have a > board for 10K already and I am not getting the speed I need out of > Virtex anyway. I tried v200fg456-4 part with my design and I got only > 14.5 MHz with LeonardoSpectrum Level 3 (I don't have Synplify Xilinx > mapper) whereas I get 22.5 MHz from 10K100ABC600-1. I need at least 20 > MHz on this design. > > muzo > > Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email) -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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