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What's the best way to start working with FPGAs? Can it be done for approx
$500 US, or is it impossible to do anything cool without spending alot of
money? Does all of the software run on commercial Unix? Does any of it run
on Win98? If not, Linux would be a bearable alternative. How difficult is
it to program FPGAs? Are there any C/C++ libraries that will allow you to
say, for example... do something like this:
#define REGISTER_WIDTH 56
MyDevice::MyDevice(int iBits)
{
m_pRegister1=CreateRegister(iBits);
m_pRegister2=CreateRegister(iBits);
m_pRegister3=CreateRegister(iBits);
m_pOverflow=CreateRegister(1);
m_pUnit1=CreateAdder(iBits);
m_pUnit1->SetInputA(m_pRegister1);
m_pUnit1->SetInputB(m_pRegister2);
m_pUnit1->SetOuput(m_pRegister3);
m_pUnit1->SetOverflowBit(m_pOverflow);
}
void main()
{
char blah1[7];
char blah2[7];
char blah3[7];
/* initialize blah1 and blah2 with 56 bit integers. */
MyDevice HelloHardware(REGISTER_WIDTH);
HelloHardware.m_pRegister1->SetRegister(blah1);
HelloHardware.m_pRegister2->SetRegister(blah2);
HelloHardware.m_pRegister3->GetRegister(blah3);
/* now do something with the 56-bit integer result in blah3 */
}
Obviously, I'd like to do something more sophisticated than build 56-bit
adders :).
--Steve
Article: 16876
You can get started for quite a bit less. Xilinx sells a student edition for I
think $99. It is crippled in that it is limited in the size device it can
compile. Still, the devices it handles are plenty big to do many things,
especially learn about the device capabilities.
That package has a schematic entry capture tool. While the industry is pushing
hard toward text based entry, lack of knowledge of the device architecture will
not let you exploit the device to anywhere near its potential. I highly
recommend newbies start out with schematic entry and use it until they at least
become comfortable with the device structure and tools and what works and
doesn't work. Once you have that down, then you are welcome to fight with the
VHDL tools to make them do what you've learned is the best implementation for
what you want to do.
BTW, if you are looking at FPGAs for audio processing, the data rates for audio
are so low compared to what an FPGA is capable of, that it usually makes sense
to process the data bit serially (ie one bit at a time). If you do that, you
can get pretty complex circuits for amazingly little logic.
Oh, one more thing. The student kit will not get you a board with the FPGA on
it. For that, I'd recommend Virtual computer's hotworks board. That can be had
for under $1000, and can plug into your PCI bus.
vrml3d.com wrote:
> What's the best way to start working with FPGAs? Can it be done for approx
> $500 US, or is it impossible to do anything cool without spending alot of
> money? Does all of the software run on commercial Unix? Does any of it run
> on Win98? If not, Linux would be a bearable alternative. How difficult is
> it to program FPGAs? Are there any C/C++ libraries that will allow you to
> say, for example... do something like this:
>
> #define REGISTER_WIDTH 56
>
> MyDevice::MyDevice(int iBits)
> {
> m_pRegister1=CreateRegister(iBits);
> m_pRegister2=CreateRegister(iBits);
> m_pRegister3=CreateRegister(iBits);
> m_pOverflow=CreateRegister(1);
> m_pUnit1=CreateAdder(iBits);
> m_pUnit1->SetInputA(m_pRegister1);
> m_pUnit1->SetInputB(m_pRegister2);
> m_pUnit1->SetOuput(m_pRegister3);
> m_pUnit1->SetOverflowBit(m_pOverflow);
> }
>
> void main()
> {
> char blah1[7];
> char blah2[7];
> char blah3[7];
>
> /* initialize blah1 and blah2 with 56 bit integers. */
>
> MyDevice HelloHardware(REGISTER_WIDTH);
> HelloHardware.m_pRegister1->SetRegister(blah1);
> HelloHardware.m_pRegister2->SetRegister(blah2);
>
> HelloHardware.m_pRegister3->GetRegister(blah3);
>
> /* now do something with the 56-bit integer result in blah3 */
> }
>
> Obviously, I'd like to do something more sophisticated than build 56-bit
> adders :).
>
> --Steve
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 16877Don't go there, you're inviting nothing but grief and gray hairs. It is exceedingly poor practice to use gates to generate delays like that. In FPGAs, you would need to do the place and route by hand to make sure the routing didn't change on you, and even then there is no guarantee the delay would be close to what you want. Use a faster clock, ans if you need to use both edges. Leslie Yip (/ Loui) wrote: > Hello everybody > > I would like to know whether VHDL can specify the delay time in FPGA / > ASIC. I know modelling can write: > DCHA <= CHA after 12 ns; -- CHA is input, DCHA is delayed output > > I implement, in the past, in ASIC by using not gates in series with > schematic capture. --not --not -- not --not > > But VHDL synthesizer like FPGA Express will optimize the logic not(s), > so would anyone know how to solve the problem? > > Leslie Yip (Loui) > -- > Hong Kong > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16878
It all depends on what you need for filter characteristics. Generally, when one talks of digital filters they are referring to filters used in digital signal processing. The filter you show would not work very well in those applications. As for the FIR and IIR filters, look at the literature on the Xilinx website for information on efficient implementations for FPGAs. Leslie Yip (/ Loui) wrote: > Well. The examples are quite comprehensive but what one needs may not be > the DSP-type FIR/IIR digital filter. The cost of such filters are very > high. (You have to implement A/D, multipliers, shifters and adders) > > I would like to propose another one of much much low-cost. Try majority > filter. The advantage of it is easy, low-cost, simple but it has delay. > It depends on your application. Below shows a filter with 3 clock-cycle > delays. (the last clock cycle is to synchronize with the sys clock to > avoid glitches) > > -- Leslie Yip (Loui) > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.all; > > Entity D_FILTER is > port( CLK,NRST: in std_logic; > S_IN: in std_logic_vector(1 > downto 0); > DFIR: in std_logic; > S_OUT: out std_logic_vector(1 downto 0) > ); > end D_FILTER; > > architecture D_FILTER_ARCH of D_FILTER is > signal countA: std_logic_vector(1 downto 0); > signal countB: std_logic_vector(1 downto 0); > signal DS_OUT: std_logic_vector(1 downto 0); > > begin > > process(CLK, NRST) > begin > if NRST='0' then > countA <= (others=>'0'); > > elsif CLK='1' and CLK'event then > if S_IN(0) ='1' and countA /= 2 then > countA <= countA + 1; > elsif S_IN(0) ='0' and countA /= 0 then > countA <= countA - 1; > end if; > end if; > end process; > > process(CLK) > begin > --if DFIR = '1' then > -- S_OUT <= S_IN; > --else > if CLK='1' and CLK'event then > if countA=2 then > DS_OUT(0) <= '1'; > elsif countA = 0 then > DS_OUT(0) <= '0'; > end if; > end if; > --end if; > end process; > > process(DFIR, S_IN, DS_OUT) > begin > if DFIR = '1' then > S_OUT(0) <= S_IN(0); > else > S_OUT(0) <= DS_OUT(0); > end if; > end process; > > process(CLK, NRST) > begin > if NRST='0' then > countB <= (others=>'0'); > > elsif CLK='1' and CLK'event then > if S_IN(1) ='1' and countB /= 2 then > countB <= countB + 1; > elsif S_IN(1) ='0' and countB /= 0 then > countB <= countB - 1; > end if; > end if; > end process; > > process(CLK) > begin > --if DFIR = '1' then > -- S_OUT <= S_IN; > --else > if CLK='1' and CLK'event then > if countB=2 then > DS_OUT(1) <= '1'; > elsif countB = 0 then > DS_OUT(1) <= '0'; > end if; > end if; > --end if; > end process; > > process(DFIR, S_IN, DS_OUT) > begin > if DFIR = '1' then > S_OUT(1) <= S_IN(1); > else > S_OUT(1) <= DS_OUT(1); > end if; > end process; > > end D_FILTER_ARCH; > > In article <7jvsnt$l1t$1@info-server.surrey.ac.uk>, > nospam_ees1ht@ee.surrey.ac.uk (Hans) wrote: > > > > > > > >I need to implement digital filters (in general) on FPGAs, I want to > do > > >it with VHDL descriptions. > > >Has anyone done this yet? > > >Is there any site where I can get any examples? > > >So, I need some bibliographics references about digital filters > > >implementation. > > >Thanks, and sorry by my poor english. > > > > Have a look at http://www.iowegian.com/loadfir.htm > > > > Hans. > > > > > > -- > Hong Kong > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16879
I need to test a design that will interface directly to the PC ISA bus via an FPGA. I am looking for an off the shelf board that connects all of the ISA bus signals to the FPGA, or at least the subset needed for a standard IO card. Does anyone know of such a board? There were a number of posts on this recently, but most of them have expired from my server. I believe there were a few posts listing lists of FPGA boards. Can anyone repost them? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 16880
This is a multi-part message in MIME format. --------------F06132218428DA93A8B4BA11 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit A problem occurs under Aldec Active VHDL 3.3 if I try to use recursive structures e.g. recursive architectures of an entity. The code in the appendix is from the book "The Designer's Guide to VHDL" but the error occurs on all files using recursive architectures. The code describes a fanout_tree. The generic parameter height is mapped in each recursionsstep to a smaller value and the recursion terminates when height=0. I also wrote a testbench tree_test instantiating the fanout_tree and mapping height to an initial value of 3. The compilation is succesfull but if I try setting tree_test as top-level I get the following error: ELBREAD: Error: Circular reference in 'Versuch1.fanout_tree(recursive)': instance 'subtree_0'. ELBREAD: Error: Elaboration process completed with errors. Design: Error: Elaboration failed Is this an error of AVHDL3.3 or have I make a mistake? Sandro Wefel --------------F06132218428DA93A8B4BA11 Content-Type: text/plain; charset=us-ascii; name="text1" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="text1" library ieee; use ieee.std_logic_1164.all; entity buf is port ( a: in STD_LOGIC; y: out STD_LOGIC ); end entity buf; architecture basic of buf is begin -- a simple buffer !!! y <= a; end basic; library ieee; use ieee.std_logic_1164.all; entity fanout_tree is generic ( height: natural); port ( input: in std_logic; output: out std_logic_vector ( 0 to 2**height-1) ); end entity fanout_tree; architecture recursive of fanout_tree is begin degenerate_tree: if height = 0 generate begin output(0) <= input; end generate degenerate_tree; compound_tree: if height > 0 generate signal buffered_input_0, buffered_input_1 : std_logic; begin buf0: entity work.buf(basic) port map ( a=> input, y=> buffered_input_0); subtree_0 : entity work.fanout_tree(recursive) generic map ( height => height-1 ) port map ( input => buffered_input_0, output => output(0 to 2**(height-1)-1)); buf1: entity work.buf(basic) port map ( a=> input, y=> buffered_input_1); subtree_1 : entity work.fanout_tree(recursive) generic map ( height => height-1 ) port map ( input => buffered_input_1, output => output(2**(height-1) to 2**height-1)); end generate compound_tree; end architecture recursive; --------------F06132218428DA93A8B4BA11--Article: 16881
Altera has a FIR filter generator in their free DSP kit for FPGA Hi Peter Jos=E9 Antonio Moreno Zamora wrote: > I need to implement digital filters (in general) on FPGAs, I want to do= > it with VHDL descriptions. > Has anyone done this yet? > Is there any site where I can get any examples? > So, I need some bibliographics references about digital filters > implementation. > Thanks, and sorry by my poor english.Article: 16882
Please can anyone advise how to get rid of the following error message using MaxPlus II 9.21. "Time stamp of file toplevel.edf is greater than the time stamp of the current CNF file(s) -- check your operating system time". The edif file is generated by synplicity 5.2.1. The Windows time stamps show that the CNF files are later than the edif. The edif file itself also has a time stamp field - perhaps this not according to Altera format. Heaven help us with Quartus is released when the 5 year old software is still so buggy!!Article: 16883
In article <37661C1C.16038936@informatik.tu-muenchen.de>, Martin Maurer <maurerm@informatik.tu-muenchen.de> wrote: > Hello, > > i have three question come up when using Xilinx Foundation: > > 1) I got the following message by ngd2edif: undriven net "PRLD". > What does it mean, how can i prevent it ? > > 2) I got another message by ref_2_inst: dangling ports. > Is this a warning or error. Must/Can i do something to prevent it ? > > 3) I use the following in one of my designs with a XC95108: > Problem is that counter TAKT_TEILER is running with frequency > ABTAST_TAKT, > but MODE_MONITOR is really 0 und stays 0 the whole time (i have > checked it on DEBUG_OUT1, > pin 24). I have another line using MODE_MONITOR, where MODE_MONITOR > seems > also to be wrong. What i am doing wrong ? > > Here are part of my source file: > > TT0 NODE istype 'reg'; > TT1 NODE istype 'reg'; > TT2 NODE istype 'reg'; > TT3 NODE istype 'reg'; > > TAKT_TEILER = [TT3..TT0]; > > DEBUG_OUT1 pin 24 istype 'com'; > DEBUG_OUT5 pin 33 istype 'com'; > DEBUG_OUT6 pin 34 istype 'com'; > DEBUG_OUT7 pin 35 istype 'com'; > DEBUG_OUT8 pin 36 istype 'com'; > > DEBUG_OUT1 = MODE_MONITOR; > > TAKT_TEILER.CLK = ABTAST_TAKT & MODE_MONITOR & (ENABLE_COUNTER # > !ENABLE_TRIGGER); > TAKT_TEILER := TAKT_TEILER + 1; > TAKT_TEILER.AR = WANT_RES; > > DEBUG_OUT5 = TT0; > DEBUG_OUT6 = TT1; > DEBUG_OUT7 = TT2; > DEBUG_OUT8 = TT3; > > Greetings and many thanks for helping, > > Martin Maurer (maurerm@in.tum.de) > > 1) You can not prevent it. PRLD is a signal you have to drive during SIMULATION only to initilize all FFs. It does not have to do with the hardware. 2) ??? 3) Take a look at the report-file of the fitter. There you can see the eqations really implemented. However, your design violates one of the unwritten laws of digital design : NEVER USE GATED CLOCKS!! I would change the design to have the count enable in the data path instead of the clock path. -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16884
Hello all. As the subject line suggests, I am looking for an independent source of timing benchmarks for FPGAs implementing DSP functions such as FIR filters and FFTs. I am attempting to compare FPGAs and digital signal processors and have found the data from various FPGA manufacturers to be lacking information such as simple tables outlining the device used, input parameters, and timing results. Thanks in advance, Michael GilliesArticle: 16885
Martin Maurer wrote: > Hello, > > i have three question come up when using Xilinx Foundation: > > 1) I got the following message by ngd2edif: undriven net "PRLD". > What does it mean, how can i prevent it ? > That means that one output (or internal signal?) is not driven. This signal is defined but nothing asserts it to a value. > > 2) I got another message by ref_2_inst: dangling ports. > Is this a warning or error. Must/Can i do something to prevent it ? > One internal signal (or input?) is defined but drives nothing (is not used). Is a placer and rooter warning a source program error? > > 3) I use the following in one of my designs with a XC95108: > Problem is that counter TAKT_TEILER is running with frequency > ABTAST_TAKT, > but MODE_MONITOR is really 0 und stays 0 the whole time (i have > checked it on DEBUG_OUT1, > pin 24). I have another line using MODE_MONITOR, where MODE_MONITOR > seems > also to be wrong. What i am doing wrong ? > > Here are part of my source file: > > TT0 NODE istype 'reg'; > TT1 NODE istype 'reg'; > TT2 NODE istype 'reg'; > TT3 NODE istype 'reg'; > > TAKT_TEILER = [TT3..TT0]; > > DEBUG_OUT1 pin 24 istype 'com'; > DEBUG_OUT5 pin 33 istype 'com'; > DEBUG_OUT6 pin 34 istype 'com'; > DEBUG_OUT7 pin 35 istype 'com'; > DEBUG_OUT8 pin 36 istype 'com'; > > DEBUG_OUT1 = MODE_MONITOR; > > TAKT_TEILER.CLK = ABTAST_TAKT & MODE_MONITOR & (ENABLE_COUNTER # > !ENABLE_TRIGGER); > TAKT_TEILER := TAKT_TEILER + 1; > TAKT_TEILER.AR = WANT_RES; > > DEBUG_OUT5 = TT0; > DEBUG_OUT6 = TT1; > DEBUG_OUT7 = TT2; > DEBUG_OUT8 = TT3; > > Greetings and many thanks for helping, > > Martin Maurer (maurerm@in.tum.de) Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16886
Utku Ozcan wrote: > I don't use the SPO's of some DP RAM's on XC40150XV. > NGDBUILD and XNF2NGD give warnings. Do these warnings > imply a possibly bad routing architecture? Shall I > use the commands which ignore these pins? I have > used following command but the warnings didn't go away: > > NET "dp_ram_spo<*>" TIG=TS01; > > Shall this TS01 be defined for write clock of the Dual > Port RAM? Shall I use such a command to improve the > performance? > > Utku Which warning do you have? Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16887
Rickman wrote: > I need to test a design that will interface directly to the PC ISA bus > via an FPGA. I am looking for an off the shelf board that connects all > of the ISA bus signals to the FPGA, or at least the subset needed for a > standard IO card. Does anyone know of such a board? > > There were a number of posts on this recently, but most of them have > expired from my server. > > I believe there were a few posts listing lists of FPGA boards. Can > anyone repost them? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com You can do a find at ; http://www.deja.com/ Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16888
Hi Can use FPGa with Analog circuit design (ADC , DAC )? Or can i use circuit about RF with FPGA? Please suggest me!!! Xilinx can do that? REgard. Wannarat Suntiamorntut E-mail : ksuwanna@kmitl.ac.thArticle: 16889
Rickman <spamgoeshere4@yahoo.com> wrote in message news:376738DD.D561E1AC@yahoo.com... > I need to test a design that will interface directly to the PC ISA bus > via an FPGA. I am looking for an off the shelf board that connects all > of the ISA bus signals to the FPGA, or at least the subset needed for a > standard IO card. Does anyone know of such a board? > > There were a number of posts on this recently, but most of them have > expired from my server. > > I believe there were a few posts listing lists of FPGA boards. Can > anyone repost them? Visit http://www.associatedpro.com/ for the best selection and support. Alternately, the logic jump stations is comprehensive at http://www.optimagic.comArticle: 16890
go to see at www.associatedpro.com Have FPGA board with ISA bus interface. U can debugg this board via program on computer:) try to see that. Wannarat ksuwanna@kmitl.ac.th Le mer Michel wrote: > Rickman wrote: > > > I need to test a design that will interface directly to the PC ISA bus > > via an FPGA. I am looking for an off the shelf board that connects all > > of the ISA bus signals to the FPGA, or at least the subset needed for a > > standard IO card. Does anyone know of such a board? > > > > There were a number of posts on this recently, but most of them have > > expired from my server. > > > > I believe there were a few posts listing lists of FPGA boards. Can > > anyone repost them? > > > > -- > > > > Rick Collins > > > > rick.collins@XYarius.com > > > > remove the XY to email me. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design > > > > Arius > > 4 King Ave > > Frederick, MD 21701-3110 > > 301-682-7772 Voice > > 301-682-7666 FAX > > > > Internet URL http://www.arius.com > > You can do a find at ; > http://www.deja.com/ > > Hope this helps, > > Michel Le Mer > Gerpi sa (Xilinx Xpert) > 3, rue du Bosphore > Alma city > 35000 Rennes (France) > (02 99 51 17 18) > http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16891
I looked too and found nothing. There no standard serial EPROMs that big. I suppose you know of the EPC2 which can not fit into the 8 dip package. Hi Peter Garrick Kremesec wrote: > Hello, > > This was brought up recently, but are there any erasable replacements > for the 8 pin dip Altera EPC1? I'm really looking for something that is > pin/function equivalent yet either electronically erasable or UV > erasable. > > Thank you for the help. > > Garrick Kremesec > University of Illinois > gkremese@ews.uiuc.eduArticle: 16892
Altera also has a limited free tool, but you don't get far with that.
As far as I know the commercial Unix tool are all expensive.
Much tools are available for windows NT, but still cost. Windows 95/98 are no
good for serious work
and many tools are discontuined for 95/98.
I would change to Linux any day if I could my FPGA/PCB tools for Linux. But I
can't.
Hi Peter
"vrml3d.com" wrote:
> What's the best way to start working with FPGAs? Can it be done for approx
> $500 US, or is it impossible to do anything cool without spending alot of
> money? Does all of the software run on commercial Unix? Does any of it run
> on Win98? If not, Linux would be a bearable alternative. How difficult is
> it to program FPGAs? Are there any C/C++ libraries that will allow you to
> say, for example... do something like this:
>
> #define REGISTER_WIDTH 56
>
> MyDevice::MyDevice(int iBits)
> {
> m_pRegister1=CreateRegister(iBits);
> m_pRegister2=CreateRegister(iBits);
> m_pRegister3=CreateRegister(iBits);
> m_pOverflow=CreateRegister(1);
> m_pUnit1=CreateAdder(iBits);
> m_pUnit1-?SetInputA(m_pRegister1);
> m_pUnit1-?SetInputB(m_pRegister2);
> m_pUnit1-?SetOuput(m_pRegister3);
> m_pUnit1-?SetOverflowBit(m_pOverflow);
> }
>
> void main()
> {
> char blah1[7];
> char blah2[7];
> char blah3[7];
>
> /* initialize blah1 and blah2 with 56 bit integers. */
>
> MyDevice HelloHardware(REGISTER_WIDTH);
> HelloHardware.m_pRegister1-?SetRegister(blah1);
> HelloHardware.m_pRegister2-?SetRegister(blah2);
>
> HelloHardware.m_pRegister3-?GetRegister(blah3);
>
> /* now do something with the 56-bit integer result in blah3 */
> }
>
> Obviously, I'd like to do something more sophisticated than build 56-bit
> adders :).
>
> --Steve
Article: 16893I'm not sure why this is a problem for you. It simply means your edif file is newer than the altera cnf file. So you must recompile tyour edif file in Altera to get the cnf file updated. Make sure that Maxplus2 has the edif file as source and not the VHDL file as you use synplify VHDL synthesize. Hi Peter Anthony Ellis - LogicWorks wrote: > Please can anyone advise how to get rid of the following error message using > MaxPlus II 9.21. > > "Time stamp of file toplevel.edf is greater than the time stamp of the > current CNF file(s) -- check your operating system time". > > The edif file is generated by synplicity 5.2.1. The Windows time stamps show > that the CNF files are later than the edif. > The edif file itself also has a time stamp field - perhaps this not > according to Altera format. > > Heaven help us with Quartus is released when the 5 year old software is > still so buggy!!Article: 16894
Hi newsgroup, I have a simple (?) problem using VHDL and Viewlogic. After declaration of an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works fine, but I want to have an active low signal (signalname with overline) in my schematic. I have no idea how to realize it in VHDL . Any suggestions?Article: 16895
Sorry, forgot my real name; damned Outlock ;-) !!! Hi newsgroup, I have a simple (?) problem using VHDL and Viewlogic. After declaration of an entity I use VHDL2SYM.EXE to create a symbol for ViewDraw. It works fine, but I want to have an active low signal (signalname with overline) in my schematic. I have no idea how to realize it in VHDL . Any suggestions? -- Ingo Purnhagen OHB-System GmbH Universitaetsallee 27-29 D-28359 Bremen Telefon: 0421-2020-702 Telefax: 0421-2020-610 mailto:Purnhagen@ohb-system.de http://www.ohb-system.deArticle: 16896
Alain Thanks for you comments. It's good to know that some companies out there are actually using Boundary Scan. Sorry but I don't have any practical knowledge to share yet. If I come up with anything useful, I'll post it to this newsgroup. Best Regards Adrian Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16897
Ray Andraka wrote: > Don't go there, you're inviting nothing but grief and gray hairs. It is > exceedingly poor practice to use gates to generate delays like that. In > FPGAs, you would need to do the place and route by hand to make sure the > routing didn't change on you, and even then there is no guarantee the > delay would be close to what you want. Use a faster clock, ans if you > need to use both edges. > [ray a.] - - - - - - - - - - - > Leslie Yip (/ Loui) wrote: > > > Hello everybody > > > > I would like to know whether VHDL can specify the delay time in FPGA / > > ASIC. I know modelling can write: > > DCHA <= CHA after 12 ns; -- CHA is input, DCHA is delayed output > > > > I implement, in the past, in ASIC by using not gates in series with > > schematic capture. --not --not -- not --not > > > > But VHDL synthesizer like FPGA Express will optimize the logic not(s), > > so would anyone know how to solve the problem? > > > > Leslie Yip (Loui) hi, yup, grief and gray hairs ... avoid the delays if you can. i had to do it once as i had to produce hardware to interface with a spec that was soooooooo sloppy i had no choice. and brutal power requirements prohobited the use of a clock delay. so i actually have thought about this some (and recently have gained a few of the gray ones, coincidence?). anyways, 1. at least with the actelian devices, you can put a property on any net called "PRESERVE" in viewlogic schematic capture which will tell the back end software not to eliminate the gate driving that net, preserving it. i haven't tried this with vhdl but this is the type of function that made more sense to do in schematic and i knew exactly what i was getting. if i did do it in vhdl, i'd go back and generate a schematic from the edif file anyways to verify it did what i wanted it to do. 2. if you run your signals through i/o, it shouldn't be able to optimize them away. make a bidirectional buffer, drive the signal off chip, then take the input buffer (which listens to the pin) and bring that back onto the array and route it over to the next i/o pin. perhaps less resolution than above and eats more i/o pins but you have access to all the taps on your board. did this one in schematic, wouldn't wanna do it in vhdl either. normally i don't use bidirectional signals in vhdl and doing the structural vhdl for something odd like would be less clear than a schematic (imo - no flame wars on this one!). 3. you might be able to do the same as 2) above in vhdl with the inputs and outputs of a module. however, you'll have to add a "donttouch" property or something like that to the compiled module and pray that the rest of the software listens (not always!). 4. bring out a range of taps spread out far enough that you know you'll have a solution irregardless of best-best case, typ, or worst-worst case. in general, done it, no choice, but avoid it. rkArticle: 16898
hi,
hmmm ... i would say that if one was on a budget there would be no need to switch
to NT, win '95 would work just fine and there is plenty of software available for
that. some packages are not available for '95, like synopsys design compiler,
which requires either a certain flavor of unix or NT (they ported to NT last
year). of course, at about $100,000 per seat it's not for the budget watcher.
one can also discuss the so-called "quality of results" of the expensive synopsys
vs. synplicity, exemplar, or even some free synthesizer and have an "interesting"
discussion.
i would say that there are plenty of win '95 packages around and don't see why it
is "no good for serious work." yes, when overloaded, it will be need to be
rebooted, but that's a tradeoff. currently, i have both NT and '95 machines and
won't change all the '95 setups to NT simply because the amount of doing so in
time (and forgetting the nt license fee) simply isn't worth the hassle. with the
computer prices of today, it's cheaper to just buy another box with nt on it and
set that aside for the "serious work." as for absolute levels of performance as
well as performance per $, the NT boxes do surprisingly well. asic and eda today
[i think that's their current name] did some object performance tests with unix
vs. wintel on large asic designs and found there was no problem with performance
on NT, in fact it outperformed unix on many tests. this goes against the dogma
that "nt clogs the system and slows it down."
anyways, what tools are discontinued for 95/98? i watch that fairly closely but
haven't heard about this.
thanks,
rk
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Peter Sørensen wrote:
> Altera also has a limited free tool, but you don't get far with that.
> As far as I know the commercial Unix tool are all expensive.
> Much tools are available for windows NT, but still cost. Windows 95/98 are no
> good for serious work
> and many tools are discontuined for 95/98.
> I would change to Linux any day if I could my FPGA/PCB tools for Linux. But I
> can't.
> Hi Peter
>
> "vrml3d.com" wrote:
>
> > What's the best way to start working with FPGAs? Can it be done for approx
> > $500 US, or is it impossible to do anything cool without spending alot of
> > money? Does all of the software run on commercial Unix? Does any of it run
> > on Win98? If not, Linux would be a bearable alternative. How difficult is
> > it to program FPGAs? Are there any C/C++ libraries that will allow you to
> > say, for example... do something like this:
> >
> > #define REGISTER_WIDTH 56
> >
> > MyDevice::MyDevice(int iBits)
> > {
> > m_pRegister1=CreateRegister(iBits);
> > m_pRegister2=CreateRegister(iBits);
> > m_pRegister3=CreateRegister(iBits);
> > m_pOverflow=CreateRegister(1);
> > m_pUnit1=CreateAdder(iBits);
> > m_pUnit1-?SetInputA(m_pRegister1);
> > m_pUnit1-?SetInputB(m_pRegister2);
> > m_pUnit1-?SetOuput(m_pRegister3);
> > m_pUnit1-?SetOverflowBit(m_pOverflow);
> > }
> >
> > void main()
> > {
> > char blah1[7];
> > char blah2[7];
> > char blah3[7];
> >
> > /* initialize blah1 and blah2 with 56 bit integers. */
> >
> > MyDevice HelloHardware(REGISTER_WIDTH);
> > HelloHardware.m_pRegister1-?SetRegister(blah1);
> > HelloHardware.m_pRegister2-?SetRegister(blah2);
> >
> > HelloHardware.m_pRegister3-?GetRegister(blah3);
> >
> > /* now do something with the 56-bit integer result in blah3 */
> > }
> >
> > Obviously, I'd like to do something more sophisticated than build 56-bit
> > adders :).
> >
> > --Steve
Article: 16899The edif file is the top level or project file and has a later time stamp than the cnf files. There is no "toplevel.vhd" file. One can delete all the .cnf files in the directory and re-run MaxPlus. It re-creates all the cnf files and then gives the error message. What may be significant is that the top level vhd file is called "toplevel_struct.vhd" (it is generated by Renoir) but the output file by Synplicity is set to "toplevel.vhd". It is done like this because Altera doesn't support file names different to the entity name. Peter Sørensen wrote in message <37676CF3.F4730B02@emi.dtu.dk>... >I'm not sure why this is a problem for you. >It simply means your edif file is newer than the altera cnf file. So you must >recompile tyour edif file in Altera to get the cnf file updated. Make sure that >Maxplus2 has the edif file as source and not the VHDL file as you use synplify >VHDL synthesize. >Hi Peter > >Anthony Ellis - LogicWorks wrote: > >> Please can anyone advise how to get rid of the following error message using >> MaxPlus II 9.21. >> >> "Time stamp of file toplevel.edf is greater than the time stamp of the >> current CNF file(s) -- check your operating system time". >> >> The edif file is generated by synplicity 5.2.1. The Windows time stamps show >> that the CNF files are later than the edif. >> The edif file itself also has a time stamp field - perhaps this not >> according to Altera format. >> >> Heaven help us with Quartus is released when the 5 year old software is >> still so buggy!! >
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