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Messages from 18950

Article: 18950
Subject: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
From: a_maier@my-deja.com
Date: Mon, 22 Nov 1999 21:26:40 GMT
Links: << >>  << T >>  << A >>
In article <Pine.GSO.3.96.991119064735.15834A-100000@moray.cs.columbia.edu>, Paul Oh <paul@moray.cs.columbia.edu> wrote:
> 
> Hi to all!
> 
> My end-goal
is to port my ISA card design to PCI.  This ISA card is a
> simple 8255-based
I/O board.  It's details if you are interested are at
>
http://www.boondog.com - see the Tutorials link.
> 
> I have no PCI
experience.  My impression is that one needs a FPGA or other
> programmable
logic device (PLD) for PCI interfacing.  
> 
> I have no PLD experience but
do know digital logic and digital system
> design (I am mechanical engineer).
 
> 
> Xilinx and Altera sell affordable ($100 range) development kits and
>
software (student versions).
> 
> Q.  For my stated end-goal which PLD should
I begin my learning curve on?
> Q.  Are on-line PCI tutorials (in relation to
my end-goal or porting
>  ISA designs to PCI) ?
> 
> Much appreciated,
> 
>
Paul Oh
> 
Hello Paul

a few years ago i ported a ISA hardware to pci using a
altera7128 CPLD. This 
was a hard work (even if it was only a PCI-slave)
because i had also no 
experience in PCI. Since this time i designed three
PCI Cards using AMD-CPLD
 and fast Logic (my second PCI design), AMCC (third)
an this time i am designing
 with PLX. I would suggest you to use a PCI
Bridge (like Assaf Sarfati suggested
you) from PLX . There is also a special
PCI Bridge from Siemens for porting ISA 
to  PCI but i have no experience
with it


regards Andreas
.


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Before you buy.
Article: 18951
Subject: Re: Virtex: Getting flip-flops into the pads
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 22 Nov 1999 22:34:24 +0100
Links: << >>  << T >>  << A >>
"Jamie Sanderson" <jamie@nortelnetworks.com> writes:
[...]
> I would much rather the synthesis tool be
> responsible for the placement of the flip-flops, rather than Xilinx's
> mapper.

Watch out what you wish for! With the new Altera Apex family and their
P&R tool Quartus, that's exactly what you got. Now the problem is
reversed: How to get Synplify to put the FFs in the I/O pads! In my
case, I wanted a registered output enable. That register is available
in the I/O pad of Altera. However, Synplify still wants to use a
regular FF instead. The high fan-out and the long distance to the I/O
pads makes the timing too slow.

Oh well...

Homann
--
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 18952
Subject: Re: How to use multiple resets?
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Mon, 22 Nov 1999 16:22:02 -0600
Links: << >>  << T >>  << A >>
My suggestion (if feasible) would be to route the combined reset out a pin,
and then back into the pin that uses the global reset network.  I know this
is kind of a cludge, but not too messy if it gets the job done.

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com
Brian Boorman <XYZ.bboorman@harris.com> wrote in message
news:38341CF7.9B3C200C@harris.com...
> Utku Ozcan wrote:
> >
> <snip>
> >
> > 1. In the Xilinx manual "Synthesis and Simulation Design Guide", page
> > 4-9, in the first paragraph:
> >
> > "XC4000 and Spartan devices have a dedicated Global Set/Reset
> > (GSR) net that you can use to initialize all CLBs and IOBs. When the
> > GSR is asserted, EVERY flip flop in the FPGA is simultaneously preset
> > or cleared. You can access the GSR net from the GSR pin on the
> > STARTUP block or the GSRIN pin of the STARTBUF (VHDL)."
> >
> > 2. In the Synplify User Guide book, at the section "Xilinx FPGA
Support",
> > at the item "Startup Block for XC4000 and XC5200", 3rd paragraph:
> >
> > "If multiple resets are used in the design, then Synplify will not
> > automatically create a startup block in GSR. If you still want one
> > of the reset signals to be used for GSR then you will need to
> > manually instantiate a STARTUP_GSR module in your design source file."
> >
> > Which is correct?
>
> Both are correct. You can have two resets, one of which uses the GSR,
> the other using normal routing. The downside is that the GSR reset will
> reset ALL flipflops. If you want two INDEPENDENT reset signals (which
> from reading your post I assume is the case) then you MUST use regular
> routing resources for BOTH reset signals.
>
> --
> Brian C. Boorman
> Harris RF Communications
> Rochester, NY 14610
> XYZ.bboorman@harris.com
> <Remove the XYZ. for valid address>


Article: 18953
Subject: Xilinx changed the pinout of the download cable?
From: Austin Franklin <austin@darkroom.com>
Date: Mon, 22 Nov 1999 22:34:47 GMT
Links: << >>  << T >>  << A >>
It appears, that Xilinx saw fit to change the pinout of the new
download cable.  I can't imagine why they would change this, since the
new cable is a subset of the pins that are on the previous version of
the download cable.

They even removed a bunch of pins.../INIT, RST, and the readback pins
RT, RD and TRIG...

We design out boards so the download header just plugs into the board,
and now, the new one doesn't.  SO..now I guess we should do all new
boards with the new 'standard' (until they change it again...) and
maintain our old boards with the 'old' standard...hum.

Does anyone have any idea what compelled them to make this seemingly
unnecessary change?  The only reason I can come up with is to sell new
download cables.

I guess the tools are getting better...but between this silly changing
of the download header pins, and the new, almost useless FPGA Editor, I
can't wait for the next 'improvement' ;-/


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Before you buy.
Article: 18954
Subject: Virtex FIFO w/ Block RAM
From: Michael G Wrighton <mgw1@arl.wustl.edu>
Date: Mon, 22 Nov 1999 17:18:59 -0600
Links: << >>  << T >>  << A >>
Hi,
We're in need of a FIFO implemented with the Virtex's Block RAM. I've
found the Xilinx appnote titled "170 MHz FIFOs Using the Virtex Block
SelectRAM+" available from the cores page. This is precisely what we
need except for that it is written in Verilog and our environment is
VHDL. I'd be willing to try this co-simulation trick to integrate the
two languages, but I wonder if anyone knows of a VHDL version of this
freely available. Also, I've heard the mixing VHDL and Verilog can
result in some pretty hairy problems. Any comments on that front?

Thanks,
MGW

Article: 18955
Subject: VHDL vs. schematic entry
From: Greg Neff <gregneff@my-deja.com>
Date: Mon, 22 Nov 1999 23:24:20 GMT
Links: << >>  << T >>  << A >>
In article <38398D1C.A7B9E445@ids.net>,
  Ray Andraka <randraka@ids.net> wrote:
> Don Husby wrote:
>
(snip)
> >
> > I agree that schematics are still the best way to enter a design.
I just
> > thought I would beat my head against the VHDL wall one more time
before
> > going back to schematics.
>
> I've been using, no beating my head against the wall, with VHDL
lately too.
> I'm doing it for two reasons: First I have some customers who bought
the VHDL
> thing hook, line, and sinker (try to convince them they're wrong!),
and for my
> own stuff because it allows me to parameterize functions pretty
easily.  I'm
> beginning to wonder if I'll ever see the return on the design
investment for
> those parameterized thingies though.
>
(snip)

I having been using schematic entry for FPGAs, probably because I have
been drawing schematics since before the days of PALs, let alone
FPGAs.  I am now considering taking the leap to VHDL entry, but I am
not convinced that there will be a benefit in either time to design or
design quality.  The above comments seem to be indicative of those like
myself, who are highly skilled at schematic entry for FPGAs.

I'm not talking about a situation where a team of engineers is
designing a mega-gate FPGA.  I am more interested in small to mid-range
(say, up to 100K gate) designs that are being entered and maintained by
one person.

I would be interested to hear from those people that have gone through
the VHDL learning curve.

Has the move to VHDL reduced design entry time?
Has the design quality improved (fewer problems)?
Is design debugging easier?
Is design maintenance easier?
Is design reuse easier?
Did you get to the point where VHDL is more efficient than schematics?
If so, how long did it take to get to this point?
Bottom line: Was it worth it?

I would like to hear from Don and Ray, to see if they consider
themselves to be still on the learning curve, or if they truly think
that VHDL is not worth the hassle.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 18956
Subject: VHDL vs. schematic entry
From: Greg Neff <gregneff@my-deja.com>
Date: Mon, 22 Nov 1999 23:59:25 GMT
Links: << >>  << T >>  << A >>
I having been using schematic entry for FPGAs, probably because I have
been drawing schematics since before the days of PALs, let alone
FPGAs.  I am now considering taking the leap to VHDL entry, but I am
not convinced that there will be a benefit in either time to design or
design quality.

I'm not talking about a situation where a team of engineers is
designing a mega-gate FPGA.  I am more interested in small to mid-range
(say, up to 100K gate) designs that are being entered and maintained by
one person.

I would be interested to hear from those people that have gone through
the VHDL learning curve.

Has the move to VHDL reduced design entry time?
Has the design quality improved (fewer problems)?
Is design debugging easier?
Is design maintenance easier?
Is design reuse easier?
Did you get to the point where VHDL is more efficient than schematics?
If so, how long did it take to get to this point?
Bottom line: Was it worth it?

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 18957
Subject: Re: VHDL vs. schematic entry
From: Mike Treseler <tres@tc.fluke.com>
Date: Mon, 22 Nov 1999 17:04:48 -0800
Links: << >>  << T >>  << A >>
Greg Neff wrote:
> 
> I would be interested to hear from those people that have gone through
> the VHDL learning curve.
> 
> Has the move to VHDL reduced design entry time?

Slightly. Gets a little better each time.

> Has the design quality improved (fewer problems)?

Yes. Simulation compile and .edf viewer finds most problems. 
Sim testbench finds most of the rest.
Adds to your confidence.

> Is design debugging easier?

Yes. And if you do a testbench, very little is needed.

> Is design maintenance easier?

Yes. By far. All text. Use CVS or RCS to control revs.
With a closed loop testbench, you can quickly verify that
incremental changes don't screw anything up.

> Is design reuse easier?

I have reused packages and procedures from project to project.

> Did you get to the point where VHDL is more efficient than schematics?

Yes.

> If so, how long did it take to get to this point?

about 6 months.
Best to get started between projects 
-- not when the pressure is on.

> Bottom line: Was it worth it?

For me it was because I enjoyed the process.
        

             -Mike Treseler
Article: 18958
Subject: Re: VHDL vs. schematic entry
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 23 Nov 1999 01:19:58 GMT
Links: << >>  << T >>  << A >>
On Mon, 22 Nov 1999 23:59:25 GMT, Greg Neff <gregneff@my-deja.com>
wrote:

>I having been using schematic entry for FPGAs, probably because I have
>been drawing schematics since before the days of PALs, let alone
>FPGAs.  I am now considering taking the leap to VHDL entry, but I am
>not convinced that there will be a benefit in either time to design or
>design quality.
>
>I'm not talking about a situation where a team of engineers is
>designing a mega-gate FPGA.  I am more interested in small to mid-range
>(say, up to 100K gate) designs that are being entered and maintained by
>one person.
>
>I would be interested to hear from those people that have gone through
>the VHDL learning curve.
>
>Has the move to VHDL reduced design entry time?
>Has the design quality improved (fewer problems)?
>Is design debugging easier?
>Is design maintenance easier?
>Is design reuse easier?
>Did you get to the point where VHDL is more efficient than schematics?
>If so, how long did it take to get to this point?
>Bottom line: Was it worth it?

IMO, you missed the main advantage of VHDL.  It's a hardware
description language.  You can make very detailed self checking
testbenches, using all sorts of constructs (some of which aren't even
sythesisable (like file I/O and floating point arithmetic)).
I typically find that I end up with about the same number of lines of
code in the test bench and the chip.

I find that there is a lot of reuse of test bench code (probably
because all the chips seem to interface to the same sort of hardware),
but not much reuse of synthesisable code (because the chips all do
different things).

Regarding the other points: if you can already design logic, another
language won't make too much of a difference.  (As a friend of mine
says: "same shit, different bucket.")  You might be better off
sticking with what you know though.

[ I'm a VHDL convert, BTW. ]

Regards,
Allan.
Article: 18959
Subject: Re: VHDL vs. schematic entry
From: Ray Andraka <randraka@ids.net>
Date: Mon, 22 Nov 1999 20:24:16 -0500
Links: << >>  << T >>  << A >>


Greg Neff wrote:

> In article <38398D1C.A7B9E445@ids.net>,
>   Ray Andraka <randraka@ids.net> wrote:
> > Don Husby wrote:
> >
> (snip)
> > >
> > > I agree that schematics are still the best way to enter a design.
> I just
> > > thought I would beat my head against the VHDL wall one more time
> before
> > > going back to schematics.
> >
> > I've been using, no beating my head against the wall, with VHDL
> lately too.
> > I'm doing it for two reasons: First I have some customers who bought
> the VHDL
> > thing hook, line, and sinker (try to convince them they're wrong!),
> and for my
> > own stuff because it allows me to parameterize functions pretty
> easily.  I'm
> > beginning to wonder if I'll ever see the return on the design
> investment for
> > those parameterized thingies though.
> >
> (snip)
>
> I having been using schematic entry for FPGAs, probably because I have
> been drawing schematics since before the days of PALs, let alone
> FPGAs.  I am now considering taking the leap to VHDL entry, but I am
> not convinced that there will be a benefit in either time to design or
> design quality.  The above comments seem to be indicative of those like
> myself, who are highly skilled at schematic entry for FPGAs.
>
> I'm not talking about a situation where a team of engineers is
> designing a mega-gate FPGA.  I am more interested in small to mid-range
> (say, up to 100K gate) designs that are being entered and maintained by
> one person.
>
> I would be interested to hear from those people that have gone through
> the VHDL learning curve.
>
> Has the move to VHDL reduced design entry time?

Yes and No.  For some of the stuff you don't care how it gets implemented,
VHDL can speed up the design time once you get used to the dialect for your
synthesizer.  For anything that benefits from floorplanning: definitely
takes several times longer in VHDL, especially if you embed the placement
in the code.  VHDL does make for easier/better simulation since you can do
elaborate test benches and can have the test bench verify results.

> Has the design quality improved (fewer problems)?

No improvement, but a lot more "pushing on a rope" to make the tools do
what you want when you want something specific.

> Is design debugging easier?

Yes and no.  The testbenches make more elaborate testing easier, but when
you are trying to track down a specific problem I find the old schematic
views of the simulation much easier for finding stupid things like stuck-at
values or where the 'X's start.

> Is design maintenance easier?

VHDL lets you read the design archive with a simple text editor, where as
schematics require the schematic reader.  Get a new version of the
schematic tool, and you might not be able to read some or all of your old
schematics (like when viewlogic went from workview plus to workview
office).  This is not to say either will compile correctly under newer
tools.  VHDL synthesis has had a poor history of new versions yielding
different synthesis results.

> Is design reuse easier?

Depends on the design.  I've been purposely spending more time on some VHDL
designs so that they are parameterized for things like bus width.  It takes
longer to do them the first time, but next time all you need to do is put
in the right generics.  In both cases, a highly hierarchical design is
needed for optimum reusability.  VHDL labels get messy with lots of
hierarchy, especially if you are using the generate statements.

> Did you get to the point where VHDL is more efficient than schematics?

Yes and no.  Depends on how much rope pushing you need to do to get what
you want, and how much you will be reusing the piece.

> If so, how long did it take to get to this point?

About 3-4 Months.

> Bottom line: Was it worth it?
>
> I would like to hear from Don and Ray, to see if they consider
> themselves to be still on the learning curve, or if they truly think
> that VHDL is not worth the hassle.
>

Well, I'm using VHDL on several projects.  One of the things that forced me
this way was the fact that Xilinx still doesn't have even functional sim
models for several of the key components in the Virtex.  For a complete
simulation of designs using those features (SRL16's, block mem for example)
you are stuck using VHDL.   I've been doing alot of placement from within
VHDL, and that is a major hassle:  the code becomes hard  to read because
it is structural down to the primitives and has lots of RLOC attributes on
everything.  It takes longer to enter than a schematic, and I find I have
to draw it out anyway.  The RTL and technology views in synplicity are
invaluable aids to seeing what gets produced.  I wish Aldec or modelsim had
a similar RTL view in its AVHDL package so I could at least see the picture
before synthesizing. (Aldec does have a RTL block diagram entry, but I find
it clumsy to use).

For me it was worth it, since I have customers who insist on VHDL, I'm
doing Virtex designs so I need to use VHDL for simulation.  I think for
data path stuff, schematics are considerably easier.  For state machines,
it depends on how picky you are about the implementation (I've got a
schematic methodolgy for one-hots that makes them look like a flowchart and
makes for very easy entry and maintenance).

> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18960
Subject: Re: VHDL vs. schematic entry
From: pladow@gocougs.wsu.edu
Date: 23 Nov 1999 01:32:59 GMT
Links: << >>  << T >>  << A >>
In comp.lang.vhdl Greg Neff <gregneff@my-deja.com> wrote:
> I'm not talking about a situation where a team of engineers is
> designing a mega-gate FPGA.  I am more interested in small to mid-range
> (say, up to 100K gate) designs that are being entered and maintained by
> one person.

This is what I do for a living, though not in FPGA land.  I work for an ASIC
design house, and of course we are doing designs larger than 100K gate.  But
we also have done small chips (the smallest was 30K gate).  And I can tell
you that VHDL design is much easier for me.

> I would be interested to hear from those people that have gone through
> the VHDL learning curve.

I started out as an intern doing schematic based entry at a large semiconductor
manufacturer.  Others within the company did HDL based design (VHDL, Verilog,
etc), but our group did schematic based.  We never even got close to 100K
gate designs.

> Has the move to VHDL reduced design entry time?

Once you know what you are doing, hell yeah!  What I think would take a lot
of time in schematic based entry I do on a regular basis in VHDL.  For example,
*) Fixed/variable length pipes
*) Adders/multipliers
*) Any size state machine w/o K-maps

Let's suppose you are working on a design.  You enter it using schematic based
entry.  Your clock frequency has been changed due to customer input, so you
are forced to add more pipelines to meet the new timing.  How easy is that to
do in schematic based design?  In VHDL, I simply add the following chunk:

  process(clk)
  begin
    if ( rising_edge(clk) ) then
      pipe_out <= pipe_in;
    end if;
  end process;

Now've I've got a pipestage.  Granted there is much more that needs to be
done, (i.e. tweak the control logic, perhaps add data valids, etc), but you'd
have to do that in schematic based entry as well.

Another issue is neatness.  Adding logic to a VHDL design can be easily done
in a quick time.  If you need to add logic to a schematic, you also need to
possibly restucture the layout to make it neat.  I guarantee you if I got a
design from someone that I needed to tweak, and it was a garbled mess, I
wouldn't even try to figure out how it worked.  I'd just redesign it.

I bet others think the same way.

One last note.  Of the entire design process, we can spend weeks writing
the spec, and have the VHDL done in a day.  It is that easy.  With that,
we are able to get the design done much quicker.  Our internal specs are
written with just the theory and high-level architecture.  We'll have
block diagrams and state-machines.  In fact, our blocks might say something
as simple (but in design complex) as "control".  And that's it.  We don't
say if we used gray coding, or that it is Mealy or Moore, but that it is
control.  Later we show a state diagram.  And going from state-diagrams to
VHDL....no more K-Maps!

> Has the design quality improved (fewer problems)?

It is just as good here as at my old design job.  There is the added step
in that you have to verify the output of the synthesizer.  That's the one
catch with VHDL design that I've learned...NEVER trust the synthesizer output.
Always rerun your verification suite after synthesis.

One beautiful thing about VHDL is how easy it is to parametrize your design.
We have a few testbench modules that take generic items.  For example, we
have a variable length pipe that takes two generics:  WIDTH and DEPTH.
Any time I need a 13 bit by 20 word deep FIFO, I just drop in this design.

And I'd love to tell you more about our current use of generics, but until
the press-release is out, I can't.  But let it be known that generics are
the real life-blood of design reuse (IMHO).

> Is design debugging easier?

I think so.  You setup your testbench and let it fly.  If you make changes,
you just recompile and start again.  Piece of cake.

Also, using VHDL (or at least a hybrid VHDL/schematic flow), you are capable
of creating complex testbench modules.  For example, we have a 80186, 6800,
I2C, and PowerPC testbenches.  We've designed a block that reads a generic
input file (similar to 186 assembly) and executes reads/writes over any of
the 4 uP interfaces as if an actual uP was there.  We also have tons of other
testbench modules that feed data to designs, like SCSI, USB, etc.

And if we are doing a custom design, we design custom testbench blocks to
verify the custom blocks.

> Is design maintenance easier?

This is a problem that exists in every design flow.  In my opinion, VHDL is
easier to maintain because you have 2 forms of documentation.  You have the
spec, and the VHDL.  The VHDL should be heavily commented, describing each
and every aspect of the design.  I've yet to see a commenting method for
schematics that adequately describes the design as well as plain text can do.

> Is design reuse easier?

We have a library of commonly used parts that have been verified several times
over in several designs.  For example, we have I/O pipestages that guarantee
timing isolation, variable-length FIFOs, etc.  Every project I've worked on
has used these modules.

> Did you get to the point where VHDL is more efficient than schematics?
> If so, how long did it take to get to this point?

For me, yeah.  But I was also proficient programmer.  It was an easy step
for myself.  The new-hires we get immediately get trained in the methodology
and proficient VHDL design.  Like them, my first VHDL was terrible, and I
didn't know synthesizable from non-synthesizable VHDL.

In fact, my first design in VHDL was a BIST for a CAM.  The first run in
synthesis had 4000 FF!!  Once I was taught "good" VHDL, it dropped to 130FF.
Still a bad design, but much better.  I could probably redo that design
now with less than 100FF easily.

So yeah, there is a learning curve, but not an impossible one.  It took myself
about 2 projects (1 year) to become quite proficient.  And the more work I do,
the easier it is.

> Bottom line: Was it worth it?

When I came to the company, it was already a VHDL based design house.  I quickly
learned the virtues of HDLs.  I remember once telling my instructor in
synchronous digital design:  "Who would ever design using an HDL?  It is
too complex."  Boy was I surprised.

> I would like to hear from Don and Ray, to see if they consider
> themselves to be still on the learning curve, or if they truly think
> that VHDL is not worth the hassle.

I'm definitely not on the curve anymore, but the ease in which we design,
verify, and spit out results, it is quite worth the hassle.

On a final note, I'm not saying that schematic entry is worthless.  In fact,
I use it often.  For low-level design, we do VHDL entry.  We then generate
symbols and link them to the VHDL.  Using schematic entry, we connect all
the designs together in the top level.  We then simulate the top-level with
all the blocks together.

Also, schematics serve as a visual que to data-flow.  I like to see data
enter on the left-hand block, progress through the pipelines, and come out of
the right-hand block.  It also makes it easy to document what parts of the
design are in different stages of completion.  But in this role, the top level
is nothing more than a glorified block-diagram.  But I will admit, hooking
up the top level in schematic form is much easier than in VHDL!  But, if I
needed to changed the top level layout later, I'd rather do it in VHDL.

Well, just my opinon.  I'd love to hear any comments, in support or in
contrary to my post.
Peter LaDow
pladow@mudplace.org

 _________________________________________________________________________
|                               | "To love for the sake of being loved is |
|ORQ: And the meek shall        |  human, to love for the sake of loving  |
|     inherit the earth...      |  is angelic." --Alphonse de Lamartine   |
 -------------------------------------------------------------------------

Article: 18961
Subject: Virtex mapper won't pack register with F5 combinatorial
From: Ray Andraka <randraka@ids.net>
Date: Mon, 22 Nov 1999 20:36:05 -0500
Links: << >>  << T >>  << A >>
I've got a design that has a six input combinatorial function
implemented in two virtex 4-LUTs and an F5-Mux.  The control for the
F5-Mux (on the BX pin) also needs to be registered, so I want to put
that register in FFX in the same slice as the six input function.  I
also want to use the other flip-flop with the direct (BY) input.  This
is a legal combination, and I do get it to work sometimes.  The problem
is the mapper doesn't seem to recognize the .FFY and .FFX extensions on
the RLOC attributes (it doesn't complain about them being there
though).  I've tried placing the flip-flops in the proper position using
RLOCs in the source, using the floorplanner and using the UCF file.  In
all 3 cases, some instances of this placed CLB give me an "Unable to
pack the register  because of connectivity restrictions".  This is not
happening for all the instances of this CLB (there are alot of them),
and in fact if I just put one down it places fine.  What I have found is
that if I leave one of the registers unplaced, the other seems to wind
up in FFY regardless of the RLOC extension (RLOC=R0C0.FFX.S1).  Xilinx
is looking at the problem, but seems to be having a little trouble
comprehending exactly what the problem is, even though I sent files.

In summary,  I want to share the BX input with the F5 mux control (for a
combinatorial output on X) and the D input to the FFX flip-flop.  The
mapper doesn't seem to respect the .FFX in RLOC=R0C0.FFX.S1.  Has
anybody seen this problem and found a work-around?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18962
Subject: Re: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
From: fuzzyyt@my-deja.com
Date: Tue, 23 Nov 1999 01:36:55 GMT
Links: << >>  << T >>  << A >>
In article <38379292.42AB@bwiil.jnj.com>,
  azarfati@bwiil.jnj.com wrote:
> Paul Oh wrote:
> >
> > Hi to all!
> >
> > My end-goal is to port my ISA card design to PCI.  This ISA card is
a
> > simple 8255-based I/O board.  It's details if you are interested are
at
> > http://www.boondog.com - see the Tutorials link.
> >
> > I have no PCI experience.  My impression is that one needs a FPGA or
other
> > programmable logic device (PLD) for PCI interfacing.
> >
> > I have no PLD experience but do know digital logic and digital
system
> > design (I am mechanical engineer).
> >
> > Xilinx and Altera sell affordable ($100 range) development kits and
> > software (student versions).
> >
> > Q.  For my stated end-goal which PLD should I begin my learning
curve on?
> > Q.  Are on-line PCI tutorials (in relation to my end-goal or porting
> >     ISA designs to PCI) ?
> >
> > Much appreciated,
> >
> > Paul Oh
>
> If you are porting an existing ISA design, the easiest path is to use
a
> standard PCI-interface chip. There are several companies which offer
> various solutions, including PCI-to-ISA. See PLX (www.plxtech.com)
AMCC
> (www.amcc.com) and V3 (www.vcubed.com).
>
> PCI-cores for FPGAs are usually intended for complex FPGAs in which
PCI
> interface is mandatory, but not a very large part of the design; they
> are also pretty expensive (NRE of $5K and above). There are also some
> FPGAs (QuickLogic, ORCA) which have a hard-wired PCI core built in.
All
> are probably overkill for your application.
>
> 		Regards
> 		Assaf Sarfati
>

PLX has a development board for its PCI9050 (PCI slave only) chip that
has a PCI->ISA implemented on it. It might be a good reference for your
design.

Hope this helps,
Yvonne


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Before you buy.
Article: 18963
Subject: Re: VHDL vs. schematic entry
From: fuzzyyt@my-deja.com
Date: Tue, 23 Nov 1999 01:50:42 GMT
Links: << >>  << T >>  << A >>
In article <81clcr$q4i$1@nnrp1.deja.com>,
  Greg Neff <gregneff@my-deja.com> wrote:
> I having been using schematic entry for FPGAs, probably because I have
> been drawing schematics since before the days of PALs, let alone
> FPGAs.  I am now considering taking the leap to VHDL entry, but I am
> not convinced that there will be a benefit in either time to design or
> design quality.
>
> I'm not talking about a situation where a team of engineers is
> designing a mega-gate FPGA.  I am more interested in small to
mid-range
> (say, up to 100K gate) designs that are being entered and maintained
by
> one person.
>
> I would be interested to hear from those people that have gone through
> the VHDL learning curve.
>
> Has the move to VHDL reduced design entry time?
> Has the design quality improved (fewer problems)?
> Is design debugging easier?
> Is design maintenance easier?
> Is design reuse easier?
> Did you get to the point where VHDL is more efficient than schematics?
> If so, how long did it take to get to this point?
> Bottom line: Was it worth it?
>
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>

For one thing, VHDL (or Verilog) is portable, so you should be able to
move between FPGA families or even manufacturers without making too many
changes to the design. This often helps early in your design stage.
You'll have less control over the synthesis results, though; since this
depends on the quality of the synthesis tool.


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Before you buy.
Article: 18964
Subject: Re: VHDL vs. schematic entry
From: phil_jackson@my-deja.com
Date: Tue, 23 Nov 1999 01:52:48 GMT
Links: << >>  << T >>  << A >>
I too started out designing at gate (schematic) level. It was a drag. I
spent quite a bit of time crunching boolean equations and doing Karnough
maps. Not a value added effort. Once you get into the mind set of
synchronous (single or as few as possible clocks) in VHDL (or verilog),
I suspect you will never want to go back to gate level.

> Has the move to VHDL reduced design entry time?
Aboslutely. I spend very little time coding the design. I do spend quite
a bit of time coding test benches to run simulations on the design.

> Has the design quality improved (fewer problems)?
Yes. Since I am not resposible for converting my logical function into
gates (synthesis tool does that), there are fewer errors.

> Is design debugging easier?
Hard to say. You still have to stimulate your design. In VHDL, we use a
piece of VHDL called a test bench most often. One thing, you will be
able to simulate prior to synthesis and the simulations run much faster
at this level than once you have synthesized the design into gates. How
much longer? My last design took about 1.5 days to run end to end
simulations on the design pre-route. The sames vectors run at gate level
took 2 weeks!!!

> Is design maintenance easier?
I think so. It's real easy to edit a line of code. Not so easy to
recalculate your karnough maps do to an added state.

> Is design reuse easier?
I am not a big proponent of this as it never seems to happen where I'm
at. I think there are items (like UARTS, PCI busses, etc) which are
perfectly reusable. However, the code you develop for a particular
requirement is often not reusable. I would think the same would be true
for gate level designs.

> Did you get to the point where VHDL is more efficient than schematics?
Yes.
> If so, how long did it take to get to this point?
It took me about 6 months of coding to really catch on and be able to
write something without grabing the book all the time.

> Bottom line: Was it worth it?
Absolutely. It's hard for me to imagine doing anything gate level, even
a 22V10. Why? VHDL is so much easier.


BTW, HDL (Verilog/VHDL) to me is a whole different style of design than
pasting gates together. It takes some getting used to. Especially, the
idea of using only one clock in the design (if possible). I call this
synchronous design. Sometimes, this is not possible, but the static
timing tools and FPGAs/ASICs all work better/easier if there is a single
clock in the design. People uses to gate level design find it hard to
get the idea of not clocking a flip flop with a single but rather
sampling that signal (over sampling). Essentially, use a 2 stage shift
register to sample a signal and look for Q0 = 1 and Q1 = 0 to detect a
rising edge. Synchronizing external input signals to the clock so as to
avoid metastability is also a prerequiste, but this is nothing new. It's
the same if you were doing it at gate level.

Good Luck!
PJ


In article <81clcr$q4i$1@nnrp1.deja.com>,
  Greg Neff <gregneff@my-deja.com> wrote:
> I having been using schematic entry for FPGAs, probably because I have
> been drawing schematics since before the days of PALs, let alone
> FPGAs.  I am now considering taking the leap to VHDL entry, but I am
> not convinced that there will be a benefit in either time to design or
> design quality.
>
> I'm not talking about a situation where a team of engineers is
> designing a mega-gate FPGA.  I am more interested in small to
mid-range
> (say, up to 100K gate) designs that are being entered and maintained
by
> one person.
>
> I would be interested to hear from those people that have gone through
> the VHDL learning curve.
>
> Has the move to VHDL reduced design entry time?
> Has the design quality improved (fewer problems)?
> Is design debugging easier?
> Is design maintenance easier?
> Is design reuse easier?
> Did you get to the point where VHDL is more efficient than schematics?
> If so, how long did it take to get to this point?
> Bottom line: Was it worth it?
>
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18965
Subject: Re: VHDL vs. schematic entry
From: Ray Andraka <randraka@ids.net>
Date: Mon, 22 Nov 1999 21:01:46 -0500
Links: << >>  << T >>  << A >>


fuzzyyt@my-deja.com wrote:

> For one thing, VHDL (or Verilog) is portable, so you should be able to
> move between FPGA families or even manufacturers without making too many
> changes to the design. This often helps early in your design stage.
> You'll have less control over the synthesis results, though; since this
> depends on the quality of the synthesis tool.
>

Even working at the RTL level, you really should be designing to the
architecture if you want good quality results.  The tools can only infer so
much.  A portable design is not going to a stellar performer nor is it as
small as it can be.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18966
Subject: Re: VHDL vs. schematic entry
From: Greg Neff <gregneff@my-deja.com>
Date: Tue, 23 Nov 1999 03:06:37 GMT
Links: << >>  << T >>  << A >>
In article <81cs1f$us4$1@nnrp1.deja.com>,
  phil_jackson@my-deja.com wrote:
(snip)
> BTW, HDL (Verilog/VHDL) to me is a whole different style of design
than
> pasting gates together. It takes some getting used to. Especially, the
> idea of using only one clock in the design (if possible). I call this
> synchronous design. Sometimes, this is not possible, but the static
> timing tools and FPGAs/ASICs all work better/easier if there is a
single
> clock in the design.
(snip)

Thank you for you detailed response.  I absolutely agree that proper
synchronous design practices are required.  This is true for FPGAs, no
matter what design entry method is used.  My concern is how to enforce
these design rules in VHDL.  In a schematic I can force a global buffer
to be used for clock distribution.  How hard is it to do this in VHDL?
Also, for synchronizing registers I can define a special timing
constraint that will guarantee the extra setup time margin needed
between synchronizing registers, to reduce the probability of
metastability.  How hard is it do this in VHDL?

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


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Article: 18967
Subject: Re: VHDL vs. schematic entry
From: "John Doe" <h2p@hotmail.com>
Date: Mon, 22 Nov 1999 19:46:14 -0800
Links: << >>  << T >>  << A >>
VHDL or Verilog is the only way to go for many reasons.

1. Re-use is as simple as cut and paste (almost)
2. Portability - most schematic entry tools that I know of use vedor
specific libraries (I definately do not recommend this).
3. Simulation was made so much easier (this alone is an excellent reason to
change over).

For ease of use, if you already know a programming language like C or
Fortran or Pascal, then you will have absolutely no problems with VHDL.
Even if you dont it shouldnt take long for you to learn.   I am currently
converting people at my company over from schematic to VHDL and very few are
hesitant to do it once they see the power of an HDL.

I do recommend a package called Active-HDL if you are interesed in just
giving it a try.  They have a free trial version available at
http://www.aldec.com.  I went through the training that they offered on VHDL
and it was very good (and very low cost for what you get).  This program
comes packed with tons of examples and a pretty descent online help.  It
also includes a tutorial that was made by esperian I believe.  Damn... I
should be making money for a sales pitch like that :).  Bottom line... its a
very good package for learning VHDL and making fast easy designs.

Bottom line... VHDL is an order of maginitude better from my point of view.

Good luck.

Greg Neff <gregneff@my-deja.com> wrote in message
news:81clcr$q4i$1@nnrp1.deja.com...
> I having been using schematic entry for FPGAs, probably because I have
> been drawing schematics since before the days of PALs, let alone
> FPGAs.  I am now considering taking the leap to VHDL entry, but I am
> not convinced that there will be a benefit in either time to design or
> design quality.
>
> I'm not talking about a situation where a team of engineers is
> designing a mega-gate FPGA.  I am more interested in small to mid-range
> (say, up to 100K gate) designs that are being entered and maintained by
> one person.
>
> I would be interested to hear from those people that have gone through
> the VHDL learning curve.
>
> Has the move to VHDL reduced design entry time?
> Has the design quality improved (fewer problems)?
> Is design debugging easier?
> Is design maintenance easier?
> Is design reuse easier?
> Did you get to the point where VHDL is more efficient than schematics?
> If so, how long did it take to get to this point?
> Bottom line: Was it worth it?
>
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 18968
Subject: Leonardo Spectrum Printing Problem
From: "John Doe" <h2p@hotmail.com>
Date: Mon, 22 Nov 1999 19:52:22 -0800
Links: << >>  << T >>  << A >>
Leonardo Spectrum is a pretty good synthesis tool except for "1" thing....
printing your schematics.

I have asked their support team time and time again to fix the built in
schematic viewer and for 20k+ a seat you think they would do that right???
NO.  Instead the only reply that I got was I can either use the old
schematic viewer that will not show higher levels of your design (i.e. you
get 300 plus pages to print out) or use the new schematic tool and use cut
and paste.  CUT AND PASTE!!! Has anyone seen the quality of the schematic in
the first place.  If you were to print that out in say Word you would get 1
big black drawing.

This is just a gripe.  I am disapointed that Exemplar and other companies
cant seem to get their shit together and make some quality software (not
just the engine but the user interface!!!).




Article: 18969
Subject: Re: VHDL vs. schematic entry
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Tue, 23 Nov 1999 03:55:29 GMT
Links: << >>  << T >>  << A >>
On Tue, 23 Nov 1999 01:19:58 GMT,
allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote:

>>
>>I would be interested to hear from those people that have gone through
>>the VHDL learning curve.

Another suggestion: a text editor that understands the language syntax
is essential.  Go for one that also does template expansion.

For example, in the editor that I use (ed4w with VHDL extension), I
can type in "ca<esc>", and it comes back with:

case  is
    when        =>
    when others =>
end case;

This saves you a lot of typing and helps you up the learning curve.
It also makes it easier to enforce a coding standard.

I believe the FAQ lists a number of editors that support VHDL.

Regards,
Allan.
Article: 18970
Subject: Re: VHDL vs. schematic entry
From: "Austin Franklin" <austin@darkr99m.com>
Date: 23 Nov 1999 03:57:54 GMT
Links: << >>  << T >>  << A >>
> IMO, you missed the main advantage of VHDL.  It's a hardware
> description language.  You can make very detailed self checking
> testbenches, using all sorts of constructs (some of which aren't even
> sythesisable (like file I/O and floating point arithmetic)).
> I typically find that I end up with about the same number of lines of
> code in the test bench and the chip.

But that has nothing to do with what the original design was done in.  I
completely agree, HDL (Verilog or VHDL and C) make a very powerful
simulation environment.  We have used HDL test benches for years and years
to test our FPGA designs (and ASIC designs), but do most of the FPGA logic
in schematic.

You hit on one very important point, why the testbench in an HDL works so
well, it isn't synthesized.  Though the HDL compilers have improved a lot,
they still have failings when you need to control how the logic gets mapped
and placed, which a lot of high speed, complex or 'full' designs require.

The use of an HDL is analogous to the use of C code...one can write really
bad (inefficient) C code, but because the processors are SO fast today, the
inefficiency is masked.  Same with FPGAs.  The general theme is 'well, just
use a faster part'.  That works in some cases, but a lot of times, you
could just to it right, and save hundreds of thousands of $$ in part costs,
and fighting with making timing etc. if one just took the time to learn the
architecture, placed some key elements (mostly data path), built the logic
so it took advantage of the architecture, and spec'd the timing accurately.

One can do a bad job with schematics too ;-)




Article: 18971
Subject: Re: implementing TCP/IP on PLD
From: "Joseph C. Su" <sujosep@sympatico.ca>
Date: Tue, 23 Nov 1999 04:22:32 GMT
Links: << >>  << T >>  << A >>
Hopefully this question will not cause conflicts with the NDAs you signed:

Do you think it is realistic for an undergraduate design project to
undertake the task of implementing TCP/IP on FPGA ( i dare not to use the
term "pld" anymore), given a team of three not very smart students?

Appreciated.

Joseph Su

"Dirk Bruere" <artemis@kbnet.co.uk> wrote in message
news:816cpt$133$1@nclient9-gui.server.ntli.net...
>
> <email@inter.net> wrote in message news:38363B84.74B@inter.net...
> > OK, let's set the record straight:
> >
> > A full-featured TCP/IP stack has been done in an FGPA.  A pair of Xilinx
> > 4044's, actually.
> >
> > It was built on a PCI card; the processor could send an entire web page
> > to the card, then essentially say "go", and the FPGA's would do _all_
> > the rest; ACKs, retries, etc.  There was no CPU core.
> >
> > The design still exists, and would probably be for sale to the right
> > parties; just don't expect it to be anywhere near 'cheap'.  Probably on
> > the same scale as an ARM IP license.
> >
> > Sorry I can't say more; I signed an NDA before I worked on it.
> >
>
> Well, another lost opportunity for both of us.
> My port of TCP/IP is now in production with thousands being made. I would
> rather have just bought the stack in chip form and interfaced it like a
> normal IC.
>
> Dirk
>
>


Article: 18972
Subject: Re: Virtex: Getting flip-flops into the pads
From: simon_bacon@my-deja.com
Date: Tue, 23 Nov 1999 04:38:42 GMT
Links: << >>  << T >>  << A >>
I think this is because a synthesiser generates IFDs and OFDs
for XC4000 IOBs, whereas _all_ FFs in the Virtex are FDs.
So, in a sense, the synthesiser does generate IOB FFs for Virtex.

BTW, I think you have the xc_ioff sense inverted.  In the mangled
English of the Synplify help file : "The default value (1) is to turn
off the use of internal flip-flops."  I _think_ this means that
a zero will set the synthesiser to target the use of the FFs in
the IOBs.  But beware - I have never used this attribute.

  "Jamie Sanderson" <jamie@nortelnetworks.com> wrote:
> What still puzzles me is that I didn't need to do this with the XC4000
> series. The technology view for my designs clearly shows that it used
the
> registered I/O primitives (IFD, OFD, etc.). Regardless of the "map"
options,
> the Xilinx tools would respect that. It is troubling that I now have
to
> force the registers into the pads. Even with the "xc_ioff" attribute
set to
> 1 or true in Synplify, the technology view reveals that it is only
using
> IBUF or OBUF primitives. I would much rather the synthesis tool be
> responsible for the placement of the flip-flops, rather than Xilinx's
> mapper.


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Article: 18973
Subject: Re: implementing TCP/IP on PLD
From: "Dirk Bruere" <artemis@kbnet.co.uk>
Date: Tue, 23 Nov 1999 05:14:06 -0000
Links: << >>  << T >>  << A >>

Joseph C. Su <sujosep@sympatico.ca> wrote in message
news:cEo_3.62916$up3.99009@news21.bellglobal.com...
> Do you think it is realistic for an undergraduate design project to
> undertake the task of implementing TCP/IP on FPGA ( i dare not to use the
> term "pld" anymore), given a team of three not very smart students?

Basically, no.
However, you first want to have a look at what TCP/IP actually entails in
terms of code. There are some free stacks on the net (usually for DOS) with
source code.

Look at it and realise that you must re-code that in h/w.

If you do manage it, I expect that along with high marks you may also have a
commercial product.

Dirk


Article: 18974
Subject: Re: implementing TCP/IP on PLD
From: kkm@dtmx.com (Kirill 'Big K' Katsnelson)
Date: 23 Nov 1999 05:35:08 GMT
Links: << >>  << T >>  << A >>
In article <cEo_3.62916$up3.99009@news21.bellglobal.com>, Joseph C. Su  says...
>
>Hopefully this question will not cause conflicts with the NDAs you signed:
>
>Do you think it is realistic for an undergraduate design project to
>undertake the task of implementing TCP/IP on FPGA ( i dare not to use the
>term "pld" anymore), given a team of three not very smart students?

You'll need very good inderstanding on how IP, ICM and TCP work. But
first of all, you'll need lots of spare money to build your prototype,
4044s are around $500 a piece if memory serves me well. Big FPGAs are
unrealistic for student projects pricewise.

Big K



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