1994 Jul Aug Sep Oct Nov Dec 1994 1995 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1995 1996 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1996 1997 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1997 1998 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1998 1999 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 1999 2000 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2000 2001 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2001 2002 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2002 2003 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2003 2004 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2004 2005 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2005 2006 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2006 2007 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2007 2008 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2008 2009 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2009 2010 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2010 2011 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2011 2012 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2012 2013 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2013 2014 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2014 2015 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2015 2016 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2016 2017 Jan Feb Mar Apr 2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 18775

Article: 18775
Subject: Altera NOT-gate push back
From: "Jaap H. Mol" <jh_mol@wxs.nl>
Date: Sun, 14 Nov 1999 16:54:50 +0100
Links: << >>  << T >>  << A >>

Hi there,

I recently had a quiet nasty experience with a function being
implemented in a FLEX10K(50) device, while testing the board containing
this device in its system environment. The problem that I encountered
was caused by the fact that one of the outputs of the device, driving an
active-low chip-select of dual-port memory on the board, seemed to
"stuck" at 0. During VHDL simulation of the RTL-, post-synthesis- and
post-layout models, this problem did not occur.
In this particular design, the (faulty) output was directly driven by
the output of a register. The asynchronous preset input of this
flip-flop was directly attached to the reset of the board/system. This
implies that the output should be set to 1 whenever the board/system
reset is active. However, after measurement this did not seem to be the
case in "real" hardware. Instead, when the system/board reset was
permanently active (=0), the output was 0 instead of 1.
By lifting/desoldering the particular I/O pin of the device, we assured
that the FLEX10K device was driving the signal to 0, and not some other
logic on the board.
The next 3 to 4 days I spend checking/simulating/measuring and building
several alternative designs to isolate the cause of the problem. I found
and that other functions implemented in the FLEX10K device work well.

I knew that a Logic Element of a FLEX10K actually does not have a async
preset on its register, but that Maxplus2 emulates a preset
(preset-emulation) by using the clear/reset pin of its register, and
inverting both the register output and the data-input (LUT). Still, this
did not provide a cause for the problem I was having.
Then I read something about the NOT-gate push back option of the
logic-synthesizer of Maxplus2. Basically, this optimization technique
will move inverters being used on the output of a register to its
data-input (LUT), resulting in improved area/timing. Although this
optimization technique did not seem to be very relevant to the problem I
had, I decided to build my design with this option switched on (also
driven by my growing frustration ;-)....). My original design had this
option switched off e.g. no NOT-gate push back optimization.
During compilation, I now saw the message/info that all presetable
registers in my design would power-up high. (Not: this message did not
show up with NOT-gate push back switched off).

To make a (already way too) long story short, the (original) design
fully functioned when I use another optimization setting in Maxplus2!
Although I'm glad to have found the problem, I still don't fully
understand it. After all, Maxplus2 did not warn me about anything (even
the famous Design Doctor), all my simulations were working correctly,
I know that the issue I had has some kind of relation with topics like
preset-emulation (Maxplus2), power-up (FLEX10K) and (logic) optimization
(Maxplus2), but that where it ends for me.

Can somebody out there explain me what exactly happened, and why? This
can be extremely helpful to prevent problems like this in the future.
For anybody who had similar experiences: I would really appreciate it if
you could share them with me.

Best Regards,

Jaap Mol


Article: 18776
Subject: configure_flex10k30e_jtag_jam
From: a_maier@my-deja.com
Date: Sun, 14 Nov 1999 19:53:13 GMT
Links: << >>  << T >>  << A >>
Hello All i want to configure a altera flex10k30e using the jtag-port and a
jam-player. I am using MAX+II vers. 9.30 and the update to 9.31 applied to
it. The jam-player i ported for my hardware is vers. 2.12. When running the
JAM/STAPL file of my design an error occurs (even with the original 16bit
jam-player jam.exe). The error is "Error on line 35: action name not found."
Is there anybody who has experience in configuring flex devices with JAM?

Andreas

Sent via Deja.com http://www.deja.com/

Article: 18777
Subject: test
From: "George" <g_roberts75@hotmail.com>
Date: Sun, 14 Nov 1999 22:48:10 -0000
Links: << >>  << T >>  << A >>



Article: 18778
Subject: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
From: "John Doe" <h2p@hotmail.com>
Date: Sun, 14 Nov 1999 17:09:47 -0800
Links: << >>  << T >>  << A >>
I have also tried all 3 and find the same results.  I do like the interface
to Leonardo a little better but it may be just because I am used to it.

Bottom line, I would not recommend FPGA Express.

Either Leonardo or Synplicity should do just fine for you.

<malino@primenet.com> wrote in message
news:80is4p$j5s$1@nnrp02.primenet.com...
> I have used all three tools and have no problem rating them.
>  Synplicity Synplify  Exemplar Leonardo Spectrum about equal
>  Synopsys FPGA Express a distant third.
>
>
>
> Greg Neff <gregneff@my-deja.com> wrote in message
> news:80f06r$4pi$1@nnrp1.deja.com...
> > We are evaluating these tools.  I would appreciate any comments from
> > those of you that have experience with at least two of the following
> > tools:
> >
> > Synopsys FPGA Express
> > Synplicity Synplify
> > Exemplar Leonardo Spectrum
> >
> > --
> > Greg Neff
> > VP Engineering
> > *Microsym* Computers Inc.
> > greg@guesswhichwordgoeshere.com
> >
> >
> > Sent via Deja.com http://www.deja.com/
>
>


Article: 18779
From: drl3 <drl3@ukc.ac.uk>
Date: Mon, 15 Nov 1999 12:33:01 +0000
Links: << >>  << T >>  << A >>
Hi,
Is it possible to get circuit designs of the Altera programming leads,
such as the byte blaster, and bit blater devices, if so any body know
where. All help much appreciated.

Cheers Dale.

Article: 18780
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Mon, 15 Nov 1999 14:03:57 +0100
Links: << >>  << T >>  << A >>
Hi
The ByteBlaster schematics was in the 1998 Data Book, we built one last
year and it works fine.
Search for the data sheet on Altera's Web Site

drl3 wrote:
>
> Hi,
>         Is it possible to get circuit designs of the Altera programming leads,
> such as the byte blaster, and bit blater devices, if so any body know
> where. All help much appreciated.
>
> Cheers Dale.

--
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE

Article: 18781
Subject: Need advice on interfacing SDRAM modules
From: Maciej Bartkowiak <mbartkow@et.put.poznan.pl>
Date: Mon, 15 Nov 1999 17:52:01 +0100
Links: << >>  << T >>  << A >>
Dear All

Here, at the University, we are running a design project that involves
interfacing the SDRAM modules with a custom FPGA-based system. We have
to cope with severe problems related to the complexity of SDRAM control.
We badly need advice from experienced designers of uC systems and would
be truly thankful for some hints. We are looking for any possibilities
to contact such experts, so please let us know if you know any.

thank you very much,

m.b.

--

Maciej Bartkowiak, PhD
========================================================================
Institute of Electronics and Telecommunication     fax: (+48 61) 6652572
Poznan University of Technology                  phone: (+48 61) 6652171
Piotrowo 3A                             email: mbartkow@et.put.poznan.pl
60-965 Poznan POLAND               http://www.et.put.poznan.pl/~mbartkow
========================================================================

Article: 18782
Subject: Xilinx m2.1i Service Pack #2 installation problems
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Mon, 15 Nov 1999 18:52:33 +0200
Links: << >>  << T >>  << A >>
I started to run the setup with perl on UNIX, but the GUI
vanished when I press NEXT button in Welcome message of
setup GUI. Is there any workaround you know?

--
I feel better than James Brown.


Article: 18783
Subject: Strongest/Fastest Logic Reduction?
From: Armin Mueller <armin.mueller@stud.uni-karlsruhe.de>
Date: Mon, 15 Nov 1999 18:09:42 +0100
Links: << >>  << T >>  << A >>
Hello,

I wonder which (two stage) logic reduction method is most practicable
(and used in common design utilities). Where can I find a comparison?

e.g.

McCluskey (Lattice Synario, strong, much memory + slow)
Espresso (fast, result not deterministic)
??? in Altera MaxPlusII (fast!)

Thanks!

Armin


Article: 18784
Subject: Re: Need advice on interfacing SDRAM modules
From: jhallen@world.std.com (Joseph H Allen)
Date: Mon, 15 Nov 1999 18:25:24 GMT
Links: << >>  << T >>  << A >>
In article <38303A31.6A89@et.put.poznan.pl>,
Maciej Bartkowiak  <mbartkow@et.put.poznan.pl> wrote:
>Dear All

>Here, at the University, we are running a design project that involves
>interfacing the SDRAM modules with a custom FPGA-based system. We have
>to cope with severe problems related to the complexity of SDRAM control.

SDRAMs are not too hard.  A way to simplify the problem is to make seperate
one-hot state machines for each operation: initialize, refresh, read,
write, read continuous burst, write continuous burst.  OR the control
signals together and feed them to the SDRAMs though output flipflops.  Of
course there will also be control signals for the bus multiplexor and the
pipeline delays all have to match properly.

If you can stand a few errors and the time the SDRAM has to hold its
contents is short (1 or 2 seconds), don't bother with refresh.

Use FPGA ram to buffer your device to the SDRAM.  Transfer a burst of four
or more words to/from the fpga buffer and have your device talk to this
buffer (which just looks like registers in Xilinx) when the bursts are
complete.  You could make a complete FIFO, but this is often unnecessary if
you can figure out how to make everything cooperate.

If your device's clock and data rate matches the SDRAM clock you can use
continuous burst mode.  It is easiest to match the SDRAM clock to whichever
device has the fixed data rate.  Use the FPGA ram buffers for the CPU
interface (or whatever part can wait).
--
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}

Article: 18785
Subject: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Mon, 15 Nov 1999 15:46:18 -0500
Links: << >>  << T >>  << A >>
It's been a couple of years since I looked at FPGA Express and Leonardo,
I use Synplicity extensively. The last time I looked at FPGA Express I
hated it, I found the UI unusable because it pretty much forced you to
use the GUI and I do everything through scripts. Synplicity works very
well for Verilog, I've occasionally run into problems with VHDL. The
only real problem with Synplicity is that it's batch mode demands an X
window, even though it's not using it, and periodically it decides that
it needs to enumerate all of the fonts on the machine which can take an
hour.

Olav Gundersen wrote:
>
> We are currently using the Synopsys FPGA Express, and I can summarize
> like this:
>
> have spent more time on installing/uninstalling the program + making the
> license manager (FlexLM) work properly than we have spent on our
> designs. I think that licensing the program must be a great cost for
> Xilinx who we bought it from.
>
> Using the tool: I think it is ok once it works. Have had some trouble
> not finding the library even though all of them are installed an still
> on the disk. The only way I found to solve this was to reinstall the
> program.
>
> Overall, if there had been no license problems, I would hesitate to
> recommend it. Still, I think we have spent so much time on this that the
> cheep price of the tool doesn't matter anymore.
>
> Greg Neff wrote:
>
> > We are evaluating these tools.  I would appreciate any comments from
> > those of you that have experience with at least two of the following
> > tools:
> >
> > Synopsys FPGA Express
> > Synplicity Synplify
> > Exemplar Leonardo Spectrum
> >
>
> --
> ------------------------------------------
>
> Olav Gundersen
> Development Engineer

Article: 18786
Subject: Re: WHERE can I find xc9536_v2.bsd??!
From: "Paul Taylor" <p.taylor@ukonline.nospam.co.uk>
Date: Tue, 16 Nov 1999 00:00:37 -0000
Links: << >>  << T >>  << A >>
This one bit me without warning on an existing product using 95108's.

I found a reference to this problem on the xilinx web page somewhere.
Basially, you need to upgrade to 1.5i or later, to support the new silicon.

Paul.

Uday Godbole <udayg@technofour.com> wrote in message
news:s2qb9573hsq84@news.supernews.com...
> I am a newbie using Xilinx Foundation Series 1.5 with XC9536VQ44-15 CPLD.
> With a deadline fast looming. Writing in some panic.
>
> I have used schematic editor entry tool and done implementation
successfully
> without errors. But trying to download to device through the JTAG
programmer
> I get the following error:
>
> -------------------------------------------------------------------
> JTAG Programmer Started 1999/11/13 01:53:25
> 'C:/fndtn/data/xc9536.bsd'.....completed successfully.
> Checking boundary-scan chain integrity...done.
> Verifying device positions in boundary-scan chain...
> Instance 'ect(Device1)' at position '1'...verified.
> Verification completed.
> Boundary-scan chain validated successfully.
> 'ect(Device1)': Checking boundary-scan chain integrity...
> ERROR:basut - Unable to locate BSDL file 'xc9536_v2.bsd'.
>  Check that your XILINX variable is properly set and
> that the BSDL file is located along its path.
> 'ect(Device1)': Programming terminated due to errors.
> ---------------------------------------------------------------------
>
> Where can I find xc9536_v2.bsd file ?
>
> Foundation has only xc9536.bsd. Does JTAG detect version of XC9536
soldered
> to PCB ?  In desparation I tried renaming the xc9536.bsd as xc9536_v2.bsd,
> but that does not help.
>
> A search on Xilinx website proved futile, and a websearch on three engines
> could not locate this file :(
>
> Would really appreciate any help!
>
> Uday
>
>
>


Article: 18787
Subject: Re: configure_flex10k30e_jtag_jam
From: steve (Steve Rencontre)
Date: Tue, 16 Nov 1999 01:03 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <80n3v8$lpi$1@nnrp1.deja.com>, a_maier@my-deja.com () wrote:

> Hello All i want to configure a altera flex10k30e using the jtag-port
> and a
> jam-player. I am using MAX+II vers. 9.30 and the update to 9.31 applied
> to
> it. The jam-player i ported for my hardware is vers. 2.12. When running
> the
> JAM/STAPL file of my design an error occurs (even with the original
> 16bit
> jam-player jam.exe). The error is "Error on line 35: action name not
> found."
> Is there anybody who has experience in configuring flex devices with
> JAM?

I don't know if it's still the case, but older versions of the JAM player
wouldn't work with FLEX10K devices because of 64k limitations, even when
compiled as 32-bit code for WinNT/9x.

I did a custom configuration program for a client with that problem;
apparently Altera had publicly claimed it would be fixed in the next
release, but privately admitted it wouldn't be a good idea to hold your
breath. I looked at the Altera code with a view to patching it, but

It may be something else entirely - I don't recognise that particular
error message - but it's the first thing I'd check. And if you want a
small, fast program that will configure any number of FLEX10Ks in an
arbitrary JTAG chain, with no practical limits even in 16-bit
implementation, feel free to mail me for a quote :-)

--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk

Article: 18788
Subject: Re: Altera NOT-gate push back
From: murray@pa.dec.com (Hal Murray)
Date: 16 Nov 1999 04:15:44 GMT
Links: << >>  << T >>  << A >>


[Long saga snipped]

> To make a (already way too) long story short, the (original) design
> fully functioned when I use another optimization setting in Maxplus2!
> Although I'm glad to have found the problem, I still don't fully
> understand it.

This is why I claim that the microscope and bit tweezers are a
necessary part of any FPGA tool package.

With a good microscope, you can go in there and look at what
the compiler and friends really did.  Maybe someday they won't be
necessary but I'm not going to hold my breath.

--
These are my opinions, not necessarily my employers.

Article: 18789
Subject: Lattice LXOR2 Question
From: "John Doe" <h2p@hotmail.com>
Date: Mon, 15 Nov 1999 20:39:19 -0800
Links: << >>  << T >>  << A >>
Hello,

I am running into a problem when I go to fit a design in a Lattice part.
The error I get is too many LXOR gates are used.  I found a way to get
around this problem before but dont recall how I did it.  I am using
Leonardo Spectrum for synthesis and then Lattice Expert Compiler for
fitting.   Anyone have any ideas?  I thought it was something I set in
Leonardo (like do not use LXOR2 gates but I dont see that ability)

Any help would be appreciated.

Thanks


Article: 18790
Subject: OLD programming Software
From: Craig Humphrey <craig@stallion.oz.au>
Date: Tue, 16 Nov 1999 15:14:39 +1000
Links: << >>  << T >>  << A >>
G'day,

I know this is a long shot but does anyone still have the old 'Prolink'
software for the Xilinx HW-120 programmer?
[This programmer was made by logical devices.]

From what I can remember it was DOS software and on floppy disks.

The HW-130 SW on xilinx web does not work, and there is no trace of
anything older.

Thanks,
Craig

Article: 18791
Subject: Re: Need advice on interfacing SDRAM modules
From: mar@tcelectronic.com
Date: Tue, 16 Nov 1999 07:58:13 GMT
Links: << >>  << T >>  << A >>
Hello Maciej

Have a look at an article, published in EDN 020298:

Analyzing and implementing SDRAM and SGRAM controllers, available at:
http://www.ednmag.com/reg/1998/020298/03df_04.htm

You'll have to register at edn, to get access to the article.

Regards,
Martin Roenne
TC Electronic

In article <38303A31.6A89@et.put.poznan.pl>,
Maciej Bartkowiak <mbartkow@et.put.poznan.pl> wrote:
> Dear All
>
> Here, at the University, we are running a design project that involves
> interfacing the SDRAM modules with a custom FPGA-based system. We have
> to cope with severe problems related to the complexity of SDRAM
control.
> We badly need advice from experienced designers of uC systems and
would
> be truly thankful for some hints. We are looking for any
possibilities
> to contact such experts, so please let us know if you know any.
>
> thank you very much,
>
> m.b.
>
> --
>
> Maciej Bartkowiak, PhD
>
========================================================================
> Institute of Electronics and Telecommunication     fax: (+48 61)
6652572
> Poznan University of Technology                  phone: (+48 61)
6652171
> Piotrowo 3A                             email:
mbartkow@et.put.poznan.pl
> 60-965 Poznan POLAND
http://www.et.put.poznan.pl/~mbartkow
>
========================================================================
>

Sent via Deja.com http://www.deja.com/

Article: 18792
Subject: Re: WHERE can I find xc9536_v2.bsd??!
From: Klaus Falser <kfalser@durst.it>
Date: Tue, 16 Nov 1999 08:17:38 GMT
Links: << >>  << T >>  << A >>
In article <80q6tl$4g6$1@apple.news.easynet.net>,
"Paul Taylor" <p.taylor@ukonline.nospam.co.uk> wrote:
> ..
> Basially, you need to upgrade to 1.5i or later, to support the new
silicon.
>

Look for "WebPack".

--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen

Sent via Deja.com http://www.deja.com/

Article: 18793
Subject: How to use GSR-net in Virtex?
From: "alco" <alco@cardiocontrol.com>
Date: Tue, 16 Nov 1999 10:49:21 +0100
Links: << >>  << T >>  << A >>
How do i set/preset several hundreds of flipflops synchronously using a
single signal?  Using the startup_virtex component, an external signal can
control the GSR signal of the virtex device. However, how do i make clear to
a vhdl synthesizer that the reset signal in

entity Eblabla is
port (
clk, reset     : in std_logic ;
..........
) ;

is actually the GSR-signal. The GSR is not made available by startup_virtex,
so it can not be connected to the components that use it.
How do i solve this ?

thanks,

Alco Looye
alco@cardiocontrol.com


Article: 18794
Subject: What happens to power-on-reset when external signals control the GSR
From: "alco" <alco@cardiocontrol.com>
Date: Tue, 16 Nov 1999 12:46:26 +0100
Links: << >>  << T >>  << A >>
when using the startup_virtex and having an external signal control the GSR,
will flipflops set and reset after configuration as it would normally. So is
it possible to have two different reset events (external signal and end of
config) control GSR ?

Alco

alco <alco@cardiocontrol.com> wrote in message
news:80r9cs$efd$1@buty.wanadoo.nl...
> How do i set/preset several hundreds of flipflops synchronously using a
> single signal?  Using the startup_virtex component, an external signal can
> control the GSR signal of the virtex device. However, how do i make clear
to
> a vhdl synthesizer that the reset signal in
>
>     entity Eblabla is
>         port (
>             clk, reset     : in std_logic ;
>             ..........
>         ) ;
>
> is actually the GSR-signal. The GSR is not made available by
startup_virtex,
> so it can not be connected to the components that use it.
> How do i solve this ?
>
> thanks,
>
> Alco Looye
> alco@cardiocontrol.com
>
>


Article: 18795
Subject: Re: How to use GSR-net in Virtex?
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 16 Nov 1999 10:41:56 -0700
Links: << >>  << T >>  << A >>
alco wrote in message <80r9cs$efd$1@buty.wanadoo.nl>...
>How do i set/preset several hundreds of flipflops synchronously using a
>single signal?  Using the startup_virtex component, an external signal can
>control the GSR signal of the virtex device. However, how do i make clear
to
>a vhdl synthesizer that the reset signal in
>
>    entity Eblabla is
>        port (
>            clk, reset     : in std_logic ;
>            ..........
>        ) ;
>
>is actually the GSR-signal. The GSR is not made available by
startup_virtex,
>so it can not be connected to the components that use it.
>How do i solve this ?

Don't instantiate the startup block.  Just make sure that the reset signal
goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool
should infer GSR.  If it does not, you should get a message saying that it
was not inferred, and you'll have to look at the synthesis report to see
which flops were not included.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.


Article: 18796
Subject: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
From: Jason.Wright@ericsson. (Jason T. Wright)
Date: Tue, 16 Nov 1999 21:29:01 GMT
Links: << >>  << T >>  << A >>
I've used FPGA Express and am using Leonardo Spectrum.  I migrated from
FPGA Compiler.  In terms of usability, I'm not convinced anybody has it
perfect yet.  But the bottom line is I have gotten FPGA Compiler, FPGA
Express, and Leonardo Spectrum all to do my bidding. ;-]

Seriously, I used scripting in each.  For FPGA Comiler and Express, I
didn't use the GUI at all, except on occasions to figure out the syntax of
my directives.  (Often the easiest thing is to have the tool do something
that you want, observe how it did it, and then add to your script
accordingly.)  For Leonardo Spectrum (on the PC--the others ran on a unix
workstation) I am using the GUI, but I have it all scripted and the
overhead is minimal.  (And the feedback is quicker.)

In comparison runs, Leonardo Spectrum was slightly better (lower CLB usage)
that FPGA Express, which was slightly better than FPGA Compiler.   Gate
counts to ~70k.  I did not give the VHDL synthesis tools any timing
constraints; I provided a ucf file for the Xilinx back-end tools, and I
wrote my VHDL in such a way that I could control critical timing where
needed (minimal logic between flip-flops, ...)  YMMV.

In regards to the licensing, I only had a few problems which were quickly
resolved while talking with Mentor Graphics' tech support.  Things like
location of the daemons (I didn't have the appropriate one installed for

Jason T. Wright

On Mon, 15 Nov 1999 15:46:18 -0500, "B. Joshua Rosen" <bjrosen@polybus.com>
wrote:

>It's been a couple of years since I looked at FPGA Express and Leonardo,
>I use Synplicity extensively. The last time I looked at FPGA Express I
>hated it, I found the UI unusable because it pretty much forced you to
>use the GUI and I do everything through scripts. Synplicity works very
>well for Verilog, I've occasionally run into problems with VHDL. The
>only real problem with Synplicity is that it's batch mode demands an X
>window, even though it's not using it, and periodically it decides that
>it needs to enumerate all of the fonts on the machine which can take an
>hour.
>
[snip]
>>
>> Greg Neff wrote:
>>
>> > We are evaluating these tools.  I would appreciate any comments from
>> > those of you that have experience with at least two of the following
>> > tools:
>> >
>> > Synopsys FPGA Express
>> > Synplicity Synplify
>> > Exemplar Leonardo Spectrum
>> >
>>
>> --
>> ------------------------------------------
>>
>> Olav Gundersen
>> Development Engineer


Article: 18797
Subject: Q: implementing TCP/IP on PLD
From: sujosep@ecf.toronto.edu (Joseph Su)
Date: 16 Nov 99 22:13:32 GMT
Links: << >>  << T >>  << A >>
fellow netters,

as a part of our engineering design project, we need to investigate the
possibility of implementing TCP/IP on PLDs. relatively new to the
concept of TCP/IP and PLD, we hope that newsgroups may provide us with
some insightful hints and suggestions regarding the topic. the reason of
considering TCP/IP on PLD is in hope to concentrate RAM, PROM, and
microprocessor into one chip, and use such chip to perform simple and
speed demanding network applications.

the questions raised are:
1. how does networking protocols implemented in network products, ie.
routers and bridges? do they use microcontrollers or PLDs?
2. what are the advantages of using microcontroller (plus RAM, PROM)
over PLD in dedicated network applications ? if there are any.
3. if software on PROM can be upgraded via periodic firmware updates,
can it is also be done easily on PLD? ie. reprogram PLD on the spot.
4. what is the minimum TCP/IP function set required to do simple file
transfer and etc.?
5. are there any resources available on this topic?

we will welcome all comments and suggestions. please feel free to write
us at sujosep@ecf.toronto.edu. thank you all.

--
Chao.
+-----------------------------------------------------------------------+
|       Email:  sujosep@ecf.toronto.edu         sujosep@ieee.org        |
|       Phone:  (905)507-1888                                           |
+-----------------------------------------------------------------------+


Article: 18798
Subject: Re: Q: implementing TCP/IP on PLD
From: wavefront@SPAMbigfoot.com (martin griffith)
Date: Wed, 17 Nov 1999 00:09:12 GMT
Links: << >>  << T >>  << A >>

On 16 Nov 99 22:13:32 GMT, sujosep@ecf.toronto.edu (Joseph Su)
scribbled:

YE GODS THIS GUY HAS AN IEEE.ORG  FUCKING ADDRESS: ( but he is from
>fellow netters,
>
>as a part of our engineering design project, we need to investigate the
>possibility of implementing TCP/IP on PLDs.
PLD are VERY SMALL devices, 16R8 etc.they consume a vast amount of
power , they may do it very quick, but they are power hungry, and you
try working with PALASM!
>relatively new to the
>concept of TCP/IP and PLD, we hope that newsgroups may provide us with
>some insightful hints and suggestions regarding the topic. the reason of
>considering TCP/IP on PLD is in hope to concentrate RAM, PROM,
If  you are still thinking of PROM technology, you are way out of
date, try and get your money back from the course you are taking

>and
>microprocessor into one chip, and use such chip to perform simple and
>speed demanding network applications.
>
>the questions raised are:
>1. how does networking protocols implemented in network products, ie.
>routers and bridges? do they use microcontrollers or PLDs?
>2. what are the advantages of using microcontroller (plus RAM, PROM)
>over PLD in dedicated network applications ? if there are any.
An AVR/PIC type chip can run at say 10MIPS, are easy to programme.
>3. if software on PROM can be upgraded via periodic firmware updates,
>can it is also be done easily on PLD? ie. reprogram PLD on the spot.
See AVR/ PIC
>4. what is the minimum TCP/IP function set required to do simple file
>transfer and etc.?
a bit of research. not just asking "how do i do this", thats my line.
>5. are there any resources available on this topic?
>
If you have to ask this question, you ought to get a job in Human
(mis)Resources, maybe you've heard that people are very interested in
the intenet.
>we will welcome all comments and suggestions. please feel free to write
>us at sujosep@ecf.toronto.edu. thank you all.
>
>--
>Chao.
>+-----------------------------------------------------------------------+
>|       Email:  sujosep@ecf.toronto.edu         sujosep@ieee.org        |
>|       Phone:  (905)507-1888                                           |
>+-----------------------------------------------------------------------+
>
M'Lud, I rest my case, and sorry If I've hurt your feelings.

Martin


Article: 18799
Subject: Re: implementing TCP/IP on PLD
From: "Dirk Bruere" <artemis@kbnet.co.uk>
Date: Wed, 17 Nov 1999 01:27:40 -0000
Links: << >>  << T >>  << A >>

Joseph Su <sujosep@ecf.toronto.edu> wrote in message
news:3831D70A.90CDD0A2@ecf.toronto.edu...

> as a part of our engineering design project, we need to investigate the
> possibility of implementing TCP/IP on PLDs. relatively new to the
> concept of TCP/IP and PLD, we hope that newsgroups may provide us with
> some insightful hints and suggestions regarding the topic. the reason of
> considering TCP/IP on PLD is in hope to concentrate RAM, PROM, and
> microprocessor into one chip, and use such chip to perform simple and
> speed demanding network applications.

Forget 'simple' with a TCP/IP stack.
The simplest would be using datagrams (UDP protocol), which you might be
able to squeeze into about 1k of uP code if you are skilful. Full
implementations you are talking about 25K+ of code on a fast uP.

> the questions raised are:
> 1. how does networking protocols implemented in network products, ie.
> routers and bridges? do they use microcontrollers or PLDs?

Microcontrollers. The AMD186 series is popular.

> 2. what are the advantages of using microcontroller (plus RAM, PROM)
> over PLD in dedicated network applications ? if there are any.

Lots and lots of software.

> 3. if software on PROM can be upgraded via periodic firmware updates,
> can it is also be done easily on PLD? ie. reprogram PLD on the spot.
> 4. what is the minimum TCP/IP function set required to do simple file
> transfer and etc.?
> 5. are there any resources available on this topic?

Yes and no.
What you are trying to do is *very* difficult - to the extent that (AFAIK)
only one manufacturer is vending TCP/IP on a chip with no legal strings
attached, and that's a custom uP.

Dirk