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Messages from 19200

Article: 19200
Subject: Re: hobbyist friendly pld?
From: "Pascal Dornier" <pdornier@pcengines.com>
Date: Sun, 5 Dec 1999 13:45:53 -0800
Links: << >>  << T >>  << A >>
Xilinx XC95xxx should work for you. The 3.3V version (XL) is significantly
cheaper than the 5V version.

--------------------------------------------------------------------
Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
Your Spec      + PC Engines            = Custom Embedded PC Hardware
--------------------------------------------------------------------

Dan Rymarz wrote in message <384AD812.858079EF@boeing.com>...
>Hello all,
>
>I am looking for a programmable logic technology I can use that
>also has a free+permanant (not 30 day trial) compiler available, that
>uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
>don't need a large gate count.  It seems like the  big devices need big
>software, and the small ones need special programming hardware.  Does
>anyone know where this holy grail of digital hobbyist devices exists -
>free s/w and simple h/w?
>
>                                                      Thanks,
>                                                             Dan


Article: 19201
Subject: NOT PCI TO PCI BUS....how it is possible with FPGA?
From: Gabry <colornig@tin.it>
Date: Mon, 06 Dec 1999 00:03:04 +0100
Links: << >>  << T >>  << A >>
Hi to everybody,
does enyone know if there already exist a project based on fpga that
allow to interface my not pci bus to a standard pci bus?
Every links or books titles are welcome.
Tanks,
Gabry.

p.s.= please, aswer me by email.

Article: 19202
Subject: Re: hobbyist friendly pld?
From: Dave Vanden Bout <devb@xess.com>
Date: Sun, 05 Dec 1999 20:17:36 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F4826BC6720345AF47F6D1D3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

You can also get the free webpack software from the XILINX web site.  It supports VHDL, Verilog, and ABEL for all sizes of the XC9500 devices.  Take a look at http://www.xess.com/webpack.pdf for a tutorial on how to get, install, and use the webpack tools.



Pascal Dornier wrote:

> Xilinx XC95xxx should work for you. The 3.3V version (XL) is significantly
> cheaper than the 5V version.
>
> --------------------------------------------------------------------
> Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
> Your Spec      + PC Engines            = Custom Embedded PC Hardware
> --------------------------------------------------------------------
>
> Dan Rymarz wrote in message <384AD812.858079EF@boeing.com>...
> >Hello all,
> >
> >I am looking for a programmable logic technology I can use that
> >also has a free+permanant (not 30 day trial) compiler available, that
> >uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
> >don't need a large gate count.  It seems like the  big devices need big
> >software, and the small ones need special programming hardware.  Does
> >anyone know where this holy grail of digital hobbyist devices exists -
> >free s/w and simple h/w?
> >
> >                                                      Thanks,
> >                                                             Dan

--------------F4826BC6720345AF47F6D1D3
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------F4826BC6720345AF47F6D1D3--

Article: 19203
Subject: Schematic Help Please....
From: "Arch^Mage" <arch__mage@hotmail.com>
Date: Sun, 5 Dec 1999 19:26:36 -0600
Links: << >>  << T >>  << A >>
Hello,

I have to design a working simulation of a cpu for a class, and I am having
problems figuring out how to initialize values into ram.  CAn anybody offer
some assistance of anykind???  I am using Xinlinx.  For parameters, we are
to use these settings:
XC4000XL                4010XLPC84                01
Any help on how to do this with built in ram or LogiBlox would be greatly
appreciated.

Thanks,
Matt
Arch__mage@hotmail.com



Article: 19204
Subject: Re: hobbyist friendly pld?
From: Leon Heller <leon_heller@hotmail.com>
Date: Mon, 06 Dec 1999 08:33:58 GMT
Links: << >>  << T >>  << A >>
In article <384AD812.858079EF@boeing.com>,
  Dan Rymarz <m261981@boeing.com> wrote:
> Hello all,
>
> I am looking for a programmable logic technology I can use that
> also has a free+permanant (not 30 day trial) compiler available, that
> uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
> don't need a large gate count.  It seems like the  big devices need
big
> software, and the small ones need special programming hardware.  Does
> anyone know where this holy grail of digital hobbyist devices exists -
> free s/w and simple h/w?
>

Get the Xilinx starter kit. It comes with a JTAG programmer, a little
CPLD evaluation board, and software that supports the CPLDs and the
Spartan series of FPGAs, as well as the older devices. It's about $100.


Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19205
Subject: Re: Schematic Help Please....
From: mushh@slip.net (Dave Decker)
Date: Mon, 06 Dec 1999 08:43:56 GMT
Links: << >>  << T >>  << A >>
Matt,

If all you want to do is kill all the RAM error messages in the
simulation, you can put this line at the top of your command file:

report -memerrs 	|stops memory error reporting

As the comment says, it stops memory error reporting, which may not be
a good thing.

I use ViewLogic ViewDraw and ViewSim. Here's what I do.

For simulation:

Here's a piece of a file I call wiperam.cmd. In this case I have named
these RAM16x1s symbols ramf, ramg, ram0, ram1, ram2, and ram3

loadm clk_dly\ramf\ram (0:15) 0
loadm clk_dly\ramg\ram (0:15) 0

loadm sub_sampl\i_dly1\ram0\ram (0:15) 0
loadm sub_sampl\i_dly1\ram1\ram (0:15) 0
loadm sub_sampl\i_dly1\ram2\ram (0:15) 0
loadm sub_sampl\i_dly1\ram3\ram (0:15) 0

I name all my RAMs, then I put a line like these for every RAM in my
design. This just sets all locations to zero. At the start of my main
.cmd command file I have a call to this wiperam.cmd subroutine, by
simply including the line 
wiperam
in my command file.

Notice that each line has the adr of the RAM all the way down to the
RAM element inside the Xilinx RAM16x1s symbol, and that the name of
this lowest level part is 'RAM.' This is not easy to figure out from
reading the help file. Do read the help file, though, in the ViewSim
help. Look under 'loadm.'

If you want to set only location 3 to a 5 you would write:

loadm sub_sampl\i_dly1\ram0\ram (3) 5

You can use combinations of ranges and single locations to get the job
done.

For Place and Rout:

Attach an attribute to the RAM16x1s symbol such as:

init=89ab

for a 16x1 RAM.

where '89ab' is a 16 bit hex number with 8 the MSB.

Usually I don't bother putting inits on RAMs, but you can if you want.
It makes more sense for ROMs.

If you're using Foundation, I believe you can just use the 'init'
attribute, and it will work for both simulation and place and rout.


Good luck,

Dave Decker
I have only one 'h' in my email adr

On Sun, 5 Dec 1999 19:26:36 -0600, "Arch^Mage"
<arch__mage@hotmail.com> wrote:

>Hello,
>
>I have to design a working simulation of a cpu for a class, and I am having
>problems figuring out how to initialize values into ram.  CAn anybody offer
>some assistance of anykind???  I am using Xinlinx.  For parameters, we are
>to use these settings:
>XC4000XL                4010XLPC84                01
>Any help on how to do this with built in ram or LogiBlox would be greatly
>appreciated.
>
>Thanks,
>Matt
>Arch__mage@hotmail.com
>
>
>


Article: 19206
Subject: Re: Help with ROM in Xilinx Virtex
From: Samer EL HAJJ <Samer@SPAM-FILTERDotCom.fr>
Date: Mon, 06 Dec 1999 10:11:25 +0100
Links: << >>  << T >>  << A >>
Jamie Sanderson a écrit :

> Greetings;
>
> I'm hoping this is a simple question to answer.
>
> When I wanted to put a ROM into an XC4000, I ran Logiblox. Within that tool,
> I was able to specify the data values, size, etc.. Now I want to do the same
> with Virtex. However, after installing a fresh copy of M2.1i, the Logiblox
> tool doesn't offer Virtex as a device family. I also tried CoreGen, but it
> doesn't offer ROM's for the Virtex family (the option is greyed out). From
> what I can tell, this tool will only create Block RAM components for Virtex.
> The ROM I need is relatively small, so I prefer not to use the larger Block
> RAM elements.
>
> Anyhow, I would really appreciate it if someone could tell me how to
> generate ROM for Virtex. I haven't ruled out the possibility that I
> installed M2.1i improperly. However, I did select the data files for the
> Virtex devices I'd be using, and I'm able to do complete Virtex designs.
>
> Thanks in advance,
> Jamie Sanderson

Hi !
Why do not use the "Ditributed Memory" in CoreGen?
you can choose the memory type (ROM, Single Port RAM or dual Port)
It supports Virtex family after installing the Service Pack 2 ....

Regards,
Samer

--
Samer EL HAJJ
DotCom S.A. http://www.dotcom.fr
S@merWeb    http://samer.web.com


Article: 19207
Subject: Re: Help with ROM in Xilinx Virtex
From: Samer EL HAJJ <Samer@SPAM-FILTERDotCom.fr>
Date: Mon, 06 Dec 1999 10:12:08 +0100
Links: << >>  << T >>  << A >>
Jamie Sanderson a écrit :

> Greetings;
>
> I'm hoping this is a simple question to answer.
>
> When I wanted to put a ROM into an XC4000, I ran Logiblox. Within that tool,
> I was able to specify the data values, size, etc.. Now I want to do the same
> with Virtex. However, after installing a fresh copy of M2.1i, the Logiblox
> tool doesn't offer Virtex as a device family. I also tried CoreGen, but it
> doesn't offer ROM's for the Virtex family (the option is greyed out). From
> what I can tell, this tool will only create Block RAM components for Virtex.
> The ROM I need is relatively small, so I prefer not to use the larger Block
> RAM elements.
>
> Anyhow, I would really appreciate it if someone could tell me how to
> generate ROM for Virtex. I haven't ruled out the possibility that I
> installed M2.1i improperly. However, I did select the data files for the
> Virtex devices I'd be using, and I'm able to do complete Virtex designs.
>
> Thanks in advance,
> Jamie Sanderson

Hi !
Why do not use the "Ditributed Memory" in CoreGen?
you can choose the memory type (ROM, Single Port RAM or dual Port)
It supports Virtex family after installing the Service Pack 2 ....

Regards,
Samer

--
Samer EL HAJJ
DotCom S.A. http://www.dotcom.fr
S@merWeb    http://samer.web.com


Article: 19208
Subject: Re: data serializer/decoder FPGA solution
From: murray@pa.dec.com (Hal Murray)
Date: 6 Dec 1999 10:05:28 GMT
Links: << >>  << T >>  << A >>

> I have to transmit data using an optical link (100 MBd).
> How can I serialize / encode and deserialize / decode
> the data using an FPGA only (no analog solution, no CPU) ?
> Are there any  pure digital solutions ?
> The way RS232 transmission works is not practicable (would need at least
> 400 MHz sampling clock)

There are two parts to your problem.

One is clock recovery.

The other is that fiber links generally want a 50% duty
cycle so the automatic gain control on the receiver does
the right thing.

At 100 megabits, I'd try hard to use external chips and
let them do all the work.

-- 
These are my opinions, not necessarily my employers.
Article: 19209
Subject: Re: Problems with routing Virtex device
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Mon, 06 Dec 1999 05:34:06 -0800
Links: << >>  << T >>  << A >>
I think all that you need is download a service pack by www.xilinx.com.
I have had the same problem and it was solved this way,
Hope it helps,


* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 19210
Subject: Re: Problems with routing Virtex device
From: husby@fnal.gov (Don Husby)
Date: Mon, 06 Dec 1999 14:41:42 GMT
Links: << >>  << T >>  << A >>
"Johan Ditmar" <qtxjdit@al.etx.ericsson.se> wrote:
> Routing active routes does not take that long, maybe a few hours, but
> routing PWR/GND gives a lot of problems. It happens often, that PAR simply
> 'hangs' at that point, by getting into some kind of loop. I have been
> waiting many hours and it never finishes. I have to change my design then
> (by changing the placement constraints in my .ucf file) and sometimes that
> works. This is the case for both rather small and large designs.

Try breaking the PWR/GND nets into multiple nets.  This will prevent
the software from trying to route one massive net all over the chip.
Ususally, you only need a constant when driving an arithmetic function,
a memory address, or a tristate bus.  Try to use a unique PWR/GND net
for each of these instances, or figure out a way to do the function
without the constant.

In a schematic this is easy to do by having 1 power and/or ground
symbol per schematic page, driving a unique, non-global net name.
(I seem to remember that for Xilinx 4000 series, it was necessary
to define my own constant generator symbols because the software
tried to "optimize" the net by merging all VCC and GND together.
You can  create a constant generator by using an AND gate:
  ZERO=(ZERO * /ZERO)
and attaching a NOMERGE attribute to the net.)

There's probably a way to do it in VHDL.   


--
Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
Fermi National Accelerator Lab                          Phone: 630-840-3668
Batavia, IL 60510                                         Fax: 630-840-5406
Article: 19211
Subject: Re: Help with ROM in Xilinx Virtex
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Mon, 6 Dec 1999 11:32:03 -0500
Links: << >>  << T >>  << A >>
Actually, distributed memory wasn't supported in Virtex by Coregen until the
C_IP3 update. Paul Hardy of Xilinx was kind enough to point that out for me.

Cheers,
Jamie

Samer EL HAJJ <Samer@SPAM-FILTERDotCom.fr> wrote in message
news:384B7DE8.E2BFD7A8@DotCom.fr...
> Hi !
> Why do not use the "Ditributed Memory" in CoreGen?
> you can choose the memory type (ROM, Single Port RAM or dual Port)
> It supports Virtex family after installing the Service Pack 2 ....



Article: 19212
Subject: Re: Simple programmator for EP910
From: "News_food" <food@alik.carrier.kiev.ua>
Date: Mon, 6 Dec 1999 21:19:24 +0200
Links: << >>  << T >>  << A >>
> Simple programmator for EP910
> --
> IPM Group
> Andrew Buckin  ipm_grp@i.kiev.ua
>                           ipm_grp@iptelecom.net.ua
>
Dear Andrew.

I think you don't found the simple programmator for
EP910 especialy in this news group.
Ask that question to fido7.max2plus.ru (check if your news server have
that group).
But also you can call to ICS or company who sell other
programmators like TURBO in Kiev and  ask them.
We've bought LabTool48 by Logitech from Biacom in Kiev.
But it was expensive enough.


Bye.

Alexandr Kouchtch
IC BOOK
http://ic.doma.kiev.ua

Article: 19213
Subject: Re: hobbyist friendly pld?
From: Steve Dewey <steve@s-dewey123.demon.co.uk>
Date: Mon, 6 Dec 1999 19:39:19 +0000
Links: << >>  << T >>  << A >>
Try Altera's 6-month "Baseline" version of MaxplusII. Programmes a good
range of devices, including all Max7k series. The byteblaster &
byteblaster MV datasheets on their web site (www.altera.com) include the
circuit diagrams so you can make your own. It's not difficult as they
only consist of a single standard buffer chip. 

MaxplusII includes a timing simulator, and allows mixed schematic and
Altera Hardware Design Language (AHDL) design entry. AHDL is VERY easy
to use and comes with a good range of parameterised functions. Further
functions and tutorials are on www.freecore.com.

I speak as a satisfied Altera customer. I have no other connection with
them. 



In article <384AD812.858079EF@boeing.com>, Dan Rymarz
<m261981@boeing.com> writes
>Hello all,
>
>I am looking for a programmable logic technology I can use that
>also has a free+permanant (not 30 day trial) compiler available, that
>uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
>don't need a large gate count.  It seems like the  big devices need big
>software, and the small ones need special programming hardware.  Does
>anyone know where this holy grail of digital hobbyist devices exists -
>free s/w and simple h/w?  
>
>                                                      Thanks,
>                                                             Dan

-- 
Steve Dewey
Remove 123 for email.
Article: 19214
Subject: Re: backup fifo's
From: Eric Crabill <crabill@xilinx.com>
Date: Mon, 06 Dec 1999 11:46:18 -0800
Links: << >>  << T >>  << A >>
Hi Rick,What you said is basically how our implementation works.Once the
data is in the IOB flip flops, it isn't in the FIFO
anymore.  So, if the other bus agent disconnects without
taking the data, you have to "back up" the FIFO if you do
not flush it.

Rickman wrote:

> I am not sure that I agree with the architecture constraints you are
> describing. The issue is speed for sure. But I would certainly leave the
> IOB FFs in so that the speed path becomes, detecting that the data was
> accepted, incrementing the FIFO counter and clocking the data through
> the muxes into the output FFs in one clock cycle.

You are correct, if a system is running at 66 MHz, the
clock frequency will not change unless the bus is reset.
However, a compliant 66 MHz implementation must
be capable of running in a 33 MHz bus segment, which
means that the clock frequency can dynamically change
from 0 MHz to 33 MHz, precluding the use of a DLL
or PLL, unless it has some sort of bypass feature.

Rickman wrote:

> But can't this be selected ahead of time. At 33 MHz you have much more
> time to process the signals eliminating the need for the PLL clock. At
> 66 MHz the clock rate is fixed IIRC. Or do they allow a dithered clock
> at 66MHz?

Thanks,
Eric Crabill

Article: 19215
Subject: JTAG use after FPGA configuration on board
From: "Xanatos" <deletemeaoe_londonfog@hotmail.com>
Date: Mon, 06 Dec 1999 19:51:17 GMT
Links: << >>  << T >>  << A >>
Hello All,

Is it possible for a JTAG to work on a Xilinx XC4000 series FPGA after the
bitfile has been downloaded and configured. I need the JTAG to work on the
FPGA after configuration. I have a feeling it does, but I would like to
confirm this to be sure.

Thanks,
Xan

(if email, remove the delme part in my hotmail address)


Article: 19216
Subject: TIme Delay 1us-100ms
From: Moussa Ba <babs@eng.umd.edu>
Date: Mon, 06 Dec 1999 17:54:36 -0500
Links: << >>  << T >>  << A >>
Good Day,
What is the best to way to implement a Delay ranging from 1us to 100ms,
I am synthesizing some verilog code for use with a xilinx xs4005xl.
Could you please direct me to the best code construct for implementing
such a delay.  The clock in my design is 8MHz and I am using Xilinx
Foundation 1.5 software.


Thank you in advance

Article: 19217
Subject: Actel Programming Information Sought
From: IEC5 <IEC5@pacbell.net>
Date: Mon, 06 Dec 1999 16:10:56 -0800
Links: << >>  << T >>  << A >>
Hello,

I am looking for anyone with information on the Actel Activator One
FPGA programmer. To the best of my knowledge the kit included
a programming head, cable and PC ISA interface card plus documentation.
Specifically, if anyone can provide a part number for the PC ISA card,
it
would be greatly appreciated.

I have a need to program 2 (two) ancient Actel Parts based on the 1020
family.

I can be reached at:  iec5@pacbell.net

Thanks-in-advance

Dan

Article: 19218
Subject: Re: TIme Delay 1us-100ms
From: Ray Andraka <randraka@ids.net>
Date: Mon, 06 Dec 1999 20:55:15 -0500
Links: << >>  << T >>  << A >>
What is the sample rate and bit-width of the signal you want to delay?  Is
the delay to be a translation delay or an inertial delay?

Moussa Ba wrote:

> Good Day,
> What is the best to way to implement a Delay ranging from 1us to 100ms,
> I am synthesizing some verilog code for use with a xilinx xs4005xl.
> Could you please direct me to the best code construct for implementing
> such a delay.  The clock in my design is 8MHz and I am using Xilinx
> Foundation 1.5 software.
>
> Thank you in advance



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19219
Subject: Re: Actel Programming Information Sought
From: rk <stellare@NOSPAM.erols.com>
Date: Mon, 06 Dec 1999 21:55:43 -0500
Links: << >>  << T >>  << A >>
IEC5 wrote:

> Hello,
>
> I am looking for anyone with information on the Actel Activator One
> FPGA programmer. To the best of my knowledge the kit included
> a programming head, cable and PC ISA interface card plus documentation.
> Specifically, if anyone can provide a part number for the PC ISA card,
> it
> would be greatly appreciated.
>
> I have a need to program 2 (two) ancient Actel Parts based on the 1020
> family.
>
> I can be reached at:  iec5@pacbell.net
>
> Thanks-in-advance
>
> Dan

have you contacted our actelian friends?

here's some info, perhaps it will help.

the activator one is pretty old and i haven't used it in a while.   i
checked here at home, don't have the info, but i may have at my day job.  i
did have an activator 1 there but it hasn't been used in many years.  i'll
see what info i can dig out for you, although there's a good possibility
that the techs trashed it.  i do (day job and home business) all the
programming on the activator 2s and recently got their new programmer to
try and keep somewhat up to date at day job.

but anyways, i'm puzzled as to why you don't use the activator 2 for your
old 1020 series parts.  all of the programming information is still in the
software and runs on the activator 2 just fine.  in fact, we still
routinely program the oldest model of that series, the 2.0 um A1020
devices.  it works just fine.  i do note that the older devices are not in
the drop down menus in designer; the info is there, it is just hidden.
this is constantly a source of confusion and i know of no good reason why
the parts aren't on the menus.  in any event, if you load the old database
into the programming software (the file you load depends on what version it
was written in, it'll most likely be either a .def or a .afm) it'll call up
the correct programming algorithms.  the newest programming software may
require you to convert your file.  i'm not using that, yet, since r1-1999
did not support the actionprobe; i believe i'm running r3-1998.  i haven't
received r2-1999 so i don't know if that'll still accept .def files or if
the actionprobe "consideration" has been fixed.

hope this helps some,

------------------------------------------------------------------------
rk                                 The world of space holds vast promise
stellar engineering, ltd.          for the service of man, and it is a
stellare@erols.com.NOSPAM          world we have only begun to explore.
Hi-Rel Digital Systems Design      -- James E. Webb, 1968

Article: 19220
Subject: Re: Synplify vs. FPGA Compiler II (v3.3)
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Mon, 6 Dec 1999 19:33:14 -0800
Links: << >>  << T >>  << A >>

Greg Neff <gregneff@my-deja.com> wrote in message
news:82cihe$qbf$1@nnrp1.deja.com...
> In article <3848AE73.B4146CD1@yahoo.com>,
>   Rickman <spamgoeshere4@yahoo.com> wrote:
>
> (snip)
> BTW, I don't understand a one-hot state machine would be implemented
> that that uses N-1 flip-flops.  If you need a wide ANDxBx gate to
> decode the zero-hot state, then doesn't this break the definition of a
> one-hot state machine?  Personally, I prefer to use binary register-
> feedback state machines, with an output state decoder.  This keeps the
> number of possible illegal states down to something reasonable, and
> gives me an easy default reset state (0 when all register flip-flops
> clear).

Synopsys called it a zero-hot state machine.  It took HOURS to get this
through to Xilinx support and finally called a bug.  Synthesis quality of
results issues are really tough to find and even tougher to get fixed.

Bruce


Article: 19221
Subject: Re: backup fifo's
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Mon, 6 Dec 1999 19:38:15 -0800
Links: << >>  << T >>  << A >>
You're right.  Interesting....  I wonder how the Quicklogic core deals with
this?  I'll be feeding the core from 3 different fifo's.

Thanks for the info!

Bruce

Eric Crabill <crabill@xilinx.com> wrote in message
news:3846DCBA.E741D25E@xilinx.com...
> Hi Bruce,
>
> No, this problem still exists.  If you are bus mastering a write,
> there are several ways the transaction can end.  One of these
> is disconnect without data by the target.  In such a case, you
> (the bus master) will have popped data out of the FIFO, and
> it will be sitting in the I/O output flip flops.  At this point, if the
> target disconnects without taking it, your FIFO is out of
> sync.
>
> This behavior is described in section 3.3.3.2.1 "Target
> Termination Signaling Rules" of the PCI 2.2 specification.
>
> Also keep in mind that this is only an issue if your data source
> is not prefetchable.  If the data source is prefetchable and you
> are using the FIFO as a rate matching buffer, you can simply
> flush the buffer when you are done.
>
> Incidentally, backing up a FIFO built from RAM and address
> pointers (counters) is very easy; you just have to use an up/down
> counter for the read address pointer.
>
> Thanks,
> Eric Crabill
>
> Bruce Nepple wrote:
>
> > Assuming that I am bus mastering a write....Isn't the problem with the
fifo
> > being out of sync at the end of a transaction eliminated by the fact
that
> > the transaction can only be terminated by a stop (unless I end it),
which
> > will take the data just saved in the hidden register?  It's hard for me
to
> > see how (if I am writing) I can be out of sync after the transaction
> > completes.
> >
> > Bruce
>


Article: 19222
Subject: test, please ignore
From: rk <stellare@NOSPAM.erols.com>
Date: Mon, 06 Dec 1999 22:39:02 -0500
Links: << >>  << T >>  << A >>
test, please ignore.

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Article: 19223
Subject: PCI RESET with FPGA
From: "Bernard Esteban" <esteban@worldnet.fr>
Date: Tue, 7 Dec 1999 12:05:25 +0100
Links: << >>  << T >>  << A >>
Hi,

Has anybodies tried to make Reset on PC mother board with a FPGA on PCI
card, as well as to reboot the bios when the FPGA is ready. ???

What do you think???

--
Bernard Esteban
esteban@worldnet.fr
Engineer design
Ste MAF
BP112
82001 Montauban Cedex
Tel 33 (0) 563632770
Fax 33 (0) 563630785



Article: 19224
Subject: JTAG on PCI slot
From: "Bernard Esteban" <esteban@worldnet.fr>
Date: Tue, 7 Dec 1999 12:14:59 +0100
Links: << >>  << T >>  << A >>
Hi,

Where can I find information how works JTAG signals on PC mother board ??,
the goal, is to check if a PCI card with JTAG devices is well connected with
on PCI slot. The JTAG connector is on PCI card.

Thanks.

--
Bernard Esteban
esteban@worldnet.fr
Engineer design
Ste MAF
BP112
82001 Montauban Cedex
Tel 33 (0) 563632770
Fax 33 (0) 563630785





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