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Messages from 19300

Article: 19300
Subject: Re: AM2901 bit slice processor
From: edick@hotmail.com (Richard Erlacher)
Date: Sat, 11 Dec 1999 16:55:03 GMT
Links: << >>  << T >>  << A >>
On Tue, 07 Dec 1999 14:31:48 GMT, mikew@hmgcc.gov.uk (Mike) wrote:

>Hello All,
>	I am looking for an VHDL model for an AM2901 bit slice
>processor. (very old Math co-pro). There are numerous web sites with
>reference to this part because it is commonly used to teach the
>fundamentals of processor achitecture.
>	 However, there apear to be no complete VHDL implementations
>available. Any ideas where I can find it ?
>
>Regards
>
>Mike
====================================================
You'd best find a spec . . . since it's not a math coprocessor per se.
You wouldn't want to be disappointed would you?

Dick
Article: 19301
Subject: Re: hobbyist friendly pld?
From: edick@hotmail.com (Richard Erlacher)
Date: Sat, 11 Dec 1999 17:00:31 GMT
Links: << >>  << T >>  << A >>
The XILINX 9500 series is available via DigiKey.  That makes it about
as hobbyist-friendly as it gets.  The Software is freely available via
the WEB, and the prices are decent.  Most other vendors want to sell
you software and then you find out their parts are a pain to buy.
Having it available at DigiKey is really handy!

Dick

On Sun, 05 Dec 1999 20:17:36 -0500, Dave Vanden Bout <devb@xess.com>
wrote:

>This is a multi-part message in MIME format.
>--------------F4826BC6720345AF47F6D1D3
>Content-Type: text/plain; charset=us-ascii
>Content-Transfer-Encoding: 7bit
>
>You can also get the free webpack software from the XILINX web site.  It supports VHDL, Verilog, and ABEL for all sizes of the XC9500 devices.  Take a look at http://www.xess.com/webpack.pdf for a tutorial on how to get, install, and use the webpack tools.
>
>
>
>Pascal Dornier wrote:
>
>> Xilinx XC95xxx should work for you. The 3.3V version (XL) is significantly
>> cheaper than the 5V version.
>>
>> --------------------------------------------------------------------
>> Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
>> Your Spec      + PC Engines            = Custom Embedded PC Hardware
>> --------------------------------------------------------------------
>>
>> Dan Rymarz wrote in message <384AD812.858079EF@boeing.com>...
>> >Hello all,
>> >
>> >I am looking for a programmable logic technology I can use that
>> >also has a free+permanant (not 30 day trial) compiler available, that
>> >uses JTAG or similar few-wire (4 for jtag etc.) programming mode.  I
>> >don't need a large gate count.  It seems like the  big devices need big
>> >software, and the small ones need special programming hardware.  Does
>> >anyone know where this holy grail of digital hobbyist devices exists -
>> >free s/w and simple h/w?
>> >
>> >                                                      Thanks,
>> >                                                             Dan
>
>--------------F4826BC6720345AF47F6D1D3
>Content-Type: text/x-vcard; charset=us-ascii;
> name="devb.vcf"
>Content-Transfer-Encoding: 7bit
>Content-Description: Card for Dave Vanden Bout
>Content-Disposition: attachment;
> filename="devb.vcf"
>
>begin:vcard 
>n:Vanden Bout;David
>tel;fax:(919) 387-1302
>tel;work:(919) 387-0076
>x-mozilla-html:FALSE
>url:http://www.xess.com
>org:XESS Corp.
>adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
>version:2.1
>email;internet:devb@xess.com
>title:FPGA Product Manager
>x-mozilla-cpt:;28560
>fn:Dave Vanden Bout
>end:vcard
>
>--------------F4826BC6720345AF47F6D1D3--
>

Article: 19302
Subject: Re: Simple programmator for EP910
From: edick@hotmail.com (Richard Erlacher)
Date: Sat, 11 Dec 1999 17:04:09 GMT
Links: << >>  << T >>  << A >>
it might work better to use a more modern device, perhaps with more
macroscells than your application demands, but using an in-circuit
programming tool which you could build yourself.  Look at the
in-circuit programmer tool for the  7000-series of parts and
contemplate whether this won't save you money in the long run.

Dick


On Mon,  6 Dec 1999 21:19:24 +0200, "News_food"
<food@alik.carrier.kiev.ua> wrote:

>> Simple programmator for EP910
>> --
>> IPM Group
>> Andrew Buckin  ipm_grp@i.kiev.ua
>>                           ipm_grp@iptelecom.net.ua
>>
>Dear Andrew.
>
>I think you don't found the simple programmator for
>EP910 especialy in this news group.
>Ask that question to fido7.max2plus.ru (check if your news server have
>that group).
>But also you can call to ICS or company who sell other
>programmators like TURBO in Kiev and  ask them.
>We've bought LabTool48 by Logitech from Biacom in Kiev.
>But it was expensive enough.
>
>
>Bye.
>
>Alexandr Kouchtch
>IC BOOK
>http://ic.doma.kiev.ua
>

Article: 19303
Subject: Re: Altera APEX lpm modules in Synplify
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 11 Dec 1999 18:23:53 +0100
Links: << >>  << T >>  << A >>
"Xanatos" <deletemeaoe_londonfog@hotmail.com> writes:

> Hi All,
> 
> Here is the problem : I was using Quartus for synthesis and P+R. However, as
> my design progressed, there were some verilog statements that Quartus will
> not handle.
> So, I started to use Synplify for synthesis, and import the vqm file into
> Quartus and let it fly.
> However, I have since started to use dual port and single port rams. I used
> the MegaWizard in Quartus to generate the ram files, and pushed it through
> synthesis using Quartus, and it was fine (except for the verilog statements
> it was choking on).
>  However, once I tried the same design files in Synplify, it whined that it
> could not find the module lpm_ram_dp and lpm_ram_dq. I assume there must be
> some file (like xc4000.v for 4000 series Xilinx parts) that I have to
> include with the design. Is this true?

Not sure if you need to do that? There's some hints in the Synplify
helpfile, but they are hard to find. At least for me. Some LPMs are
ready for use, and some needs some special consideration. I don't have
Synplify at home, so i can't check i out. It's in the helpfile, but
you have to scroll all the way down through that page (Vendor
specific, Altera).

Let me know how it works out.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 19304
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: jan coombs <jcoombs@mcmail.com>
Date: Sat, 11 Dec 1999 17:35:06 +0000
Links: << >>  << T >>  << A >>
Jamie Sanderson wrote:
 . . .
> A more efficient,
> but slightly more complex, way would be to run a single dual-port memory at
> twice the required speed. 

I'm also facing this problem, and require maximum clock
speed. It seems from the Xilinx databook that 2-3 read
accesses can be obtained in the minimum write port cycle
time, so Jamie's solution would seem ideal where only one
write port is required.

Jan Coombs


Article: 19305
Subject: Announcement and First Call for Papers - 2000 MAPLD Conference
From: rk <stellare@NOSPAM.erols.com>
Date: Sat, 11 Dec 1999 23:52:09 -0500
Links: << >>  << T >>  << A >>
             Announcement and First Call for Papers

                      2000 MAPLD Conference

                  Kossiakoff Conference Center
     The Johns Hopkins University - Applied Physics Laboratory
                    11100 Johns Hopkins Road
                   Laurel, Maryland 20723-6099

                      September 26-28, 2000

   The 3rd annual Military and Aerospace Applications of
   Programmable Devices and Technologies International
Conference
   will address devices, technologies, usage, reliability, fault

   tolerance, radiation susceptibility, and applications of
   programmable devices and adaptive computing systems in
military
   and aerospace systems. The program will consist of oral and
   poster technical presentations and industrial exhibits.  The
   majority of the conference is open to US and foreign
   participation and is unclassified.  There will be one
   classified session at the secret level, for U.S. citizens
only.
   For conference information, please see the Programmable
   Technologies Web Site (http://rk.gsfc.nasa.gov) or the
   conference www home page at:

http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html

   Abstracts are being solicited in all aspects of the use of
   programmable elements, devices, and systems for military and
   aerospace applications. These include: PALs, FPGAs, PROMs,
   Programmable Substrates, FPIC, Programmable Analog Circuits,
   adaptive computing systems and related technologies.

   Invited speakers for the conference include:

        Keynote Address:
        Henry Spencer - SP Systems
        "Faster, Better, but Most Important, Much Much Cheaper"

        Eldon Hall, MIT Instrumentation Lab
        "The Apollo Guidance Computer - A Designer's View"

        Lloyd Massengill, Vanderbilt University
        "Single Event Modeling on Emerging Commercial
Technologies"

        AIAA Invited Talk:
        James Kinnison, Johns Hopkins University/Applied Physics
Lab
        "System Level Radiation Tolerance"


http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/InvitedSpeakers00.html

        contains abstracts for the invited speakers.  Several
invited
        talks will be added as some details are being finalized.

   Conference proceedings will be published and will consist of
all
   presentations (oral and poster) as well as written papers.
Papers
   may be submitted in one of two categories: "Select" or
"Contributed."
   Select papers will be subject to a peer-review and will be
published
   in a special edition of the AIAA Journal of Spacecraft and
Rockets as
   well as the conference proceedings.  Contributed papers will
be
   subject to a less stringent review.

   We are again including tours this year.  Guided tours will be

   given at the NASA Goddard Space Flight Center and at the
   National Security Agency's National Cryptologic Museum.  We
   are finalizing plans for tours of Johns Hopkins University's
   Applied Physics Laboratory.  For additional tour information,

   please see:
     http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Tours.htm

   Conference topics include (but are not limited to) the
following:

     System on a Chip
     Advanced Devices, Technologies, and Software and Their
          Impact on Critical System Reliability
     Programmable Technologies and State-of-the-Art Devices and
          Programmable Elements
     Low-Power Design Techniques
     High-Speed Design Techniques
     Arithmetic and Signal Processing
     Adaptive Computing Systems
     Evolvable Hardware
     Radiation Effects, Device Reliability and Element
          Characteristics
     Device Architecture, Performance, and Capabilities
     Applications and Novel Techniques for Military and
          Spaceflight Circuits.
     Use of COTS Devices in the Military and Spaceflight
Environment
     Testing and Analysis Techniques
     Software Tools for Design/Analysis - HDLs, Synthesis,
Design
          Entry Systems
     Translation from High Level Languages
     Intellectual Property
     Advanced Packaging including Known-Good-Die, MCMs, and
          Chip-scale packaging.
     Military Applications
     Aeronautics and Space Applications
     Encryption Systems
     Experience and "Lessons Learned" from Mission Experience

   The conference is sponsored by:

     NASA Goddard Space Flight Center
     JHU/Applied Physics Laboratory
     National Security Agency
     NASA Radiation Effects Program
     Military & Aerospace Programmable Logic Users Group
     American Institute of Aeronautics and Astronautics


   For more information see http://rk.gsfc.nasa.gov or contact:

     Richard Katz - Conference Chair
     NASA Goddard Space Flight Center
     rich.katz@gsfc.nasa.gov
     Tel: (301) 286-9705

     Alan W. Hunsberger - Conference Co-Chair
     National Security Agency
     awhunsb@afterlife.ncsc.mil
     Tel: (301) 688-0245

     Ann Darrin - Conference Co-Chair
     Johns Hopkins University
     Applied Physics Laboratory
     ann.darrin@jhuapl.edu
     Tel: (240) 228-4952

     Tanya Vladimirova - Conference Co-Chair
     University of Surrey
     T.Vladimirova@ee.surrey.ac.uk
     +44(0)1483 879137


   Abstracts should be approximately 2 pages long and are due
   June 9, 2000. Please send abstracts to
   maplug@pop700.gsfc.nasa.gov.   If your abstract is in an
   attached file, please name the file in the following format:
   LastName_A.ext  - where last name is the name of the first
   author - e.g., Katz_A.txt.  Please include first author
   information (name, affiliation, phone number, and email
   address) as well as whether an open or classified
presentation
   is desired.   Additionally, please specify whether you will
be
   submitting your paper for a peer-reviewed publication or a
   symposium publication.  All abstracts should be unclassified
   when sent over email.  If you can not submit an unclassified
   abstract, please contact Al Hunsberger.

   Industrial exhibit reservations should be sent to
   maplug@pop700.gsfc.nasa.gov and should include company name
   and contact information (phone and email). Please see

http://rk.gsfc.nasa.gov:80/richcontent/MAPLDCon00/Industrial_Exhibits.htm

   for additional information.

   Technical Committee
   ===================

   Marty Fraeman            Johns Hopkins University
   Ken LaBel                NASA Goddard Space Flight Center
   John McHenry             National Security Agency
   Hans Tiggeler            University of Surrey
   Ray Andraka              The Andraka Group
   Frank R. Stott           Jet Propulsion Laboratory
   Tanya Vladimirova        University of Surrey
   Robert Reed              NASA Goddard Space Flight Center
   Marco Figueiredo
   Lew Cohn                 Defense Threat Reduction Agency
   Ralph Kohler             Air Force Research Laboratory
   Creigh Gordon            Air Force Research Laboratory/VSSE
   Ben Cohen                Hughes Aircraft/Raytheon Systems
Company
   Neil Bergmann            Queensland University of Technology
   Michael Regula           Dornier Satellitensysteme GmbH
   Brad Hutchings           Brigham Young University
   Jing Yuan                Jet Propulsion Laboratory
   David Hepner             US Army Research Laboratory
   Thomas D. Milnes         Johns Hopkins University


Article: 19306
Subject: Re: Lattice ispLSI Security
From: "Luigi Funes" <fuzzy8888@hotmail.com>
Date: Sun, 12 Dec 1999 15:35:56 +0100
Links: << >>  << T >>  << A >>
Jeff,
as Lattice user, I can confirm you that the security bit is a *physical*
security bit. The Lattice isp programming algorithm is fully documented
and you can verify it.
But I can't know how much secure it is. Back doors? I don't think... too
much dangerous and unnecessary for a semiconductor manufacturer.
Generally, if a device emploies no special antitampering measures,
perhaps the best way to reverse engineering it is open the IC package,
locate the security eeprom cell and UV erasing only it, so the device will
appear unprotected and one can read it immediately.
But could be other unexpected ways... some protected devices unlock
their security if submitted to unusual voltages or power-up/down
sequences... the Microchip PIC16C84 is an example of this bad
security design.
If you need the best security in a programmable device, you don't have to
use erasable eprom or eeprom technologies, but antifuse or
laser-programming technologies available from not many manufacturers.

Luigi

Jeff Smith ha scritto nel messaggio <384f2b96.261147832@news.pompano.net>...
>I am just starting to look at incorporating the Lattice reprogrammable
>parts like the ispLSI1016E or maybe some of the bigger parts, but I am
>wondering just how secure they are, once the fuse is blown. Since even
>with a blown security fuse, they can be erased and reused....is it
>really all that secure?  The programs they provide (e.g. the Daisy
>Chain Download program) can't read a secured part, but is this a case
>of the part being impossible to read, physically, or is someone going
>to be able to read it with relative ease, given proper knowledge and
>tools?  Would I be ahead using a different type of part for better
>security?
>
>TIA,
>
>Jeff Smith




Article: 19307
Subject: Re: Lattice ispLSI Security
From: Ray Andraka <randraka@ids.net>
Date: Sun, 12 Dec 1999 10:59:08 -0500
Links: << >>  << T >>  << A >>
For the ultimate in security, you can use a battery backed an SRAM based FPGA
that is loaded during manufacture.  There is no copy of the bitstream anywhere
in the product other than in the FPGA and if you remove power it is gone without
a trace.  It works well for things like military gear that can be reloaded
periodically in a secure environment.

Luigi Funes wrote:

> Jeff,
> as Lattice user, I can confirm you that the security bit is a *physical*
> security bit. The Lattice isp programming algorithm is fully documented
> and you can verify it.
> But I can't know how much secure it is. Back doors? I don't think... too
> much dangerous and unnecessary for a semiconductor manufacturer.
> Generally, if a device emploies no special antitampering measures,
> perhaps the best way to reverse engineering it is open the IC package,
> locate the security eeprom cell and UV erasing only it, so the device will
> appear unprotected and one can read it immediately.
> But could be other unexpected ways... some protected devices unlock
> their security if submitted to unusual voltages or power-up/down
> sequences... the Microchip PIC16C84 is an example of this bad
> security design.
> If you need the best security in a programmable device, you don't have to
> use erasable eprom or eeprom technologies, but antifuse or
> laser-programming technologies available from not many manufacturers.
>
> Luigi
>
> Jeff Smith ha scritto nel messaggio <384f2b96.261147832@news.pompano.net>...
> >I am just starting to look at incorporating the Lattice reprogrammable
> >parts like the ispLSI1016E or maybe some of the bigger parts, but I am
> >wondering just how secure they are, once the fuse is blown. Since even
> >with a blown security fuse, they can be erased and reused....is it
> >really all that secure?  The programs they provide (e.g. the Daisy
> >Chain Download program) can't read a secured part, but is this a case
> >of the part being impossible to read, physically, or is someone going
> >to be able to read it with relative ease, given proper knowledge and
> >tools?  Would I be ahead using a different type of part for better
> >security?
> >
> >TIA,
> >
> >Jeff Smith



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19308
Subject: Re: hobbyist friendly pld?
From: Grant Sargent <g.sargent@auckland.ac.nz>
Date: Mon, 13 Dec 1999 11:47:48 +1300
Links: << >>  << T >>  << A >>
Dan Rymarz wrote:
> I am looking for a programmable logic technology I can use that
> also has a free+permanant (not 30 day trial) compiler available, that
> uses JTAG or similar few-wire (4 for jtag etc.) programming mode.

I've just finished a board using a Altera Max 7000S chip, programmed
using MAXPLUS2 baseline and JTAG/Byteblaster.

It's very fast to program, the byteblaster works like a charm. MAXPLUS2
is a nice bit of software, and their helpfiles are excellent. I haven't
tried much in the way of AHDL/VHDL (Maxplus2 only does AHDL unless you
pay for it.), but can muddle through the gist of the AHDL files it
generates from the graphical side of things.

I'd recommend it. I did see that a previous poster mentioned it was a
6-month time-limited version, but the version I've got is unlimited
(well, I'm fairly sure it's unlimited... I didn't see anything that
mentioned a time-limit.)

Cheers,
Grant
Article: 19309
Subject: R: Command line for FPGA Express
From: Mark Harvey <mark.harvey@farsystems.it>
Date: Mon, 13 Dec 1999 08:18:40 +0100
Links: << >>  << T >>  << A >>
FPGA Express is installed as a seperate program, I bypass the Foundation
Project manager GUI by writing my code with the Prism editor, then
synthesizing using the FPGA Express GUI, then P & R with the Xilinx Design
Manager - all launched as seperate programs.

Mark Harvey.
=20

> -----Messaggio originale-----
> Da:=09Mark van de Belt [SMTP:mark@nospam.bs]
> Inviato:=09venerd=EC 3 dicembre 1999 12.25
> A:=09comp.arch.fpga@list.deja.com
> Oggetto:=09Re: Command line for FPGA Express
>=20
>  Message from the Deja.com forum:=20
>  comp.arch.fpga
>  Your subscription is set to individual email delivery
> >=20
> Hello,
>=20
> I looked into this fe shell, and it is possible to create a batch file fo=
r
> synthesis, but only if there is a FPGA express project. The foundation
> software does not make this project.
>=20
> The intention of this all is to use an other VHDL editor (Codewright) and
> to
> synthesise the project from there (bypassing the foundation GUI and
> version/
> revision philosophy). The design implementation is no problem, this is a
> long series of batch commands (check the fe.log and you can see all the
> batch commands for the implementation). The only thing is the syntax chec=
k
> and the synthesis and optimalisation.
>=20
> I think a lot of people can benefit from this.
>=20
> Mark van de Belt
>=20
>=20
>=20
>=20
>=20
>  _____________________________________________________________
>  Deja.com: Before you buy.
>  http://www.deja.com/
>  * To modify or remove your subscription, go to
>  http://www.deja.com/edit_sub.xp?group=3Dcomp.arch.fpga
>  * Read this thread at
>  http://www.deja.com/thread/%3C944220170.454831%40big.hacom.nl%3E


 Sent via Deja.com http://www.deja.com/
 Before you buy.
Article: 19310
Subject: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
From: Peter Heidrich <peter.heidrich@erlf.siemens.de>
Date: Mon, 13 Dec 1999 08:30:44 +0100
Links: << >>  << T >>  << A >>
Hello out there,

I do have to realise a Ethernet-to-Ethernet (10- and/or 100-Base)
switch with MII to the PHYsical layer.

Instead of programming a FPGA I would rather use a commercially
available, ready to go chip.

Does someone know if such a device exists and where to find it?

Thanks in advance,
Peter.
--
Peter Heidrich
Siemens AG, A&D MC
EMail: peter.heidrich@erlf.siemens.de
Article: 19311
Subject: Re: Virtex boards
From: "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk>
Date: Mon, 13 Dec 1999 14:31:48 -0000
Links: << >>  << T >>  << A >>
We have 3 VW300 boards from VCC which, while we have only had limited use of
so far are great

using the boards for partial reconfiguration with Jbits, and a some other
stuff

Only gripe is that you need either 3 different power supplies (5, 3.3, 2.5V)
to power up the board or build your own power supply (as we have done)

Also need relevant download cable (Parallel, Xchecker Multilinx etc)

We have just ordered a PCI based XCV1000 board form embedded solutions -
have heard this is pretty good but no hands on experience yet

Daryl


<smithers12@my-deja.com> wrote in message
news:82r6un$1t1$1@nnrp1.deja.com...
> Hello,
>
> I was wondering if anyone has had any experience with the various
> Virtex-based prototyping boards out on the market (e.g., Avnet, VCC,
> etc.).  Any recommendations would be appreciated.  Thanks.
>
> Sincerely,
>
> Hugh
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 19312
Subject: Re: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
From: uj101@my-deja.com
Date: Mon, 13 Dec 1999 15:11:25 GMT
Links: << >>  << T >>  << A >>
www.icube.com
For performance eval of the same, u can see a report at
www.svnl.com - I-CUBE second generation switching chip set
comp. perf. evaluation



In article <3854A0A4.CAB6B420@erlf.siemens.de>,
  Peter Heidrich <peter.heidrich@erlf.siemens.de> wrote:
> Hello out there,
>
> I do have to realise a Ethernet-to-Ethernet (10- and/or 100-Base)
> switch with MII to the PHYsical layer.
>
> Instead of programming a FPGA I would rather use a commercially
> available, ready to go chip.
>
> Does someone know if such a device exists and where to find it?
>
> Thanks in advance,
> Peter.
> --
> Peter Heidrich
> Siemens AG, A&D MC
> EMail: peter.heidrich@erlf.siemens.de
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19313
Subject: power on reset with FLEX 10K
From: Thomas Rathgen <trathgen@gmx.de>
Date: Mon, 13 Dec 1999 16:52:15 +0100
Links: << >>  << T >>  << A >>
Hi,

Here's my problem: I need to run a special sequence on power up, 
meaning after configuration on a FLEX 10K. As I remember, every 
register should power up high but I could'n use this feature yet.

Does someone know of a simple way of providing a reset signal for 
e.g. 10 clocks after configuration ?

Any help would be much apprechiated

rgds 
	Tom
Article: 19314
Subject: Virtex hard macro
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Mon, 13 Dec 1999 18:09:39 +0100
Links: << >>  << T >>  << A >>
Hi
I tried to create a hard macro for Virtex with the FPGA editor.
I loaded the design and chose "Save as macro". It crashed, saying "too
many routes in macro"
I didn't find anything in the Xilinx Answer DataBase.
If someone has an idea to help me create this macro...
Thanks in advance
-- 
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 19315
Subject: Re: Lattice ispLSI Security
From: Armin Mueller <armin.mueller@stud.uni-karlsruhe.de>
Date: Mon, 13 Dec 1999 18:36:01 +0100
Links: << >>  << T >>  << A >>
Jeff Smith wrote:

> [...]
> wondering just how secure they are, once the fuse is blown. Since even
> with a blown security fuse, they can be erased and reused....is it
> really all that secure?

I remember there was an issue with Lattice GAL parts when erasing -
the security fuse was erased first. You just had to know the right
timing...

Armin
Article: 19316
Subject: Re: power on reset with FLEX 10K
From: "aitan ameti" <aameti@erols.com>
Date: Mon, 13 Dec 1999 16:16:59 -0500
Links: << >>  << T >>  << A >>
I use the CONF_DONE signal OR'ed with a manual reset switch as an input to a
reset chip ( like MAX704 ) and connect it to my own reset input ( used one
of the global inputs)

--
--------------------------------------------------------
Aitan Ameti
E-Mail aameti@multispectral.com
Phone 301-590-3978
Fax 301-590-1429
Thomas Rathgen <trathgen@gmx.de> wrote in message
news:3855162F.3038B823@gmx.de...
> Hi,
>
> Here's my problem: I need to run a special sequence on power up,
> meaning after configuration on a FLEX 10K. As I remember, every
> register should power up high but I could'n use this feature yet.
>
> Does someone know of a simple way of providing a reset signal for
> e.g. 10 clocks after configuration ?
>
> Any help would be much apprechiated
>
> rgds
> Tom


Article: 19317
Subject: Velab and VSS simulation
From: Walter Soto Encinas Jr <soto@icmc.sc.usp.br>
Date: Mon, 13 Dec 1999 20:04:55 -0200
Links: << >>  << T >>  << A >>
Hello

	I am doing some designs with XC6216 using structural VHDL. I'd wish to do
the simulation with Synopsys VSS tools of the post-routed design. So, I need
backannotate in VSS the SDF file generated by XACT6000, the place/route
tool. 

	Detailing the design flow:

1) My VHDL code is written in structural style, and with lots of placement
attributes spread in the code. This placement attributes help the
place/route tool (XACT6000) do the best placement. 

2) This attributes are not used by dc when it generates the EDIF output. So
I use a program called VELAB (Vhdl Elaborator) to do this job. Velab
recognizes a subset of VHDL statemets (just structural ones), and, very
important, recognizes attributes too, putting them in the EDIF file. 

3) The EDIF (generated by Velab) is read by place/route tool (XACT6000) 
without problems. XACT does the placement/routing (using the attributes) and
also creates SDF file with accurate timing parameters.

4) The SDF file is read by VSS to do the gate level simulation, with errors.

	The SDF file has the following naming scheme:

(CELL
        (CELLTYPE "AND2B1")
        (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
        (DELAY
                (ABSOLUTE
                        (PORT I0 (9.476:9.476:9.476) (8.143:8.143:8.143))
                        (IOPATH I0 O (0:0:0) (0:0:0))
                        (PORT I1 (3.040:3.040:3.040) (3.575:3.575:3.575))
                        (IOPATH I1 O (0:0:0) (0:0:0))
        ...

        Looking into the design tree, using vhdlsim, I found the path to
that cell shown above. 

# pwd
/TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX
# ls
TIMINGCHECKSON  MSGON           TIPD_I1         I1
VITALBEHAVIOR
INSTANCEPATH    TPD_I0_O        TIPD_I0         I0              I1_IPD
XON             TPD_I1_O        O               WIREDELAY       I0_IPD

	The error message in the backannotation is:

# vhdlsim -fi_all -sdf_typ -sdf_top /tb_addr/c_addr -sdf addr.sdf
CFG_TB_ADDR

**Error: vhdlsim,259: 
    (SDF File: addr.sdf Line: 20) instance
    /TB_ADDR/C_ADDR/COUNT_COL/COUNT_0_INI_1_C_MUX not found.

	Is there any way to solve this name mismatch (COUNT_0_INI_1_C_MUX vs
COUNT(0)/INI/C_MUX) in VSS? I know (thanks, folks) DC has naming rules to
change the entity names and commands to remove the hierarchy. I am afraid
these rules won't help me, because the EDIF are generated by VELAB, not by
DC. I need naming rules that can be applied inside VSS, when VSS reads (or
analyze) the VHDL code... Or any other solution!

	Any help would be very appreciated!

	[]s

-- 
|                                       Walter Soto Encinas Jr          |
|                                            PhD  Student               |
|                                             IFSC / USP                |
|                                               Brazil                  |
Article: 19318
Subject: VirtexE availability?
From: jeffrey j cook <jjcook@staff2.cso.uiuc.edu>
Date: 13 Dec 1999 22:15:59 GMT
Links: << >>  << T >>  << A >>
Does anyone know when the VirtexE series will be available?   I haven't
been able to find any dates on their website.

If they are already available, who has them (avnet doesn't)?

Thanks.
-- 
Jeffrey J. Cook
University of Illinois Computer Engineering Student
jjcook@uiuc.edu

"Sometimes the easiest way to get something done is to be a little naïve
about it -- and just ship it."
Bill Joy, Sun Microsystems  - Jini Engineer
Article: 19319
Subject: State machine ok with binary encoding but unstable with one hot encoding
From: "Marc Battyani" <Marc_Battyani@csi.com>
Date: Tue, 14 Dec 1999 10:48:35 +0100
Links: << >>  << T >>  << A >>
I don't understand why the following state machine is ok when I use binary
state encoding (with safest mode) but oscillate when I use one hot encoding
(with safest mode also).

type State is (Waiting, StartDataRead, InDataRead);
signal S : State;
begin
SM : process (Clock, Reset)
begin
    if (Reset = '1') then
        State <= Waiting;
    elsif rising_edge(Clock) then
        case State is
            when Waiting =>
                if DataStb = '0' then
                    if Write = '1' then
                        State <= StartDataRead;
                    end if;
                end if;
            when StartDataRead =>
                  State <= EppInDataRead;
            when InDataRead =>
                if DataStb = '1' then
                    State <= Waiting;
                end if;
           when others =>
                State <= EppWaiting;
       end case;
    end if;
end process SM;

The compiler is VHDL express, for a Spartan xcs40.
Any idea ?

Thanks
Marc Battyani


Article: 19320
Subject: Re: State machine ok with binary encoding but unstable with one hot encoding
From: "David Murray" <dmurray@iol.ie>
Date: Tue, 14 Dec 1999 12:05:18 GMT
Links: << >>  << T >>  << A >>
Marc ,
I'm not sure if you included all your State machine definitions in your
description below e.g. (EppInDataRead, EppWaiting) .

Anyway, some things to be careful of when you synthesis your One hot encoded
FSM's. During reset, your state register should look something like "00001"
and some FPGAs (although rarer these days) can only have a single global set
or reset which means that a '1' hot encoded state machine cannot be
synthesized to these type of devices.

                             - David Murray


Marc Battyani wrote in message
<062E9EEFDD659520.D67674846BD251B1.A017E921C8876561@lp.airnews.net>...
>I don't understand why the following state machine is ok when I use binary
>state encoding (with safest mode) but oscillate when I use one hot encoding
>(with safest mode also).
>
>type State is (Waiting, StartDataRead, InDataRead);
>signal S : State;
>begin
>SM : process (Clock, Reset)
>begin
>    if (Reset = '1') then
>        State <= Waiting;
>    elsif rising_edge(Clock) then
>        case State is
>            when Waiting =>
>                if DataStb = '0' then
>                    if Write = '1' then
>                        State <= StartDataRead;
>                    end if;
>                end if;
>            when StartDataRead =>
>                  State <= EppInDataRead;
>            when InDataRead =>
>                if DataStb = '1' then
>                    State <= Waiting;
>                end if;
>           when others =>
>                State <= EppWaiting;
>       end case;
>    end if;
>end process SM;
>
>The compiler is VHDL express, for a Spartan xcs40.
>Any idea ?
>
>Thanks
>Marc Battyani
>
>


Article: 19321
Subject: Re: hobbyist friendly pld?
From: Leon Heller <leon_heller@hotmail.com>
Date: Tue, 14 Dec 1999 12:06:02 GMT
Links: << >>  << T >>  << A >>
In article <384fc07d.193780480@news.ncl.ac.uk>,
  news@river-view.freeserve.co.uk wrote:
> On Mon, 06 Dec 1999 08:33:58 GMT, Leon Heller
> <leon_heller@hotmail.com> wrote:
>
> >Get the Xilinx starter kit. It comes with a JTAG programmer, a little
> >CPLD evaluation board, and software that supports the CPLDs and the
> >Spartan series of FPGAs, as well as the older devices. It's about
$100.
>
> Is that the same one as:
> http://www.microcall.memec.com/xilinx/promo.htm - £60 in the UK?
>
> I'm considering it as an FPGA starter kit- anyone had any experience
> with it?  Any time or feature limitations I should be aware of?  I
> know it doesn't have VHDL./Verilog.
>
> If that isn't it, do you have a UK source for the Xilinx one you
> mentioned?

Yes, that's the one. I got mine from MicroCall.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


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Before you buy.
Article: 19322
Subject: CORE-2000 - Reconfigurable Computing Workshop
From: Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk>
Date: Tue, 14 Dec 1999 12:06:17 +0000
Links: << >>  << T >>  << A >>

*******************************************************************
          CORE-2000 - Reconfigurable Computing Workshop
     Fundação Euripides de Marilia - Faculdade de Informatica
           August 10-11 2000   Marília, S.P., Brazil

            URL:  http://www.fim.fundanet.br/core2000
            Deadline Submission:     24/03/2000
*******************************************************************
                            The First Call

Objectives
-----------
REconfigurable COmputing  (CORE) is a research  area of growing
interest in Brazil as well as other countries. Still in its development
stage, it presents many challenges and open problems, which
motivate research groups around the world. CORE-2000 will be the
second event on the subject  held in Brazil. Its is intended to be a
forum to present ideas, results, and on-going research from both,
academia and industrial sectors. Another major  objective of the
workshop is to enable the establishment  of  collaborative projects
among  different groups.

Topics of Interest
--------------------
Authors are invited to submit papers in all areas of  reconfigurable
computing. The main topics of interest include, but are not limited
to:
   - Industrial applications and experiences
   - General applications employing reconfigurable computing
   - Total and partially reconfigurable designs
   - Development tools for reconfigurable computing
   - Reconfigurable systems codesign (software and hardware)
   - Dynamically  reconfigurably systems
   - Interaction among devices, architectures, and reconfigurable
technologies
   - Performance analysis
   - Benchmarking and profiling
   - Fault tolerance, test methodologies, and reliability
   - Educational experiences and opportunities
   - Future trends


Program Committee
-------------------
Andre DeHon, CALTECH, USA
Carlos A.P.S. Martins, PUC-MG, BR
Claudionor J.N. Coelho, UFMG, BR
Edna N.S. Barros, UFPE, BR.
Eduardo Marques, USP, BR
Eduardo Sanchez, EPFL, CH
Edward D. Moreno, FEM, BR
Fernando G. Moraes, PUC-RS, BR
Ildeberto G. Bugatti, FEM, BR
Jorge Luiz e Silva, FEM, BR
José H. Saito, UFSCar, BR
Juan M. Moreno, UPC, ES
Julio S. Salek, UFRJ, BR
Ricardo Jacobi, UNB, BR
Ricardo Reis, UFRGS, BR
Sergio T. Kofuji, USP, BR
S.Q. Zheng, UT, USA
Scott A Hauck, UW, USA


Submission Guidelines
----------------------
Authors should submit an electronic version of a manuscript to
core2000@fundanet.br, either in english or portuguese.  Submissions
should not exceed 10 pages of  A4 size paper, including single
spaced text in double-columns, figures, tables, and references. The
name of the authors, with affiliation and e-mail address, should
appear on the top of the first page.
File formats allowed are PostScript, PDF, and  MS-Word. When
appropriate, authors should make sure that the submission could be
viewed on ghostscript or Acrobat Reader.
Alternatively, 3 copies of hard copy submissions can be sent to:

    CORE-2000 Fundação Euripides de Marilia
    Av. Hygino Muzzi Filho, 529
    17525-901,  Marília,  SP
     Brazil

All manuscripts will be reviewed by experts in the respective field.
Accepted papers should be presented at the workshop in order to be
published on the workshop proceedings.


Important Dates
-----------------
Paper submission:                                     24/03/2000
Notification of acceptance/rejection:          19/05/2000
Camera ready  version:                             09/06/2000
Workshop:                                         10-11 August 2000


Organisation and Support
-------------------------
Fundação Euripides de Marilia
Local Companies
XILINX (Insight Electronics)
IEEE South Brazil
ALTERA                                               pending
SBC (Brazilian Computing Society)         pending


Local
-------
Fundação Euripides de Marilia -  Faculdade de Informatica.
Marilia - Sao Paulo, Brazil.


Workshop and Program Chair
-------------------------------
Edward Moreno                         Jorge Luiz e Silva
edmoreno@fundanet.br              jsilva@fundanet.br


More information: http://www.fim.fundanet.br/core2000
=================================================
Article: 19323
Subject: Re: MAX7256A dies during ICP
From: deroberts@my-deja.com
Date: Tue, 14 Dec 1999 12:53:17 GMT
Links: << >>  << T >>  << A >>
In article <38510b91.1083590@modem.mecalc>,
  lourens@mecalc.co.za wrote:
> Hi
>
> We have a board with 8 Altera MAX7000 CPLD's in the JTAG chain. Most
> of them are MAX7128A's and MAX7064A's with one MAX7256A. The devices
> work fine and I can program them successfully using the ByteBlaster.
> However, approximately every 10'th time I reprogram the MAX7256, it
> dies. It actually programs successfully, but them fails during the
> VERIFY phase.
>
> After this the ByteBlaster software can not see the JTAG chain
> anymore. Also, the MAX7256 temperature rises within seconds so that it
> is too hot to touch.
>
> Has anybody ever came across this? Any suggestions? I've check the
> layout and power supply and decoupling, it seems fine.
>
Yes, I've seen this.  The programming stream gets corrupted while
programming the 7256, and turns some inputs into outputs, the device
then fights other devices driving it and can burn out. I glued heatsinks
onto mine until I got things figured out.

The single biggest problem is the drive capacity of the ByteBlaster.
Altera reccomend buffering the Byteblaster signals if your chain has
more than 3 or 4 devices, and certainly if your blaster or parallel port
cable is in any way extended.

Beyond that, I could only suggest splitting your JTAG chain in two, or
contacting Altera for support (only don't hold your breath).

Derek Roberts.
AT&T Labs Cambridge, UK


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Before you buy.
Article: 19324
Subject: Re: Virtex boards
From: cartman_sspi@my-deja.com
Date: Tue, 14 Dec 1999 15:09:56 GMT
Links: << >>  << T >>  << A >>
I looked into this recently I came across a company called Alpha Data
who had a PCI Virtex board and PMC Virtex card. Can't remember the web
address but I am sure I got it from: www.optimagic.com who also has a
list of other suppliers. I'd ask them all for a quote.

Cart.

In article <832vqk$690$1@pump1.york.ac.uk>,
  "Daryl Bradley" <dwb105@nospam.ohm.york.ac.uk> wrote:
> We have 3 VW300 boards from VCC which, while we have only had limited
use of
> so far are great
>
> using the boards for partial reconfiguration with Jbits, and a some
other
> stuff
>
> Only gripe is that you need either 3 different power supplies (5,
3.3, 2.5V)
> to power up the board or build your own power supply (as we have done)
>
> Also need relevant download cable (Parallel, Xchecker Multilinx etc)
>
> We have just ordered a PCI based XCV1000 board form embedded
solutions -
> have heard this is pretty good but no hands on experience yet
>
> Daryl
>
> <smithers12@my-deja.com> wrote in message
> news:82r6un$1t1$1@nnrp1.deja.com...
> > Hello,
> >
> > I was wondering if anyone has had any experience with the various
> > Virtex-based prototyping boards out on the market (e.g., Avnet, VCC,
> > etc.).  Any recommendations would be appreciated.  Thanks.
> >
> > Sincerely,
> >
> > Hugh
> >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
>


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