Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 19275

Article: 19275
Subject: Re: EEPROM for spartan xl series FPGA?
From: "Holger Kleinert" <Holger@hollgi.de>
Date: Thu, 9 Dec 1999 23:22:13 +0100
Links: << >>  << T >>  << A >>
Theron Hicks <hicksthe@egr.msu.edu> schrieb in im Newsbeitrag: 384FD4C6.5CACADCA@egr.msu.edu...
> FPGA (XCS05XL)                             PROM
> DIN                           <-----                DATA
> CCLK                         ----->               CLK
> DONE                        ----->               CE         (Is this
> direction correct?)
Yes, it is.
> INIT_bar                   ----->                OE/reset_bar
>
> my guess for the other signals
>
> FPGA INPUTS                                  OTHER SIGNALS
> M0                             -----                 open circuit(??)
> M1                             -----                 open circuit(??)
Do not leave this pins open.
The internal pull up resistors of approx 90k Ohms are not enough for
supressing possible noise which may generate strange bevavior to the FPGA.
Better pull it up with 4K7.

I don't have worked with the XCS FPGAs for a longer time.
So, I have forgotten the exact connectrions for some signal... except the M Signals.

PS : The devices will boot proberbly using 2.2V, an XCS10XL and
an ATMEL 17LV128. Once this was a design error mada by me .. but it worked :-)

Holger



Article: 19276
Subject: Re: Synopsys backannotation
From: Walter Soto Encinas Junior <soto@icmc.sc.usp.br>
Date: Thu, 09 Dec 1999 20:58:55 -0200
Links: << >>  << T >>  << A >>
Andy Peters wrote:

> >        I suppose there is a problem naming the instances. My placer/router
> >is the XACT6000 and there is no option to control the generation of
> instance
> >names in SDF file. Is there some config in Synopsys analyzer to make the
> >names of instances compatible with the names of SDF? Or this problem needs
> >another solution ?
> 
> Have you compiled the Xilinx simulation libraries?

	All the VITAL libraries were analyzed and the .sim files were generated
without any problem. And the simulation without backannotation is working
fine, too. 


-- 
|                                       Walter Soto Encinas Jr          |
|                                            PhD  Student               |
|                                             IFSC / USP                |
|                                               Brazil                  |
Article: 19277
Subject: Re: CAN testing - Any CANbus cores out there?
From: Jonathan Bromley <jonathan@oxfordbromley.u-net.com>
Date: Thu, 09 Dec 1999 23:37:05 +0000
Links: << >>  << T >>  << A >>
"F.Rodriguez" wrote:
> 
> This is original message from the CAN LIST
> 
> -- CANLIST message --
> 
> The European Space Agency has released the VHDL source code of the
> prototype CAN controller core. Information can be found at the following
> address:
> 
> ftp://ftp.estec.esa.nl/pub/ws/wsd/CAN/can.htm


Many, many thanks - I failed to find this by searching the ESA 
site.

Jonathan Bromley
Article: 19278
Subject: Re: EEPROM for spartan xl series FPGA?
From: "David Hawke" <dhawke@skynow.net>
Date: Fri, 10 Dec 1999 00:18:57 -0000
Links: << >>  << T >>  << A >>
If you are worried about the rise time of your PSU, you can hold off config
until it has risen by holding INIT low...

Dave Hawke.
Xilinx



Article: 19279
Subject: FPGA Benchmarks
From: "Thomas W. Fry" <zaphod@ee.washington.edu>
Date: Thu, 09 Dec 1999 16:37:20 -0800
Links: << >>  << T >>  << A >>
Hi,
    I heard that there are now some benchmarks that are being used to
compare different FPGA architectures and that Media Bench was one of
them. Does anyone know where you can get this, or where other benchmark
suits that are geared toward FPGA's are? Thanks,

Tom Fry
University of Washington
zaphod@ee.washington.edu


Article: 19280
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 09 Dec 1999 16:47:37 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A53CEEECC5BE3831CCCD32A6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Jan Gray wrote:
> 
[ stuff about multiport SRAMS in FPGAs, concentrating on 3-port RRW ]
> 
> * 2 2-port SRAMs and do the two RR accessses and the W access in one cycle.

A 25% more area efficient implementation would use 1 2-port and 1
1-port.

- John
--------------A53CEEECC5BE3831CCCD32A6
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for John L. Smith
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             John L. Smith
n:              Smith;John L.
org:            Visicom Imaging Products
adr:            10052 Mesa Ridge Court;;;San Diego;CA;92121;USA
email;internet: jsmith@visicom.com
title:          Principal Engineer
tel;work:       858-320-4102
tel;fax:        858-??????
note:           http://www.visicom.com/products/Vigra/index.html
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard


--------------A53CEEECC5BE3831CCCD32A6--

Article: 19281
Subject: Re: JTAG programming problem with multiple Altera MAX7000A devices
From: Burn@D.man (Free Spirit)
Date: Fri, 10 Dec 1999 01:27:04 GMT
Links: << >>  << T >>  << A >>
What's your chain topology?
Do you have other devices in the chain?
I have 2 GALs and 2 Max 7128A's and dont have 
problems under NT or Win98 with a ByteBlaster.
How do the TCK,TMS and TDI look on a scope?
Are you getting a good connect on the VCC pin?
The JTAG interface powers from the Target VCC pin.
I had a lot of problems with the Lattice isp cable,
it was sensitive to parallel port timing, it would
work on one system, only when it was daisy-chained
through a Zip drive. I never got it work my NT system,
using a Soyo motherboard.
You might try putting a 1uf cap on TCK to slow it down,
just to see if you are having a marginal setup problem with
TMS and TDI.
On Thu, 09 Dec 1999 00:00:46 -0500, Andrew Reddig <andyr@tekmicro.com> wrote:

>Subject tells the story.  We have started to have a lot of problems
>lately programming Altera devices through JTAG.  We have both a
>"BitBlaster" (serial interface to JTAG port) and a ByteBlasterMV
>(parallel port interface to JTAG).  We have had a wide range of problems
>on many different designs.
>
>The common thread is that the device fails to program and MAX-Plus
>either reports that the device is unknown, not installed, JTAG chain is
>bad, or else does an examine/program and then fails with verify errors. 
>In the latter case, we can often get exactly the same # of verify errors
>each time.
>
>This happens with two different computers, a couple of different
>versions of MAX-Plus, and both the BitBlaster and the ByteBlasterMV.  It
>also happens with both single EPLD systems and cards that have five
>devices in a chain.
>
>The only common thread is that the problem seemed to start when we
>started using MAX7000A's, although it sometimes happens with 7000S
>devices as well.
>
>We've checked pinouts, clocks, signals; all look fine.  We've tried
>using the ByteBlasterMV with both 3.3V and 5V, no difference.  We've
>buzzed out the cables, tried terminating TCK, and nothing works.  But,
>every now and then, you can press "Program" 55 times and get it to work
>on the 55th.  Sometimes, you can program all 5 chips in a chain a few
>times without complaint, then it starts failing again.
>
>Anybody seen this kind of thing?  Any ideas?  We're pulling our hair
>out.
>
>Thanks for any suggestions.

Article: 19282
Subject: Re: Synopsys backannotation
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 9 Dec 1999 18:29:01 -0700
Links: << >>  << T >>  << A >>
Walter Soto Encinas Junior wrote in message
<3850342F.803CC92C@icmc.sc.usp.br>...
>Andy Peters wrote:
>
>> >        I suppose there is a problem naming the instances. My
placer/router
>> >is the XACT6000 and there is no option to control the generation of
>> instance
>> >names in SDF file. Is there some config in Synopsys analyzer to make the
>> >names of instances compatible with the names of SDF? Or this problem
needs
>> >another solution ?
>>
>> Have you compiled the Xilinx simulation libraries?
>
> All the VITAL libraries were analyzed and the .sim files were generated
>without any problem. And the simulation without backannotation is working
>fine, too.

Nope, not them : the Xilinx unisim and simprim libraries.  See:

http://www.xilinx.com/techdocs/2561.htm

for details.


--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Article: 19283
Subject: Re: EEPROM for spartan xl series FPGA?
From: "Luc Nantel" <luc_nantel@videotron.ca>
Date: Thu, 9 Dec 1999 21:07:56 -0500
Links: << >>  << T >>  << A >>
Have you looked at the new XC1800 series FLASH (JTAG ISP) SPROM from Xilinx?


"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:384FD4C6.5CACADCA@egr.msu.edu...
| Can someone dirrect me to a specific ap note on how to connect a
| configuration prom to a Spartan XCS05XL series FPGA.  I would prefer to
| avoid OTP devices.  So far I have found information on the XC17S05.
| This is, of course, a OTP device.  I have only one FPGA and one EEPROM.
| Based on that info I think that this is correct:
|
| FPGA (XCS05XL)                             PROM
| DIN                           <-----                DATA
| CCLK                         ----->               CLK
| DONE                        ----->               CE         (Is this
| direction correct?)
| INIT_bar                   ----->                OE/reset_bar
|
| my guess for the other signals
|
| FPGA INPUTS                                  OTHER SIGNALS
| M0                             -----                 open circuit(??)
| M1                             -----                 open circuit(??)
| PWR_DOWN_bar     -----                 held low until power is stable
|
| The data sheet on the Spartan configuration prom shows a reset input on
| the FPGA but I can't find that in the data sheet (except for the one
| generated in my design) so I assume that that is really the PWR_DOWN_bar
| signal.  In my case the power could come up comparitively slowly.  (I am
| note certain how long, but 50 mSec is only 3 full cycles at 60 Hz.)   I
| note that the ap notes talk about power supply rise time (1 to 3 volts)
| being less than 50 mSec.  Is there a _simple_ hardware work around for
| this problem such as holding some pin(s) low?  I would rather not switch
| the FPGA power supply.
|
| Obviously the In-Circuit-Programable device would use some more signals
| on the configuration PROM.  What are they and how do I connect them?
| Again specific examples would be greatly appreciated.  I would rather
| get this correct the first time.  While I am at it what ISP device is
| appropriate for the XCS05XL Spartan FPGA?  As a second alternative a
| reprogramable but not ISP device would be a second choice.  Thanks so
| much for your patience and help.
|


Article: 19284
Subject: Re: Is there two-read one-write asynchronous SRAM in FPGA?
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 09 Dec 1999 23:44:15 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------C6A4AF46111C2F39B9C3E945
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

My previous post was wrong, you can't build a 3-port 1-cycle
RRW memory from just a 2-port and a 1-port. Both sub-RAMs have
to be updated in the same cycle.

John L. Smith wrote:
> 
> Jan Gray wrote:
> >
> [ stuff about multiport SRAMS in FPGAs, concentrating on 3-port RRW ]
> >
> > * 2 2-port SRAMs and do the two RR accessses and the W access in one cycle.
> 
> A 25% more area efficient implementation would use 1 2-port and 1
> 1-port.
> 
> - John
> 
>   ------------------------------------------------------------------------
> 
>   John L. Smith <jsmith@visicom.com>
>   Principal Engineer
>   Visicom Imaging Products
> 
>   John L. Smith
>   Principal Engineer        <jsmith@visicom.com>
>   Visicom Imaging Products  HTML Mail
>   10052 Mesa Ridge Court    Work: 858-320-4102
>   San Diego                 Fax: 858-??????
>   CA                        Netscape Conference Address
>   92121                     Netscape Conference DLS Server
>   USA
>   http://www.visicom.com/products/Vigra/index.html
>   Additional Information:
>   Last Name     Smith
>   First Name    John L.
>   Version       2.1
--------------C6A4AF46111C2F39B9C3E945
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for John L. Smith
Content-Disposition: attachment; filename="vcard.vcf"

begin:          vcard
fn:             John L. Smith
n:              Smith;John L.
org:            Visicom Imaging Products
adr:            10052 Mesa Ridge Court;;;San Diego;CA;92121;USA
email;internet: jsmith@visicom.com
title:          Principal Engineer
tel;work:       858-320-4102
tel;fax:        858-??????
note:           http://www.visicom.com/products/Vigra/index.html
x-mozilla-cpt:  ;0
x-mozilla-html: TRUE
version:        2.1
end:            vcard


--------------C6A4AF46111C2F39B9C3E945--

Article: 19285
Subject: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
From: ydHeVVur <ydHeVVur@biVgAHys.comNOSPAM>
Date: 10 Dec 1999 11:49:14 GMT
Links: << >>  << T >>  << A >>






<!-- Get Specific Variables for cobrand -->
<!-- YESs and NOs are CaSe SeNsItIvE... Always use ALL CAPS for them! -->

    

   


<!-- EXTRA_CODE_AFTER_TOP/BOTTOM are typically used for consistent
	 identification or used for "floating" nav bars. If you say YES
	 make sure you hare corresponding code in /parts/cobrand/ -->



<!-- What Modules to use --->







    










<HTML>
<HEAD>

<TITLE>XOOM.it Servizi Iscritti: root</TITLE>
<META name="resource-type" content=document>
<META name="description" content="XOOM.COM Get your web space free! Get Chat! See Movies! Cool Stuff all for Free!">
<META name="keywords" content="XOOM FREE CHAT WEB SPACE MOVIES EMAIL WEB CLIP ART HTML CLIPART CARDS DOWNLOADS">
<META name=distribution content=global>
</HEAD>

<BODY BGCOLOR="#FFFFFF" BACKGROUND="http://media.xoom.it/new/Background.gif" TEXT="#000000" LINK="#0000FF" VLINK="#0000FF" ALINK="#FF0000">

<!-- Top Part Table -->


<TABLE border=0 cellPadding=0 cellSpacing=0 width=600>
  <TBODY>
  <TR>
    <TD background="http://media.xoom.it/new/Left_Background.gif" vAlign=top wid
th=111>
        <A href="http://www.xoom.it">
        <IMG border=0 height=113 hspace=0 src="http://media.xoom.it/new/logo_corner.gif" width=111>
        </A>
      <TABLE background="http://media.xoom.it/new/spacer.gif" border=0 cellPaddi
ng=0 cellSpacing=0 width=111>
        <TBODY>
        <TR>
          <TD align=middle vAlign=top>

<!--- inizio HOTSPOT --->

<IMG height=1 hspace=0 src="http://media.xoom.it/new/clear.gif" width=90><BR><IMG height=25 hspace=0 src="http://media.xoom.it/new/hot_spots_top.gif" width=90><BR>

<!-- Hotspot 1 -->
<A href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.xoom.it/downloads" target=_top>
<IMG alt="Software Download" border=0 height=27 src="http://media.xoom.it/hotspots/hs_shareit.gif" width=90></A><BR>

<!-- Hotspot 2 -->
<A href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.barzelletta.com&title=hs" t
arget=_top>
<IMG alt="Barzellette via email" border=0 height=27 src="http://media.xoom.it/hotspots/hs_barzelletta.gif" width=90></A><BR>

<!-- Hotspot 3 -->
<A href="http://www.xoom.it/chat" target=_top>
<IMG alt="Preleva la tua Chat" border=0 height=27 src="http://media.xoom.it/hotspots/hs_chat.gif" width=90></A><BR>

<!-- Hotspot 4 -->
<A href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.carli.com/store/WelcomeCarli.asp%3Fcan=WB7-001&title=hs" target=_top>
<IMG alt="Olio Carli" border=0 height=27 src="http://media.xoom.it/hotspots/hs_carli.gif" width=90></A><BR>


<IMG height=1 hspace=0 src="http://media.xoom.it/new/hot_spots_bottom.gif" width=90><BR>
<IMG height=10 src="http://media.xoom.it/new/spacer.gif" width=90><BR>

<!--- fine HOTSPOT --->


<!-- *** HOTSPOT *** -->
<!--< include ("/usr/WWW/parts/hotspot.html");>-->


<!---- inizio RISORSE ---->
<br>
                        <IMG alt="" border=0
            height=161 hspace=0 src="http://media.xoom.it/new/resources.gif"
            useMap=#RESOURCES width=90>
<MAP name=RESOURCES><AREA alt=""
              coords=1,17,88,32
                href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.xoom.it/dizionario&title=ris"
              shape=RECT><AREA alt="" coords=1,34,88,48
              href="http://www.xoom.it/chatroom/xoom" 
              shape=RECT><AREA alt="" coords=2,50,88,65
              href="http://www.xoom.it/products/boutique.php"
              shape=RECT><AREA alt="" coords=2,66,88,80
              href="http://www.xoom.it/helpcenter/"
              shape=RECT><AREA alt="" coords=2,82,88,95
              href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://cartoline.xoom.it/xigo" shape=RECT><AREA alt="" coords=2,97,88,111
              href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.xoom.it/classicmovies"
              shape=RECT><AREA alt="" coords=2,113,88,126
              href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.tuttogratis.com/cgi/entra.cgi&title=ris"    
              shape=RECT><AREA alt="" coords=2,129,88,141
              href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.pronto.i
t"            
              shape=RECT><AREA alt="" coords=2,145,88,157
              href="http://www.xoom.it/cgi-bin/redir.cgi?url=http://italia.qxl.c
om/cgi-bin/qxl/link.cgi%3FURL=%26ID=xoom&title=ris1"
              shape=RECT></MAP>
<!--- fine RISORSE --->

<!---- inizio RISORSE ---->
<br><br>
                        <IMG alt="" border=0
            hspace=0 src="http://media.xoom.it/services/altriservizi.gif"
            useMap=#altrimap width=90> <MAP name=altrimap><AREA alt=""
              coords=1,17,88,32
              href="http://www.xoom.it/clipart"
              shape=RECT><AREA alt="" coords=1,34,88,48
              href="http://www.xoom.it/downloads"
              shape=RECT>
	    </MAP>
<!--- fine RISORSE --->



</TD></TR></TBODY></TABLE></TD>

        <TD vAlign=top width=489>
        <!--- inizio LATO DESTRO --->      <TABLE BORDER=0 CELLPADDING=0 CELLSPACING=0 WIDTH=489><TR>
<TD HEIGHT=2 BGCOLOR=#000000 COLSPAN=2 WIDTH=489><SPACER TYPE="BLOCK" WIDTH=1 HE
IGHT=2></TD></TR>
</TABLE>
<TABLE BORDER=0 CELLPADDING=0 CELLSPACING=0 WIDTH=489 bgcolor=#ffcc99><TR>
<!-- Inizio banner -->
<STYLE TYPE=text/css>
<!--
xoom8 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:7pt;}
xoom9 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:8pt;}
xoom10 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:8pt;}
xoom12 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:10pt; }
xoom14 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:12pt; }
xoom16 {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:14pt; }
xoomhead {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:14pt; font-weight:bold; }
xoomcomhead {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:10pt; font-weight:bold;}
xoomcomsubhead {font-family:Verdana,Tresbuchet MS,Helvetica,Arial; font-size:9pt; margin-left:4pt; }
-->
</STYLE>


<TD bgcolor=#FFCC66 align=center WIDTH=487>

<table border=0><tr><td height=4 nowrap>
</td></tr></table>

<IFRAME SRC="http://ad.it.doubleclick.net/adi/xoom.it/membersarea;area=membersarea;sz=468x60;ord=4904?" WIDTH=468 HEIGHT=60 MARGINWIDTH=0 MARGINHEIGHT=0 HSPACE=0 VSPACE=0 FRAMEBORDER=0 SCROLLING=no BORDERCOLOR="#FFCC66">
<SCRIPT language="JavaScript1.1" SRC="http://ad.it.doubleclick.net/adj/xoom.it/membersarea;area=membersarea;abr=!ie;sz=468x60;ord=4904?">
</SCRIPT>
<NOSCRIPT>
<A HREF="http://ad.it.doubleclick.net/jump/xoom.it/membersarea;area=membersarea;abr=!ie4;abr=!ie5;sz=468x60;ord=4904?">
<IMG SRC="http://ad.it.doubleclick.net/ad/xoom.it/membersarea;area=membersarea;abr=!ie4;abr=!ie5;sz=468x60;ord=4904?" BORDER=0 WIDTH=468 HEIGHT=60>
</A>
</NOSCRIPT>
</IFRAME>


<CENTER><IMG SRC="http://media.xoom.it/NovLook/spacer.gif" HEIGHT=3 WIDTH=468><BR>
<IMG SRC="http://media.xoom.it/blackline.gif" HEIGHT=1 WIDTH=468><BR>
    
<TABLE BORDER=0 CELLPADDING=0 CELLSPACING=0 WIDTH=100%>
		<TR>
			<TD COLSPAN=4><IMG SRC="http://media.xoom.it/new/clear.gif" WIDTH="487" HEIGHT="4" HSPACE="0" VSPACE="0"><BR></TD>
		</TR>

		<TR>

<!-- Tastino 1 -->
<TD VALIGN=TOP ALIGN=MIDDLE WIDTH=25%><A HREF="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.webcast.it/xoom_partner.htm" TARGET=_top><IMG SRC="http://media.xoom.it/bottoni/topmp3.gif" BORDER=1 WIDTH=88 HEIGHT=31></A><BR>
<FONT FACE="Verdana,Arial,HELVETICA" SIZE=1><SPAN CLASS=X9><B>GUIDA MP3</B></SPAN></FONT></TD>

<!-- Tastino 2 -->
<TD VALIGN=TOP ALIGN=MIDDLE WIDTH=25%><A HREF="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.vnss.net/index.asp%3Fi=XOOM%26m=button&title=button" TARGET=_top><IMG SRC="http://media.xoom.it/Banners/vittoria/button_vnss.gif" BORDER=1 WIDTH=88 HEIGHT=31></A><BR>
<FONT FACE="Verdana,Arial,HELVETICA" SIZE=1><SPAN CLASS=X9><B>GUADAGNA sul WEB</B></SPAN></FONT></TD>

<!-- Tastino 3 -->
<TD VALIGN=TOP ALIGN=MIDDLE WIDTH=25%><A HREF="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.italianetwork.it/" TARGET=_top><IMG SRC="http://media.xoom.it/Banners/italia/It_Network_nero_88x31.gif" BORDER=1 WIDTH=88 HEIGHT=31></A><BR>
<FONT FACE="Verdana,Arial,HELVETICA" SIZE=1><SPAN CLASS=X9><B>NET RADIO</B></SPAN></FONT></TD>

<!-- Tastino 4 -->
<TD VALIGN=TOP ALIGN=MIDDLE WIDTH=25%><A HREF="http://www.xoom.it/cgi-bin/redir.cgi?url=http://www.qxl.com/cgi-bin/qxlhome.cgi/IT/xoom&title=but" TARGET=_top><IMG SRC="http://media.xoom.it/bottoni/qxl88x31.gif" BORDER=1 WIDTH=88 HEIGHT=31></A><BR>
<FONT FACE="Verdana,Arial,HELVETICA" SIZE=1><SPAN CLASS=X9><B>ASTE ON-LINE</B></SPAN></FONT></TD>

		</TR>
		</TABLE>




<!-- fine banner -->
</TD>

        <TD BGCOLOR=#000000><SPACER TYPE="BLOCK" WIDTH=2 HEIGHT=2></TD>
</TR>

<TR>
        <TD HEIGHT=2 BGCOLOR=#000000 COLSPAN=2><SPACER TYPE="BLOCK" WIDTH=1 HEIGHT=2></TD>
</TR>
</TABLE>



<TABLE CELLPADDING=10 BORDER=0> <!-- Inside Table START   Only here for padding -->
<TR><TD>
<IMG SRC="http://media.xoom.it/images/headers/Ooops.gif" ALT="( Ooops! )" WIDTH="450" HEIGHT="48"><P>

<FONT SIZE=+2>
La pagina a cui stai cercando di accedere non può essere trovata!<P></FONT>

Cause possibili:<P>

<UL>
<LI TYPE="circ">La pagina è momentaneamente offline per allestimento. Controlla l'homepage di XOOM.it per il sistema status/alerts e riprova più tardi.
<LI TYPE="circ"> Indirizzo non corretto. (Ricorda, gli indirizzi URL sono case-sensitive!) </LI>
<LI TYPE="circ">La suddetta pagina non esiste più</LI>
<LI TYPE="circ">Il membro è stato rimosso per violazione delle  <A HREF=http://xoom.it/TOS>Condizioni di Utilizzo</A>di XOOM.it.</FONT><P>
</UL>

XOOM.it non permette riferimenti a:<P>

<UL>
<LI TYPE="circ">materiale pornografico e a sfondo sessuale di natura oscena; 
<LI TYPE="circ">materiale che viola i diritti d'autore, in particolare software pirata
                        ("WAREZ, CRACK") file musicali, immagini, video, testi protetti da
                        copyright; 
<LI TYPE="circ">materiale offensivo incluse espressioni diffamatorie, di fanatismo,
                        razzismo, odio, irriverenza o minaccia; 
<LI TYPE="circ">materiale che promuove o fornisce informazioni che istruiscano su
                        attività illegali o che possano causare pregiudizio a terzi; 
<LI TYPE="circ">software, informazioni o altro materiale contenente virus o componenti
                        dannosi; 
<LI TYPE="circ">iniziative legate al gioco d'azzardo, concorsi, giochi che richiedono una
                        partecipazione a titolo oneroso. 
<LI TYPE="circ">Inserire sulla tua pagina pubblicità o banner di sponsor. 
<LI TYPE="circ">Rimuovere dalla tua pagina il banner di XOOM.it e relativi collegamenti a
                        XOOM.it o sue directory. 
<LI TYPE="circ">Concedere l'accesso alla tua pagina(e) XOOM.it solo a utenti con
                        password. 
<LI TYPE="circ">Inviare email utilizzando un indirizzo di XOOM.it o contenenti riferimenti
                        alla tua home page su XOOM.it. 
<LI TYPE="circ">Utilizzare nella fase di registrazione come membro un account di email
                        che non è il tuo o che non funziona. 
<P>
</UL>

<FONT SIZE=+2>Per conoscere al completo le Condizioni di Utilizzo
                   clicca <A HREF=http://xoom.it/TOS>qui</A>.<P>

Se pensi che la tua pagina membro sia stata rimossa
                   per errore, spedisci una e-mail a  <A HREF=mailto:webmaster@xoom.it>Webmaster</A>.<P>

<A HREF="http://xoom.it/signup/JoinNow.xihtml?R=0&P=7">Iscriviti ora a XOOM.it! E' gratis!</A></FONT><P>

</FONT>
</TD></TR></TABLE>

</TD></TR>

  <TR>
    <TD background="http://media.xoom.it/new/Left_Background.gif" height=70
    vAlign=bottom width=111><IMG align=baseline height=70 hspace=0
      src="http://media.xoom.it/new/left_bottom4.gif" width=111></TD>
    <TD height=70 vAlign=top width=489 bgcolor=#ffcc66>

        <!---- punto di inserimento snap ----->


      <TABLE border=0 cellPadding=0 cellSpacing=0 height=2 width=489>
        <TBODY>
        <TR>
          <TD bgColor=#000000 colSpan=2 height=2 width=489><SPACER HEIGHT="2"
            WIDTH="1" TYPE="BLOCK"></TD></TR></TBODY></TABLE>
      <TABLE border=0 cellPadding=0 cellSpacing=0 height=66 width=489>
        <TBODY>
        <TR>
          <TD bgColor=#ffcc66 width=487><IMG height=5 hspace=0 src="http://media.xoom.it/new/spacer.gif" width=314><BR><B><FONT class=X11 face="Verdana, Arial, Helvetica">&nbsp;&nbsp;&nbsp;Iscriviti a XOOM.it adesso per questi servizi gratuiti!<BR></FONT>

<FONT class=X11 face="Verdana, Arial, Helvetica">&nbsp;&nbsp;&nbsp;</FONT><FONT class=xh9 face="Arial, Helvetica" size=1><A href="http://xoom.it/webspace/">Spazio Web</A> | <A href="http://xoom.it/email/">Email</A> | <A href="http://xoom.it/chat/">Chat Room</A> | <A href="http://xoom.it/cgi-bin/redir.cgi?url=http://counter.xoom.it/">Xoomcounter</A> | <A href="http://xoom.it/clipart/">Clip
            Art</A> | <A href="http://xoom.it/downloads/">Area Download</A>
            </FONT></B><IMG height=2 hspace=0
            src="http://media.xoom.it/new/spacer.gif" width=314><BR><FONT class=
X11
            face="Verdana, Arial, Helvetica">&nbsp;&nbsp;</FONT><FONT class=X9
            face="Arial, Helvetica" size=1><A href="http://xoom.it/about">Chi e' Xoom.it</A> |
 <A href="http://xoom.it/about/advertising">Pubblicita'</A> | <A
            href="http://xoom.it/PPS">Legge sulla privacy</A> | <A
            href="http://xoom.it/TOS">Condizioni di utilizzo</A><BR><A
            href="http://xoom.it/copyright">Copyright</A> xa9 1999 Licenze XOOM.it. Tutti i d
iritti riservati. Powered by <a href=http://www.it.net><b><font color="#800000">
IT</font><font color="#008000"><i>net</i></b></a></FONT>.
                        <br>
                        <BR clear=all><IMG height=5 hspace=0
            src="http://media.xoom.it/new/spacer.gif" width=314><BR></TD>
          <TD bgColor=#000000 width=2><SPACER HEIGHT="2" WIDTH="2"
            TYPE="BLOCK"></TD></TR></TBODY></TABLE>
      <TABLE border=0 cellPadding=0 cellSpacing=0 height=2 width=489>
        <TBODY>
        <TR>
          <TD bgColor=#000000 colSpan=2 height=2 width=489><SPACER HEIGHT="2"
            WIDTH="1" TYPE="BLOCK"></TD></TR></TBODY></TABLE></TD></TR>
  <TR>
    <TD align=left colSpan=2 vAlign=top><IMG height=20 src="http://media.xoom.it/new/fade_bottom.gif" width=250>
</TD></TR></TBODY></TABLE>
</FORM>
</BODY>
</HTML>


Article: 19286
Subject: Re: Synopsys backannotation
From: "Daniel K. Elftmann" <elftmann@ix.netcom.com@mindspring.com>
Date: Fri, 10 Dec 1999 08:36:22 -0500
Links: << >>  << T >>  << A >>
Walter,

It appears to be a naming style issue.  Note that the SDF file does not have
the round braces on the 0 (ie COUNT(0) vs COUNT_0_) but the netlist does.

You'll probably need to modify your Synopsys script, ala:

/***********************************************************/
/* Need to set up name rules based on the language type    */
/* prevents problems with sdf files                        */

bus_naming_style = "%s_%d"
bus_dimension_separator_style = "_"
define_name_rules PROASIC -allowed "A-Z a-z 0-9_" \
                            -first_restricted "_ 0-9" \
                            -last_restricted "_"
default_name_rules = PROASIC

You can force the new naming style after compilation and before writing out
your netlist with the following command.

change_names -h -rule PROASIC

Sorry for the Actel twist.

Walter Soto Encinas Junior <soto@icmc.sc.usp.br> wrote in message
news:385023E4.722A4379@icmc.sc.usp.br...
> Hi
>
>         This is a question from a recent Synopsys user. I did a small
design
> to XC6200 using structural VHDL. I have the VITAL compatible library with
> XC6200 primitives (AND, OR, and so on).
>
>         I analyzed this design for simulation.  The high level
(behavioral)
> simulation works well.  But I can't backannotate the design with the
timing
> parameters generated by the placer/router tool, for accurate gate-level
> simulation.  These parameters are in SDF format, and looking into the
file,
> it makes sense. Look:
>
> (CELL
>         (CELLTYPE "AND2B1")
>         (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
>         (DELAY
>                 (ABSOLUTE
>                         (PORT I0 (9.476:9.476:9.476) (8.143:8.143:8.143))
>                         (IOPATH I0 O (0:0:0) (0:0:0))
>                         (PORT I1 (3.040:3.040:3.040) (3.575:3.575:3.575))
>                         (IOPATH I1 O (0:0:0) (0:0:0))
>         ...
>
>         When I read the design the messages are:
>
> # vhdlsim -fi_all -sdf_typ -sdf_top /tb_addr/c_addr -sdf addr.sdf
CFG_TB_ADDR
>
> **Error: vhdlsim,259:
>     (SDF File: addr.sdf Line: 20) instance
>     /TB_ADDR/C_ADDR/COUNT_COL/COUNT_0_INI_1_C_MUX not found.
>
> ... and a lot of messages about other instances
>
>         Looking into the design tree, using vhdlsim, I found the path to
the
> cell shown above.
>
> # pwd
> /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX
> # ls
> TIMINGCHECKSON  MSGON           TIPD_I1         I1
> VITALBEHAVIOR
> INSTANCEPATH    TPD_I0_O        TIPD_I0         I0              I1_IPD
> XON             TPD_I1_O        O               WIREDELAY       I0_IPD
>
>         I suppose there is a problem naming the instances. My
placer/router
> is the XACT6000 and there is no option to control the generation of
instance
> names in SDF file. Is there some config in Synopsys analyzer to make the
> names of instances compatible with the names of SDF? Or this problem needs
> another solution ?
>
>         Sorry for the long posting. But it is very, very important! Thanks
in
> advance.
>
> --
>
> |                                       Walter Soto Encinas Jr          |
> |                                            PhD  Student               |
> |                                             IFSC / USP                |
> |                                               Brazil                  |


Article: 19287
Subject: MAX7256A dies during ICP
From: lourens@mecalc.co.za (Lourens Geldenhuys)
Date: Fri, 10 Dec 1999 14:37:28 GMT
Links: << >>  << T >>  << A >>
Hi

We have a board with 8 Altera MAX7000 CPLD's in the JTAG chain. Most
of them are MAX7128A's and MAX7064A's with one MAX7256A. The devices
work fine and I can program them successfully using the ByteBlaster.
However, approximately every 10'th time I reprogram the MAX7256, it
dies. It actually programs successfully, but them fails during the
VERIFY phase.

After this the ByteBlaster software can not see the JTAG chain
anymore. Also, the MAX7256 temperature rises within seconds so that it
is too hot to touch.

Has anybody ever came across this? Any suggestions? I've check the
layout and power supply and decoupling, it seems fine.

Regards,
  Lourens



================================================================
Lourens Geldenhuys                Tel:        +27 (0)12 665 1480
Project Engineer                  Fax:        +27 (0)12 665 1495
Mecalc (Pty) Ltd                  e-mail:   lourens@mecalc.co.za
86 Oak Avenue, Highveld Technopark, Centurion, South Africa
================================================================
Article: 19288
Subject: Xilinx COREgen memory initialization files
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Fri, 10 Dec 1999 16:15:06 +0100
Links: << >>  << T >>  << A >>
I want to implement distributed ROMs in a Virtex so I used COREgen
(latest update)
The docs say that the old .coe initialization files are supported. I
still wonder why I got so many error messages...
I then tried with .mif files. COREgen lets you choose the radix (binary
or hex) used in these text files. Well... Choose whatever you want,
it'll work only with binary radix files.

Makes me want to throw all this junk through the window...

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 19289
Subject: Virtex boards
From: smithers12@my-deja.com
Date: Fri, 10 Dec 1999 15:41:12 GMT
Links: << >>  << T >>  << A >>
Hello,

I was wondering if anyone has had any experience with the various
Virtex-based prototyping boards out on the market (e.g., Avnet, VCC,
etc.).  Any recommendations would be appreciated.  Thanks.

Sincerely,

Hugh


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19290
Subject: Re: Synopsys backannotation
From: "David Robinson" <davie@eee.strath.ac.uk>
Date: Fri, 10 Dec 1999 16:36:32 -0000
Links: << >>  << T >>  << A >>
From memory XACT6000 creates incorrect SDF when VHDL blocks are used.  i.e.
instead of <block_label>/<instantiation> you get
<block_label>_<instantiation>

> /TB_ADDR/C_ADDR/COUNT_COL/COUNT(0)/INI/C_MUX

Instead of
      (INSTANCE COUNT_COL/COUNT_0_INI_1_C_MUX)
try
      (INSTANCE COUNT_COL/COUNT_0/INI_1/C_MUX)

David Robinson



Article: 19291
Subject: Re: Xilinx COREgen memory initialization files
From: "Rémi SEGLIE" <rseglie@celogic.com>
Date: Fri, 10 Dec 1999 17:43:04 +0100
Links: << >>  << T >>  << A >>

Nicolas Matringe <nicolas@dotcom.fr> a écrit dans le message :
385118FA.151650B9@dotcom.fr...
> I want to implement distributed ROMs in a Virtex so I used COREgen
> (latest update)
> The docs say that the old .coe initialization files are supported. I
> still wonder why I got so many error messages...
> I then tried with .mif files. COREgen lets you choose the radix (binary
> or hex) used in these text files. Well... Choose whatever you want,
> it'll work only with binary radix files.
>
> Makes me want to throw all this junk through the window...
>
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE

J'ai eu le même problème, en fait pour l'instant les fichiers MIF ne
fonctionnent que si les valeurs sont en binaire.
Cependant avec Logiblox on peut spécifier la base mais c'est mal adapté au
Virtex (...)

Rémi SEGLIE
CELOGIC


Article: 19292
Subject: test message
From: "Richard B. Katz" <rich.katz@nospam.gsfc.nasa.gov>
Date: Fri, 10 Dec 1999 12:48:04 -0500
Links: << >>  << T >>  << A >>
this is a test, two groups.
Article: 19293
Subject: test message
From: "Richard B. Katz" <rich.katz@nospam.gsfc.nasa.gov>
Date: Fri, 10 Dec 1999 12:50:40 -0500
Links: << >>  << T >>  << A >>
test message two, single group
Article: 19294
Subject: Re: constraints between clock domains: can't advance
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Fri, 10 Dec 1999 20:08:27 +0200
Links: << >>  << T >>  << A >>
> Can you post your Verilog?
> 
> Bob Perlman

  Bob and other friends,

  thank you very much for your responses. I have all been busy all the
  time, so I have just found time to pass the Verilog code.

  The dataflow is like this:

           e1_buff                      e1
    +--------------FF-------FF--------------FF----------+
    |              25       25              6           |
    |      e2_buff                      e2              |
    |   +----------FF-------FF--------------FF------+   |
    |   |          25       25              6       |   |
   _|___|__                                        _|___|__
  |        |                                      |        |
  | 25 MHz |                                      |  6 MHz |
  | domain |                                      | domain |
  |________|                                      |________|
    |   |                                           |   |
    |   |                                           |   |
    |   |    f1_empty           f1        f1_buff   |   |
    |   |        |               |           |      |   |
    |   |        V               V           V      |   |
    |   +----FF-------FSM-----FF--------FF----------+   |
    |        25               25        6               |
    |                                                   |
    |                                                   |
    |        f2_empty           f2        f2_buff       |
    |            |               |           |          |
    |            V               V           V          |
    +-------FF-------FSM-----FF--------FF---------------+
            25               25        6


   Very very simplified Verilog code:

   always @ (posedge clk25m)
    begin
     e1_buff0 <= e1;
     e2_buff0 <= e2;
     e1_buff  <= e1_buff0;
     e2_buff  <= e2_buff0;
     casex ({e1_buff, g1})
      <25_MHz_clock_domain>
     endcase
     casex ({e2_buff, g2})
      <25_MHz_clock_domain>
     endcase
     casex ({state_25m, rd_en, f1_empty, f2_empty})
      <FSM_which_outputs_are_f1_and_f2>
     endcase
    end
  
   always @ (posedge clk6m)
    begin
     f1_buff <= f1;
     f2_buff <= f2;
    end
  
   always @ (negedge clk6m)
    begin
     if (some_signal)
      begin
       casex ({state_6m, f1_buff, f2_buff})
        <FSM_which_outputs_are_e1_and_e2>
       endcase
      end
     else
      begin
       dsin <= `HIGH;
       e1   <= `HIGH;
       e2   <= `HIGH;
      end
    end

1. 6 MHz and 25 MHz lojics are above, all modeled in the same Verilog file.
2. Some buffered signals modeled separately, some are modeled in another ALWAYS.
3. 25 MHz logics include several case blocks in parallel (I think so,
-Synplify!!-).
4. Non-blocking assignments (NBAs) used, but no transport delay model #DELAY.

Q1: Not important to put different clock domains in the same Verilog file. Is
it?
Q2: Shall the buffers be modeled separetely? Does Synplify-Xilinx behave
different?
Q3: Shall I pay attention to model separate case in the same ALWAYS, rather than
    completely separate (i.e. each must have its own ALWAYS)?
Q4: Shall I give transport delay?

Postlayout simulations are correct, lab tests fail. Problem: FSMs must toggle
at every of their own clock executions, i.e. their state registers, 1-bit each,
must toggle 0-1-0-1-0-1... but lab test show 0-1-0-1-1-0-1-0 sometimes.

Design Entry: Verilog
Synthesizer: Synplify v5.21
P&R: Design Manager M1.5 patched
Technology: Xilinx XC4044XLA

Utku
Article: 19295
Subject: Altera APEX lpm modules in Synplify
From: "Xanatos" <deletemeaoe_londonfog@hotmail.com>
Date: Fri, 10 Dec 1999 22:49:10 GMT
Links: << >>  << T >>  << A >>
Hi All,

Here is the problem : I was using Quartus for synthesis and P+R. However, as
my design progressed, there were some verilog statements that Quartus will
not handle.
So, I started to use Synplify for synthesis, and import the vqm file into
Quartus and let it fly.
However, I have since started to use dual port and single port rams. I used
the MegaWizard in Quartus to generate the ram files, and pushed it through
synthesis using Quartus, and it was fine (except for the verilog statements
it was choking on).
 However, once I tried the same design files in Synplify, it whined that it
could not find the module lpm_ram_dp and lpm_ram_dq. I assume there must be
some file (like xc4000.v for 4000 series Xilinx parts) that I have to
include with the design. Is this true?

Thanks,
Xanatos.



Article: 19296
Subject: Re: JTAG use after FPGA configuration on board
From: Andrew Cannon <ajc@gmx.net>
Date: Sat, 11 Dec 1999 01:37:17 +0100
Links: << >>  << T >>  << A >>
Yes, you just have to include the "BSCAN" part in your design and connect it
to the TDI, TDO, TMS and TCK IOparts. After configuration you will have full
JTAG access plus the ability to define user defined JTAG instructions.

Andrew


Xanatos wrote:

> Hello All,
>
> Is it possible for a JTAG to work on a Xilinx XC4000 series FPGA after the
> bitfile has been downloaded and configured. I need the JTAG to work on the
> FPGA after configuration. I have a feeling it does, but I would like to
> confirm this to be sure.
>
> Thanks,
> Xan
>
> (if email, remove the delme part in my hotmail address)



Article: 19297
Subject: Re: JTAG programming problem with multiple Altera MAX7000A devices
From: Andrew Reddig <andyr@tekmicro.com>
Date: Fri, 10 Dec 1999 20:23:07 -0500
Links: << >>  << T >>  << A >>
We've made some progress on this.  The ByteBlaster we were using turned
out to have an intermittent fault in a cable.  We got a new one this AM
and it seems to work OK.  We still have a couple of issues that we are
tracking down, but nothing like it was.

Thanks for the input.

--- Andy R.

Free Spirit wrote:
> 
> What's your chain topology?
> Do you have other devices in the chain?
> I have 2 GALs and 2 Max 7128A's and dont have
> problems under NT or Win98 with a ByteBlaster.
> How do the TCK,TMS and TDI look on a scope?
> Are you getting a good connect on the VCC pin?
> The JTAG interface powers from the Target VCC pin.
> I had a lot of problems with the Lattice isp cable,
> it was sensitive to parallel port timing, it would
> work on one system, only when it was daisy-chained
> through a Zip drive. I never got it work my NT system,
> using a Soyo motherboard.
> You might try putting a 1uf cap on TCK to slow it down,
> just to see if you are having a marginal setup problem with
> TMS and TDI.
> On Thu, 09 Dec 1999 00:00:46 -0500, Andrew Reddig <andyr@tekmicro.com> wrote:
> 
> >Subject tells the story.  We have started to have a lot of problems
> >lately programming Altera devices through JTAG.  We have both a
> >"BitBlaster" (serial interface to JTAG port) and a ByteBlasterMV
> >(parallel port interface to JTAG).  We have had a wide range of problems
> >on many different designs.
> >
> >The common thread is that the device fails to program and MAX-Plus
> >either reports that the device is unknown, not installed, JTAG chain is
> >bad, or else does an examine/program and then fails with verify errors.
> >In the latter case, we can often get exactly the same # of verify errors
> >each time.
> >
> >This happens with two different computers, a couple of different
> >versions of MAX-Plus, and both the BitBlaster and the ByteBlasterMV.  It
> >also happens with both single EPLD systems and cards that have five
> >devices in a chain.
> >
> >The only common thread is that the problem seemed to start when we
> >started using MAX7000A's, although it sometimes happens with 7000S
> >devices as well.
> >
> >We've checked pinouts, clocks, signals; all look fine.  We've tried
> >using the ByteBlasterMV with both 3.3V and 5V, no difference.  We've
> >buzzed out the cables, tried terminating TCK, and nothing works.  But,
> >every now and then, you can press "Program" 55 times and get it to work
> >on the 55th.  Sometimes, you can program all 5 chips in a chain a few
> >times without complaint, then it starts failing again.
> >
> >Anybody seen this kind of thing?  Any ideas?  We're pulling our hair
> >out.
> >
> >Thanks for any suggestions.

-- 
Andrew Reddig                            andyr@tekmicro.com
TEK Microsystems, Incorporated                 781.270.0808
One North Avenue                           Fax 781.270.0813
Burlington, MA  01803           Web http://www.tekmicro.com
Article: 19298
Subject: FPGA to ASIC Conversion?
From: "Milliwave" <milliwave@rfengineering.freeserve.co.uk>
Date: Sat, 11 Dec 1999 12:31:14 -0000
Links: << >>  << T >>  << A >>
Hello does anyone know of any FPGA to ASIC conversion CAD tools? Where I
could get some on
the net and have ago?

cheers



Article: 19299
Subject: Re: FPGA Benchmarks
From: Brian Dipert <bdipert@NOSPAM.pacbell.net>
Date: Sat, 11 Dec 1999 06:38:32 -0800
Links: << >>  << T >>  << A >>
Tom,
Check out my article in the May 27, 1999 issue of EDN
(http://www.ednmag.com/ednmag/reg/1999/052799/11cs.htm)

>Hi,
>    I heard that there are now some benchmarks that are being used to
>compare different FPGA architectures and that Media Bench was one of
>them. Does anyone know where you can get this, or where other benchmark
>suits that are geared toward FPGA's are? Thanks,
>
>Tom Fry
>University of Washington
>zaphod@ee.washington.edu
>

Brian Dipert
Technical Editor: Memory, Multimedia and Programmable Logic
EDN Magazine: The Design Magazine Of The Electronics Industry
http://www.ednmag.com
1864 52nd Street
Sacramento, CA   95819
(916) 454-5242 (voice), (916) 454-5101 (fax)
***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY***
mailto:bdipert@NOSPAM.pacbell.net
Visit me at http://members.aol.com/bdipert


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search