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Messages from 19975

Article: 19975
Subject: Re: looping FIFO?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 20 Jan 2000 15:53:48 -0800
Links: << >>  << T >>  << A >>


Mark Summerfield wrote:

> Austin Franklin wrote:
> > Problem with using SRAM, is I am pinbound at this point...8k is another 14
> > pins...don't think I can do it...but that would be my first choice....if I
> > had the pins...
>
> You could use an external counter with your SRAM -- then you'd only need
> enough FPGA pinouts to connect to the control/status pins of the
> counter.  Maybe implement an application-specific counter in a small
> PLD?
>
>

You might want to look at the new in-system-programmable Serial PROMs, like
Xilinx XC1800. They have 8 parallel outputs and run pretty fast.
I have not researched this any deeper, but it would be a cheap and low-power
solution, using very few pins.
Peter Alfke, Xilinx Applications


Article: 19976
Subject: Re: Xilinx vs. other FPGAs manufactrers
From: dmac <dmac@cutme.matter200.demon.co.uk>
Date: Fri, 21 Jan 2000 00:01:41 +0000
Links: << >>  << T >>  << A >>

Historically,

Xilinx:
        wank tools              hot silicon

Altera:
        easy tools              wank silicon

Easy life follows easy tools.

Obviously my opinion only - not wishing to invoke infinite thread

dave

-- 
dmac
Article: 19977
Subject: Re: Xilinx vs. other FPGAs manufactrers
From: "peter dudley" <padudle@worldnet.att.net>
Date: Thu, 20 Jan 2000 17:58:24 -0700
Links: << >>  << T >>  << A >>
I prefer the Xilinx tool philosophy to that of Altera. Xilinx provides nice
schematic libraries for Viewlogic, Mentor, Orcad, ...  Generally I use
Viewlogic to design my system so I like to use it for my fpga's as well.
This way I can do board or system level simulation very easily.

Historically to use Altera it was necesary to learn their design tools and
then to do board level simulation you had to write out a huge structural
vhdl file for the fpga.

The Xilinx/Viewlogic combo is hard to beat.

--
Pete Dudley

Arroyo Grande Systems

Ray Andraka <randraka@ids.net> wrote in message
news:3887666C.6E66F592@ids.net...
> Frankly, I don't get it either.  I've remarked many times on the
shortcomings of
> the Altera acrhitectures with respect to DSP applications here in this
newsgroup
> (you can search deja-news if you are curious).  I've also found the Xilinx
> support hotline infinitely more responsive than Altera's help line (it
could
> still use quite a bit of help though), so it's not that.  Altera has been
a
> little more synthesis friendly, mostly because of the global routing
structure,
> but I think virtex has closed that gap somewhat.
>
> I think a large part of it may be 1) what users are used to, and 2)
percieved
> ease of use.  Altera has a very aggressive university program which puts
the
> altera devices and tools into student's hands at virtually no cost.
Xilinx
> isn't nearly so forthcoming on that front.  Altera's tools are more 'push
the
> big green button and let it go' than xilinx, which is fine when you are
doing
> designs that don't effectively use the FPGA's capability.  Altera tools
lack the
> controllability needed to tweak the design compilation, which may make the
tool
> less onerous to learn but more frustrating for the accomplished user.
>
> For DSP, you really need an effective carry chain architecture, and the
ability
> to efficiently realize delay queues.  Altera's carry chain structure is
crippled
> for all but the most basic arithmetic functions, and delay queues chew up
an
> awful lot of resource.
>
> George wrote:
>
> > Hi Folks,
> >
> > Which is the best FPGA chip for Digital Signal Processing?
> >
> > In my opinion Xilinx latest VIRTEX FPGAs seem to be  the best.
> >
> > These FPGAs features:
> >
> > - Fast carry logic for fast addition and thus multiplication.
> > - Fast synchronous distributed RAMs. These can implment very quick shift
> > registers.
> > - Large and very fast on chip RAMs (BlockRAMs). these can implement real
> > dual port RAM, very usefull for FIFO design.
> > - DLLs for clock deskew --> System design
> >
> > These are very important features in DSP applications. I had a look at
other
> > FPGA manufactures, a lot of them  offer similar features but either not
all
> > of them or with some limitation. The closest is Altera in my opinion.
> > So from a pure performance point of view, Xilinx seems to be the best,
is
> > not it?
> > However, I noticed a considerable number of people using Altera devices.
I
> > do not want to advertise for Xilinx, but I cannot see why some people
perfer
> > other parts, is there a cost factor? a support one?
> >
> > Any comments?
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>


Article: 19978
Subject: Re: odd behavior of Virtex RAM Block model
From: Ray Andraka <randraka@ids.net>
Date: Fri, 21 Jan 2000 01:45:09 GMT
Links: << >>  << T >>  << A >>
Set the TimingChecksOn generic to "FALSE", that should suppress the
checks.  I'm not sure why those are defaulted TRUE in the unisim
library.  If you look at the vital source, you'll see that generic along
with a whole list of timing generics.

Arrigo Benedetti wrote:

> Dear all,
>
> I was wondering if others have noticed any strange results from the
> *functional* simulation of VHDL design using the Virtex SelectRAM
> Block model from the UNISIM library (I'm using Synopsys). First,
> I get warnings about setup time violations and I don't see why
> since I'm doing a functional simulation:
>
> "*/RAMB4_S2_S4 HOLD  Low VIOLATION ON WEB WITH RESPECT TO CLKB;
>   Expected := 0.01 NS; Observed := 0 NS; At : 146575.1 NS"
> Assertion WARNING at 146575100 PS in design unit VITAL_TIMING from
> process /BENCH/U1/U2/BRAM1/VITALBEHAVIOR:
>
> A quick fix of course is delaying the signal WEB with respect to
> CLKB by 10ps with an after clause in the signal assignment,
> but I should not get this worning at all I think.
>
> I also noticed that the DOA (port A outputs) go active as soon as ENA
> goes from 0 to 1 instead of going active with the transition of
> the clock from 0 to 1.
>
> Any ideas?
>
> Thanks in advance,
>
> -Arrigo
> --
> Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
> Caltech, MS 136-93                              phone: (626) 395-3695
> Pasadena, CA 91125                              fax:   (626) 795-8649

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Reply-To: "Sherdyn" <sherdyn@yahoo.com>
Article: 19979
Subject: Biphase mark decoder
From: "Sherdyn" <sherdyn@yahoo.com>
Date: Fri, 21 Jan 2000 10:42:59 +0800
Links: << >>  << T >>  << A >>
Hi,

Can someone tell me how I can extract a clock embedded in a serial stream
which is biphase mark coded? I have only a single input stream to FPGA and
need to extract some bits within a frame of 90 bits (assuming I have an
independent clock which is running 2 times or more). The only thing I know
is I would be able to do that with a Digital PLL but do not exactly sure
what it is.




Article: 19980
Subject: Re: Biphase mark decoder
From: murray@pa.dec.com (Hal Murray)
Date: 21 Jan 2000 03:11:01 GMT
Links: << >>  << T >>  << A >>

> Can someone tell me how I can extract a clock embedded in a serial stream
> which is biphase mark coded? I have only a single input stream to FPGA and
> need to extract some bits within a frame of 90 bits (assuming I have an
> independent clock which is running 2 times or more). The only thing I know
> is I would be able to do that with a Digital PLL but do not exactly sure
> what it is.

I think biphase is also called Manchester - as used in Ethernet.

Get out paper and pencil and try a few things.  You can probably
figure it out.

It's a lot easier if you have a clock that's running at 8x or 16x
rather than 2x.

The general idea is to have a small state machine that keeps track
of the input bit cell.  Suppose you have a 16x clock.  There will be
a transition on the input signal, either between bits or in the middle
of a bit cell.  Call that state 0 and number the states as the time
(at 16x) since the start of the current bit.  The bit will normally
be 16 states long - that is you expect the input signal to tell you
there is a new bit after 16 ticks.  But if the clocks differ slightly
it might be 15 or 17.  Your state machine has to do that.

It also has to put out 2 control bits for the downstream logic.  One
is something like a data-valid or here-is-a-bit.  The other is the
value of the bit: 0 or 1.

There might be a good writeup in the documentation for how to program
the SCC (8030) chips.  I think they could do biphase.  Yup, page 5-9 on
my (old yellow) copy.
-- 
These are my opinions, not necessarily my employers.
Article: 19981
Subject: [Q] Reconfigurable cache architecture
From: Huesung Kim <huesung@iastate.edu>
Date: Thu, 20 Jan 2000 21:25:48 -0600
Links: << >>  << T >>  << A >>
This could be a very fundamental question.
I have a question about the actual/real cache architecture.
Taught In most of Comp. Arch. classes, a conventional cache has one row
and one column decoder with a bunch of adjacent memory cells.

I conver a cache memory into a functional unit. (LUT-based)
Although I added some logic to realize a function, the reconfigurble
cache is faster than a conventional cache.

Thus, I wonder if real/commercial caches have parallel decoding
structure (not
hierarchical) with segmented bit/word lines and dedicated local decoders
to each partitioned sub block, which is emplyed in the reconfigurable
cache.

If there is a parallel decoding scheme in caches (different from above),
what kind of structure is it?

Thanks.
Article: 19982
Subject: Re: Biphase mark decoder
From: khall@pacbell.net (Kelly Hall)
Date: Fri, 21 Jan 2000 04:22:25 GMT
Links: << >>  << T >>  << A >>
On Fri, 21 Jan 2000 10:42:59 +0800, Sherdyn <sherdyn@yahoo.com> wrote:
>Can someone tell me how I can extract a clock embedded in a serial stream
>which is biphase mark coded? I have only a single input stream to FPGA and
>need to extract some bits within a frame of 90 bits (assuming I have an
>independent clock which is running 2 times or more). The only thing I know
>is I would be able to do that with a Digital PLL but do not exactly sure
>what it is.

As I recall, you should have a 32x clock.  Sample on counts 7 and 23.
If the two samples are the same, the data is a 1, else a 0.  You can
use different clock periods, but be test to test interoperability.

Kelly
Reply-To: "Sherdyn" <sherdyn@yahoo.com>
Article: 19983
Subject: Re: Biphase mark decoder
From: "Sherdyn" <sherdyn@yahoo.com>
Date: Fri, 21 Jan 2000 13:21:07 +0800
Links: << >>  << T >>  << A >>
But how am I going to know the clk frequency? One of the feature of this
design is that it should be able to support 4 different frequencies. (in the
range 400us - 500 us period)

Sherdyn

Kelly Hall <khall@pacbell.net> wrote in message
news:5aRh4.83$oj1.7843@nnrp3-w.snfc21.pbi.net...
> On Fri, 21 Jan 2000 10:42:59 +0800, Sherdyn <sherdyn@yahoo.com> wrote:
> >Can someone tell me how I can extract a clock embedded in a serial stream
> >which is biphase mark coded? I have only a single input stream to FPGA
and
> >need to extract some bits within a frame of 90 bits (assuming I have an
> >independent clock which is running 2 times or more). The only thing I
know
> >is I would be able to do that with a Digital PLL but do not exactly sure
> >what it is.
>
> As I recall, you should have a 32x clock.  Sample on counts 7 and 23.
> If the two samples are the same, the data is a 1, else a 0.  You can
> use different clock periods, but be test to test interoperability.
>
> Kelly


Article: 19984
Subject: Re: Biphase mark decoder
From: "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za>
Date: Fri, 21 Jan 2000 07:39:28 +0200
Links: << >>  << T >>  << A >>
Hi. I have done this for 1553B and other apps. Depending on the data rate
this is not a real problem.
The encoded data has transition edges marking the beginning of bit times.
What you need to do is use these edges to generate a sampling point further
along into the data bit. (Think of having a delay line that moves you say
200 ns from the edge.) For a digital solution detect these edges in the
incoming data stream and use them to reset a 16X or 8X  counter. Use the
count to get the center bit time. Note that some encoding methods do not
always generate an edge at the beginning of the bit cell so the counter must
be able to free run through this and still mark the centre of the cell time.
The next edge will re-sync you again.
Tony

Sherdyn wrote in message <3887c6b4.0@news.cyberway.com.sg>...
>Hi,
>
>Can someone tell me how I can extract a clock embedded in a serial stream
>which is biphase mark coded? I have only a single input stream to FPGA and
>need to extract some bits within a frame of 90 bits (assuming I have an
>independent clock which is running 2 times or more). The only thing I know
>is I would be able to do that with a Digital PLL but do not exactly sure
>what it is.
>
>
>
>


Article: 19985
Subject: Re: Biphase mark decoder
From: "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za>
Date: Fri, 21 Jan 2000 07:44:27 +0200
Links: << >>  << T >>  << A >>
Not realy a problem if your clock range is so narrow. The sampling point
must be in the middle. Say 250us (for your 400-500us spread) from the start
cell bit time. For the 400us case this is just shifted out bu 50us.
Tony
Sherdyn wrote in message <3887ebc5.0@news.cyberway.com.sg>...
>But how am I going to know the clk frequency? One of the feature of this
>design is that it should be able to support 4 different frequencies. (in
the
>range 400us - 500 us period)
>
>Sherdyn
>
>Kelly Hall <khall@pacbell.net> wrote in message
>news:5aRh4.83$oj1.7843@nnrp3-w.snfc21.pbi.net...
>> On Fri, 21 Jan 2000 10:42:59 +0800, Sherdyn <sherdyn@yahoo.com> wrote:
>> >Can someone tell me how I can extract a clock embedded in a serial
stream
>> >which is biphase mark coded? I have only a single input stream to FPGA
>and
>> >need to extract some bits within a frame of 90 bits (assuming I have an
>> >independent clock which is running 2 times or more). The only thing I
>know
>> >is I would be able to do that with a Digital PLL but do not exactly sure
>> >what it is.
>>
>> As I recall, you should have a 32x clock.  Sample on counts 7 and 23.
>> If the two samples are the same, the data is a 1, else a 0.  You can
>> use different clock periods, but be test to test interoperability.
>>
>> Kelly
>
>


Article: 19986
Subject: Re: Biphase mark decoder
From: khall@pacbell.net (Kelly Hall)
Date: Fri, 21 Jan 2000 06:15:05 GMT
Links: << >>  << T >>  << A >>
On Fri, 21 Jan 2000 07:44:27 +0200, Anthony Ellis - LogicWorks wrote:
>Not realy a problem if your clock range is so narrow. The sampling point
>must be in the middle. Say 250us (for your 400-500us spread) from the start
>cell bit time. For the 400us case this is just shifted out bu 50us.

Do you want to sample in the center of the cell?  That's where a transition 
may occur, right?  And you don't want to sample at the beginning of
the period, either, because the line could still be ringing.

Details are in the paper "A Formal Model of Asynchronous Communication 
and Its Use in Mechanically Verifying a Biphase Mark Protocol" 
by J Strother Moore. August, 1991. 50 pages.  Abstract is available
here: http://www.cli.com/reports/abstracts.html

Kelly
Article: 19987
Subject: Re: help: signal stuck at 'U' inside generate statement
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Thu, 20 Jan 2000 23:58:45 -0800
Links: << >>  << T >>  << A >>
Hi  Ray,
I am not sure if it is you problem, but it could be so.
As I could understand from your VHDL, "dini" is the bidirectional bus
in you design.
So you may set something on the bus in your stimuli (some not week
signals).
Then in the assignment time you will see "U" on the bus.
Modelsim shows "U" after the assignment if the value on the bus not
correctly resolved.
Hope it helps,


* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 19988
Subject: Re: Desperate Xilinx problem SOLVED!
From: jonathan@canuck.com (Victor the Cleaner)
Date: 21 Jan 2000 09:10:02 GMT
Links: << >>  << T >>  << A >>
Turboproc (turboproc@aol.com) wrote:
: Gee,
: A quick search of support.xilinx.com found:
: Xilinx Answer #6136 : 1.5i: 5200/Spartan/4000E/4000XL/4000EX/4000/4000L 
: Registers are not working properly when device is configured through  JTAG
: http://support.xilinx.com/techdocs/6136.htm


Uh, yes, thank you very much.

1. It's easy to find an answer when you know the answer.

2. It's quite reasonable to believe that a problem described as
   "Urgency:  Hot" in version 1.5i would have been fixed by 2.1i
   update 3.

3. The actual cause of the failure, and the method of working
   around it, is not addressed in the above-mentioned app note.
   Though related, the fix in this case did not involve either 
   instantiating the BSCAN in the design or anything to do with
   the DONE pin.

We look forward to your helpful comments, next time, *before* the
problem has been solved.

Jonathan

Article: 19989
Subject: Re: Indexing functions
From: Phil Endecott <phil_endecott@spamcop.net>
Date: Fri, 21 Jan 2000 10:37:20 +0000
Links: << >>  << T >>  << A >>
Andreas Doering wrote:
> I am interested in the implementation of indexing memory in hardware
> (custom or FPGA).
> The problem is the following:
> say we have inputs a0,a1
> and a0 (a 5-bit-vector) can have 19 different values and
>     a1 (also 5-bit) can have 21 different values.
> We need to address a memory with binary addresses.
> Hence we could concatenate both vectors and needed 1K memory words.

Hi Andreas,

Are the valid values of a0 and a1 consequtive and starting from 0?  I'll
assume not.  I suggest that you give your synthesis tool a reasonably
abstract specification for the problem and let it work out the best
implementation.  Something like the following should give reasonable
results.  I haven't tested this!

--Phil


entity decoder_19 is
  port(a0: in std_ulogic_vector(4 downto 0);
       d19: buffer std_ulogic_vector(18 downto 0)
       );
end entity;

architecture behaviour of decoder_19 is
begin
  p: process(a0)
  begin
    d19<=(others=>'0');
    case a0 is
      when "00000" => d19(0)<='1';
      when "00010" => d19(1)<='1';
      -- and so on for all 19 valid values of a0
      when others => d19<=(others=>'X');
    end case;
  end process;
end architecture;

entity decoder_21 is
  port(a1: in std_ulogic_vector(4 downto 0);
       d21: buffer std_ulogic_vector(20 downto 0)
       );
end entity;

architecture behaviour of decoder_21 is
begin
  p: process(a1)
  begin
    d21<=(others=>'0');
    case a1 is
      when "00000" => d21(0)<='1';
      when "00010" => d21(1)<='1';
      -- and so on for all 21 valid values of a1
      when others => d21<=(others=>'X');
    end case;
  end process;
end architecture;


entity dual_port_ram is
  port(rd_a0: in std_ulogic_vector(4 downto 0);
       rd_a1: in std_ulogic_vector(4 downto 0);
       rd_data: buffer std_ulogic_vector(...);
       wr_a0: in std_ulogic_vector(4 downto 0);
       wr_a1: in std_ulogic_vector(4 downto 0);
       wr_data: in std_ulogic_vector(...)
       );
end entity;

architecture behaviour of dual_port_ram is
  signal rd_d19: std_ulogic_vector(18 downto 0);
  signal rd_d21: std_ulogic_vector(20 downto 0);
  signal wr_d19: std_ulogic_vector(18 downto 0);
  signal wr_d21: std_ulogic_vector(20 downto 0);
begin
  rd_d0: decoder_19
    port map(a0=>rd_a0, d19=>rd_d19);
  rd_d1: decoder_21
    port map(a1=>rd_a1, d21=>rd_d21);
  wr_d0: decoder_19
    port map(a0=>wr_a0, d19=>wr_d19);
  wr_d1: decoder_21
    port map(a1=>wr_a1, d21=>wr_d21);
  
  g0: for i0 in 0 to 18 generate
    g1: for i1 in 0 to 20 generate
      ramcell: block
	port(rd_en0: in std_ulogic,
	     rd_en1: in std_ulogic,
	     wr_en0: in std_ulogic,
	     wr_en1: in std_ulogic);
	port map(rd_en0=>rd_d19(i0),
		 rd_en1=>rd_d21(i1),
		 wr_en0=>wr_d19(i0),
		 wr_en1=>wr_d21(i1));
	signal data: std_ulogic_vector(...);
      begin
	reader: process(rd_en0, rd_en1, data)
	begin
	  if rd_en0='1' and rd_en1='1' then
	    rd_data<=data;
	  else
	    rd_data<=(others=>'Z');
	  end if;
	end process;
	writer: process(wr_en0, wr_en1, wr_data)
	begin
	  if wr_en0='1' and wr_en1='1' then
	    data<=wr_data;
	  end if;
	end process;
      end block;
    end generate;
  end generate;
end architecture;
Article: 19990
Subject: Re: help: signal stuck at 'U' inside generate statement
From: eml@riverside-machines.com.NOSPAM
Date: Fri, 21 Jan 2000 11:28:09 GMT
Links: << >>  << T >>  << A >>
On 21 Jan 2000 03:58:27 GMT, vhdlcohen@aol.com (VhdlCohen) wrote:

>Ray, 
>Your problem is as follows: 
>1. The  constant ntaps is dependent upon Coef'length, with coef a generic or a
>port of a signal (not shown in your example).
>It is also a function of the generate loop index, not a locally static value. 
>Thus, NTAPS is not locally static, but GLOBALLY static. 
> constant ntaps: natural:=(coefs'length+1)/2-filt;--filt=0 for I, 1 for Q
>
>2. QLEN depends upon a GLOBALLY static balue (ntaps), and thus is GLOBALLY
>Static. 
>constant dqlen: natural:=((ntaps+7)/8)*8;--length of delay queue (taps
>
>3. In the statement below the index of dq  is globally static (dqlen/2 +2).
>Thus, this concurrent signal assignment create a DRIVER for EVERY element of
>dq, including dq(0) and dq(1). 
>Since dq(0) is uninitialized, the driver for Dq(0) and dq(1) from above
>statement drives a 'U'. 
> dq(dqlen/2+2)<=dq(dqlen/2 + (ntaps mod 2)); --loop back connection

I'm not so sure about this. The question is, what is the longest
static prefix of:

> dq(dqlen/2+2)

Where:

> constant dqlen: natural:=((ntaps+7)/8)*8;
> constant ntaps: natural:=(coefs'length+1)/2-filt;

and 'filt' is a generate index. The complete name "dq(dqlen/2+2)" is a
static signal name, and so will denote only one driver, if the prefix
(dq) is a static name (it is), and the expression is a static
expression (note *not* a *locally* static expression: nothing here has
to be local, since drivers are created during elaboration).

The expression "(dqlen/2+2)" is [globally] static if:

1) filt is a globally static primary - it is, since it's a generate
parameter

2) coefs'length is globally static. Ray doesn't give a declaration for
coefs, but I'm guessing that it's not of a globally static subtype, or
that he's analysing with '87 set rather than '93 (coefs'length is
definitely not static in '87). It doesn't seem to me that Aldec is
necessarily wrong here - it would be useful to see the coefs
declaration, and find out if '87 or '93 is set.

Evan

Article: 19991
Subject: Re: Random Number Generator
From: murray@pa.dec.com (Hal Murray)
Date: 21 Jan 2000 11:29:33 GMT
Links: << >>  << T >>  << A >>

> someone asked (in another ng) for a way to assign different LAN node
> addresses, or something like that, in an FPGA, and couldn't think of any way
> that a proper synchronous design would ever do anything different from node
> to node; all the 'random' numbers would inevitably be the same. After all,
> if a synchronous digital system wasn't absolutely repeatable, we couldn't
> use it. So some recourse to an external event is needed; I suggested
> measuring the time delay of a slow, very bad external RC, and then somebody
> else suggested using the free-running clock in a Xilinx chip. The 'stirring'
> is just an easy way to get a simple, maybe low-frequency async clock, to
> generate a many-bit random number.

Thanks.

If I understand the problem, you want one random number at power up
(or out-of-reset) time.

I'm not sure stirring helps that.  I'll offer as a straw man, just
letting an LFSR spin until some unpredictable event happens - the
external clock ticks or an R-C charges up.

I'd be more interested in "stirring" if you needed more than one
random number.

The case where stirring will help is if the pattern of numbers
coming out of the un-stirred generator isn't random relative to
the application you have.  Or one generator might get in lock step
with another one.


-- 
These are my opinions, not necessarily my employers.
Article: 19992
Subject: Re: Xilinx vs. other FPGAs manufactrers
From: murray@pa.dec.com (Hal Murray)
Date: 21 Jan 2000 11:46:42 GMT
Links: << >>  << T >>  << A >>

> I think a large part of it may be 1) what users are used to, and 2) percieved
> ease of use.  Altera has a very aggressive university program which puts the
> altera devices and tools into student's hands at virtually no cost.  Xilinx
> isn't nearly so forthcoming on that front.  Altera's tools are more 'push the
> big green button and let it go' than xilinx, which is fine when you are doing
> designs that don't effectively use the FPGA's capability.  Altera tools lack the
> controllability needed to tweak the design compilation, which may make the tool
> less onerous to learn but more frustrating for the accomplished user.

Humm.  Thanks.  I like that analysis.


I usually think of an FPGA that I might use as having two problem areas:
hardware/silicon and software/tools.  Maybe that's not good enough.  Maybe
there are three problem areas:  silicon, tools, and designers.

If all the designers are working on applications that don't push
the bleeding edge of the silicon then they will probably be happy
with tools that only have one big button.

There are a lot of bleeding edge type geeks on this newsgroup.  We
want tools that help us do that.  That means we have to get other
designers to push the edge too so they will demand tools to help
them do their job.  If the chip vendors listen we will get better
tools.

-- 
These are my opinions, not necessarily my employers.
Article: 19993
Subject: Re: help: signal stuck at 'U' inside generate statement
From: Ray Andraka <randraka@ids.net>
Date: Fri, 21 Jan 2000 14:25:42 GMT
Links: << >>  << T >>  << A >>
The problem was the coef'length was not considered static by Modelsim.   I've run
into this before when declaring a controlling a generate using a 'length.  In those
cases the compiler complained that something wasn't globally static.  In this case,
it didn't, which is what threw me off.

Assigning a constant equal to coef'length in the entity rather than in the
architecture fixes the problem.





eml@riverside-machines.com.NOSPAM wrote:

> On 21 Jan 2000 03:58:27 GMT, vhdlcohen@aol.com (VhdlCohen) wrote:
>
> >Ray,
> >Your problem is as follows:
> >1. The  constant ntaps is dependent upon Coef'length, with coef a generic or a
> >port of a signal (not shown in your example).
> >It is also a function of the generate loop index, not a locally static value.
> >Thus, NTAPS is not locally static, but GLOBALLY static.
> > constant ntaps: natural:=(coefs'length+1)/2-filt;--filt=0 for I, 1 for Q
> >
> >2. QLEN depends upon a GLOBALLY static balue (ntaps), and thus is GLOBALLY
> >Static.
> >constant dqlen: natural:=((ntaps+7)/8)*8;--length of delay queue (taps
> >
> >3. In the statement below the index of dq  is globally static (dqlen/2 +2).
> >Thus, this concurrent signal assignment create a DRIVER for EVERY element of
> >dq, including dq(0) and dq(1).
> >Since dq(0) is uninitialized, the driver for Dq(0) and dq(1) from above
> >statement drives a 'U'.
> > dq(dqlen/2+2)<=dq(dqlen/2 + (ntaps mod 2)); --loop back connection
>
> I'm not so sure about this. The question is, what is the longest
> static prefix of:
>
> > dq(dqlen/2+2)
>
> Where:
>
> > constant dqlen: natural:=((ntaps+7)/8)*8;
> > constant ntaps: natural:=(coefs'length+1)/2-filt;
>
> and 'filt' is a generate index. The complete name "dq(dqlen/2+2)" is a
> static signal name, and so will denote only one driver, if the prefix
> (dq) is a static name (it is), and the expression is a static
> expression (note *not* a *locally* static expression: nothing here has
> to be local, since drivers are created during elaboration).
>
> The expression "(dqlen/2+2)" is [globally] static if:
>
> 1) filt is a globally static primary - it is, since it's a generate
> parameter
>
> 2) coefs'length is globally static. Ray doesn't give a declaration for
> coefs, but I'm guessing that it's not of a globally static subtype, or
> that he's analysing with '87 set rather than '93 (coefs'length is
> definitely not static in '87). It doesn't seem to me that Aldec is
> necessarily wrong here - it would be useful to see the coefs
> declaration, and find out if '87 or '93 is set.
>
> Evan

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19994
Subject: Re: help: signal stuck at 'U' inside generate statement
From: Ray Andraka <randraka@ids.net>
Date: Fri, 21 Jan 2000 14:37:00 GMT
Links: << >>  << T >>  << A >>
No, no bidirectionals in the design.  dini was the input signals from outside
this module.  DQ is the delay queue wiring (no logic), whose connections (and
the construction of the whole thing) depends on external parameters including
coef'length.  there are two instances of the generate_S. Each has two delay
queues embodied in DQ(), one chaining the even taps, one chaining the odd.  One
line from Dini(3:0) connected to each of DQ(0) and DQ(1) from the two instances
generated by the generate statement.  As stated earlier, the problem turned out
to be coef'length isn't considered globally static by the simulator, so the size
of DQ is also not globally static.  That apparently confuses the assignments to
each instance of DQ.  changing coef'length to a constant that is assigned in the
entity block from coef'length fixes the problem.  I've run into modelsim
thinking 'length is not static before.  It usually complains though; this time
it didn't, and that threw me off.

Bonio Lopez wrote:

> Hi  Ray,
> I am not sure if it is you problem, but it could be so.
> As I could understand from your VHDL, "dini" is the bidirectional bus
> in you design.
> So you may set something on the bus in your stimuli (some not week
> signals).
> Then in the assignment time you will see "U" on the bus.
> Modelsim shows "U" after the assignment if the value on the bus not
> correctly resolved.
> Hope it helps,
>
> * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
> The fastest and easiest way to search and participate in Usenet - Free!

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19995
Subject: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
From: "Nikolay" <nikolayr@acte.no>
Date: Fri, 21 Jan 2000 16:21:49 +0100
Links: << >>  << T >>  << A >>
Service Pack 2 for Quartus 1999.10 must be installed while Regional Settings
are set to English (US). There is no need to restart the computer, and
Regional Settings can be put back to your preferred settings after
installation. This will at least remove the internal error in the Delay
Annotator.

Regards
  Nikolay Rognlien

giuseppe giachella <il_templare@hotmail.com> wrote in message
news:20000119235730.1309.qmail@hotmail.com...
> It's almost four days that I'm having some devastating experiences using
> Quartus
> 99.10 SP2. It happens that sometimes the fitter goes into an endless loop
> (showing
> the same fitting percentage for hours and hours). Sometimes the fitting is
> completed
> but the Delay Annotation causes an internal error.
> I fear I'm only wasting my time: this Quartus release seems to be full of
> bugs and
> I'm planning to abandon Altera in favour of Xilinx Virtex.
> But what about Xilinx place and route tools? Are they so buggy ?
> Should I expect the same neverending fitting loops using Xilinx tools
> (Alliance or
> Foundation) ?
>
>
>  Sent via Deja.com http://www.deja.com/
>  Before you buy.


Article: 19996
Subject: timing simulation
From: erika_uk@my-deja.com
Date: Fri, 21 Jan 2000 15:38:28 GMT
Links: << >>  << T >>  << A >>
Hi all,

user of XILINX F2.1i

whenever I launch the timing simulation, i have realeased that the
initials values are not as expected on the first cycles.

example, if you use the command "assign", the first value is read twice
from the file, when you instantiate clkdll, the differents clocks
(clk90,clk180,...) have all unexpected state during the first cycles
it's really vital for me to know what real states will take those
signals as i am using them to genrate my different design signal control

regards

--erika


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19997
Subject: Re: Please help : Translogic's .ini files
From: dave_admin@my-deja.com
Date: Fri, 21 Jan 2000 16:56:19 GMT
Links: << >>  << T >>  << A >>
Hi,

I got a few responses from people that advised me simply to
re-install the program. Unfortunately, that is impossible,
because the registry off my workstation is heavily damaged
and one more installation can destroy it completely.
Reinstalling windows is not an option either.
Next week we'll get new Coppermine systems and then the problem
will be solved, but we need a temporary solution until then .
Being a small start-up company we have to save every cent ( as you
can see from my email address, we don't even have a web server yet).
If you have .ini files of HDLENTRY ver 4.0 , please send them to me.

regards,
David.


In article <860b0c$480$1@nnrp1.deja.com>,
  dave_admin@my-deja.com wrote:
> Hi,
>
>  I was cleaning up my hard disk and accidentally deleted all
>  Translogic's .ini files (menu.ini, eale.ini. ease.ini etc). Can
>  anybody send me his .ini files of HDL ENTRY ver 4.0x ? They should
be
>  the same.
>
>  best regards,
>  Dave Man
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19998
Subject: Re: WebFitter???
From: Stephanie Tapp <stapp@xilinx.com>
Date: Fri, 21 Jan 2000 14:50:08 -0800
Links: << >>  << T >>  << A >>
Anthony,

This tool is used by designers for the specific advantages it provides.
There are a number of advantages to using the WebFITTER, such
as the software automatically being updated with the latest version.
It has an easy interface accessible through a web-browser  requiring no
installation to use the software.  Price quotes, report files, and
competitive comparison tools are just a few of the many features
available.   The WebFITTER is located at:

http://www.xilinx.com/sxpresso/webfitter.htm

As with all tools there are projects that the WebFITTER  is ideal for, and
those that it is not.  If a designer is expecting  to have a long design cycle
for their CPLD project and they need  to keep  the same version of
software it is  recommended that they use the downloadable WebPACK
software tools.  This has the same fitting software, and it has additional
software  modules for front-end hdl design as well as download
programming.  You can find this on our website:

http://www.xilinx.com/sxpresso/webpack.htm

Both of these tools provide great solutions for CPLD designers, but
the appropriate tool should be picked based on the needs of the designer.

Best Regards,
Stephanie



Anthony Ellis - LogicWorks wrote:

> For someone new to Xilinx.
> I am planning to use a XC9572 PLD using the online Web compiler and fitter -
> using  VHDL source code.
> Does anyone know how to embedd my pin allocation details into the VHDL
> source.
>
> Thanks Anthony

Article: 19999
Subject: Transmeta CM & Conf. Comp?
From: mu0lia0ni@my-deja.com
Date: Sat, 22 Jan 2000 03:37:23 GMT
Links: << >>  << T >>  << A >>
Hi, I have an idea about combining Configurable
computers/CPU / Processor modules based on FPGA
with the new Transmeta's CODE MORPHING software.
If succesful,  the Intel X86 programs can run
on the configurable computer.
Is this possible? What is your comments/opinion?
Is there any problem with Floating Point operation
on FPGA based configurable computers?
What is the typical setup delay?
Regards


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Before you buy.


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