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Messages from 20225

Article: 20225
Subject: Re: Count 1's algorithm...
From: Mike Treseler <tres@tc.fluke.com>
Date: Tue, 01 Feb 2000 08:35:06 -0800
Links: << >>  << T >>  << A >>
"Pawe³ J. Rajda" wrote:
> 
> Does anyone has an idea how to quickly count number of 1's (or 0's)
> in a word (i.e. 8 or 24 bits). I have to implement this as a part of
> algorithm in FPGA.

I would: 

Assign the word vector to a variable
Loop the length of the variable incrementing an unsigned count for '1'
Assign the count to an unsigned signal.

    -Mike Treseler
Article: 20226
Subject: Re: PCI core in public domain
From: steenl@pal.ECE.ORST.EDU (Steen Larsen)
Date: 1 Feb 2000 16:46:40 GMT
Links: << >>  << T >>  << A >>
In article <s9dng6smer2121@corp.supernews.com>,
Larry Eisner <leisner@bryceusa.com> wrote:
>Does anyone know of a PCI core which is the public domain. My specific needs
>are for a simplified target (non-master) version only. All the licensed
>designs I have found are full blown PCI, with associated full blown license
>fees.
>
Larry, Altera Corp provides a target-only 32/33 core and variants thereof.  I 
don't know the price, but it might be worth looking into.

www.opencores.org is working on one.

http://www.tkt.cs.tut.fi/~havu/ has some VHDL source, but looking at the config
register area there are some holes.

-steen
Article: 20227
Subject: Re: Count 1's algorithm...
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Tue, 01 Feb 2000 12:19:46 -0500
Links: << >>  << T >>  << A >>
Use a carry save (also known as 3 to 2 counters) adder tree.

Josh

"Pawe³ J. Rajda" wrote:
> 
> Does anyone has an idea how to quiclky count number of 1's (or 0's)
> in a word (i.e. 8 or 24 bits). I have to implement this as a part of
> algorithm in FPGA.
> 
> --
> Regards,
> Pawel J. Rajda
> 
> -----------------------------------------------------------------------------
> 
> Pawel J. Rajda, MSc. E.E.         mail: pjrajda@uci.agh.edu.pl
> Dept. of Electronic Engineering    www:
> http://galaxy.uci.agh.edu.pl/~pjrajda
> AGH Technical University           tel: (+48-12) 617 3980
> Al. Mickiewicza 30                 fax: (+48-12) 633 2398
> 30-059 Cracow, POLAND
> -----------------------------------------------------------------------------
Article: 20228
Subject: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
From: "Anthony Ellis - LogicWorks" <a.ellis@logicworks.co.za>
Date: Tue, 1 Feb 2000 19:30:38 +0200
Links: << >>  << T >>  << A >>
Seeing thiis whole thread is about PLL's etc. I have a simple question?

Given a Manchester encoded input at 125Mhz. Can one use a Zilinx PLL, DPLL
or whatever to generate a phase sync'd clock at 125Mhz  to extract the data?

Thanks Anthony


Don Husby wrote in message <8746qh$spc$1@info3.fnal.gov>...
>Ray Andraka <randraka@ids.net> wrote:
>> I hadn't considered a VCO made as a ring oscillator.
>
>Take a look at the Lucent 3T parts.  Their clock synchronizer
>can be used in either DLL or PLL mode.  It's implemented as a
>multi-tap voltage-controlled delay line.
>
>
>--
>Don Husby <husby@fnal.gov>             http://www-ese.fnal.gov/people/husby
>Fermi National Accelerator Lab                          Phone: 630-840-3668
>Batavia, IL 60510                                         Fax: 630-840-5406


Article: 20229
Subject: Re: Xilinx Tools
From: Ray Andraka <randraka@ids.net>
Date: Tue, 01 Feb 2000 20:07:49 GMT
Links: << >>  << T >>  << A >>
F1.4 is two major revisions old.  Apparently you didn't buy the yearly
maintenance, as that gets you the upgrades when they come out.  It also buys
you the lukewarm line support, which compared to others is actually pretty
good (I should know, I seem to find all the bugs in the tools).

Keith Wootten wrote:

> Hi
>
> I've been using Foundation F1.4 for a while, using XC5215 and Spartan
> XCS40.  I want to change to the 3.3V XCS40XL part, but my software won't
> support this part.
>
> Apparently, there is no upgrade path for F1.4 and I'll have to *buy*
> some new software.  To cope with both the XC5215 and the XCS40XL parts,
> I'll need to spend over GBP1000 - yes, one kilopound.  I already spent
> over GBP2000 for the F1.4 stuff, and I'm not a volume user.

                ^^^^^^ you might say you spent a ton on it :-)   (a US ton
is 2000 pounds)


>
>
> Why do they do this?  Surely the small company user has *some* value?
> The support from the dealer was poor and the promised training sessions
> never materialised once the money was paid, so cost of support is no
> justification.
>
> Can anyone recommend a UK dealer who is not a shark?
>
> Cheers
> --
> Keith Wootten

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20230
Subject: Re: Count 1's algorithm...
From: Ray Andraka <randraka@ids.net>
Date: Tue, 01 Feb 2000 20:10:35 GMT
Links: << >>  << T >>  << A >>
The 'best' implementation for FPGAs depends on the amount of time you have to do
it and how many bits you are counting.

For relatively small numbers of bits, use the 4LUTs to create partial sums of the
individual bits.  the 4 LUT outputs will be weighted.  YOu combine like weighted
outputs until you are down to 2 of every weight, then add those vectors together
in a conventional adder.  That's a merged tree implementation.  Note that most
merged tree work in the literature deals with gates with a fanin and fanout of
2.  The FPGA LUTs generally have a fan-in of 4, so for the most efficient merged
tree, you need to modify the approach slightly.

For larger numbers of bits, you can take the odd bits, shift them down by one and
add them to the even bits.  That will get you N/2 values of 0,1 or 2, but you get
to use the carry chain to cut down on the real-estate.  Then take every other two
bit output, shift it down two bits and add to the even sets.  Keep repeating that
till you have one set.

If you have a clock that is n times faster than the data rate (not likely in your
case based on your problem statement), you can use a shift register and counter
(but that was obvious. huh?)



"Pawe³ J. Rajda" wrote:

> Does anyone has an idea how to quiclky count number of 1's (or 0's)
> in a word (i.e. 8 or 24 bits). I have to implement this as a part of
> algorithm in FPGA.
>
> --
> Regards,
> Pawel J. Rajda
>
> -----------------------------------------------------------------------------
>
> Pawel J. Rajda, MSc. E.E.         mail: pjrajda@uci.agh.edu.pl
> Dept. of Electronic Engineering    www:
> http://galaxy.uci.agh.edu.pl/~pjrajda
> AGH Technical University           tel: (+48-12) 617 3980
> Al. Mickiewicza 30                 fax: (+48-12) 633 2398
> 30-059 Cracow, POLAND
> -----------------------------------------------------------------------------

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 20231
Subject: Re: Count 1's algorithm...
From: "John L. Smith" <jsmith@visicom.com>
Date: Tue, 01 Feb 2000 13:14:38 -0800
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0ED228255F832848066B58B3
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit


Traditionally:

You could start with a 2 bit 1-counter, which is called a half-adder.
     ___
A---| H |--Carry
B---|_A_|--Sum

Next, use two of those and an or gate to build a 3 bit 1-counter,
called a full-adder.
                        ___
     ___   |-----------| O |
A---| H |--| ___    |--|_R_|---S1 
B---|_A_|---| H |---|
C-----------|_A_|--------------S0

Next, take two full adders to add up six bits, plus two more
full adders to add up the output from the first two full adders plus
another bit, and you have a 7 bit counter:
    ___
A--| F |
B--| A |----------|
C--|___|-----|    |        ___
             |    |-------| F |
    ___   |- | -----------| A |---S2
D--| F |  |  |   ___   |--|___|---S1
E--| A |--|  |--| F |  |
F--|___|--------| A |--|
G---------------|___|-------------S0              
 

Next, A pair of seven-bit counters, and three more full adders to
add up the output from the seven-bit counters plus another bit, and
you have a 15-bit 1-counter.

Next, ...

For FPGAs:

If it is going into FPGAs, which commonly use 4-LUTs as basic logic
element, you might start at the bottom with a 4 bit 1-counter,
use two of those feeding into an (optimum for your FPGA) two input,
3-bit adder to make an 8 bit 1-counter.

Generally:
The end stages of bit counting algorithms are usually adders, which
sum up the results of different sections of the word being counted.
So optimising bit counting is usually the same as optimizing
adders. Look into adder optimizations.

"Pawe³ J. Rajda" wrote:
> 
> Does anyone has an idea how to quiclky count number of 1's (or 0's)
> in a word (i.e. 8 or 24 bits). I have to implement this as a part of
> algorithm in FPGA.
> 
> --
> Regards,
> Pawel J. Rajda
> 
> -----------------------------------------------------------------------------
> 
> Pawel J. Rajda, MSc. E.E.         mail: pjrajda@uci.agh.edu.pl
> Dept. of Electronic Engineering    www:
> http://galaxy.uci.agh.edu.pl/~pjrajda
> AGH Technical University           tel: (+48-12) 617 3980
> Al. Mickiewicza 30                 fax: (+48-12) 633 2398
> 30-059 Cracow, POLAND
> -----------------------------------------------------------------------------
--------------0ED228255F832848066B58B3
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Content-Transfer-Encoding: 7bit
Content-Description: Card for John L. Smith
Content-Disposition: attachment;
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begin:vcard 
n:Smith;John L.
tel;work:858-320-4102
x-mozilla-html:FALSE
url:http://www.visicom.com
org:Visicom;Imaging Products
adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA
version:2.1
email;internet:jsmith@visicom.com
title:Principal Engineer
x-mozilla-cpt:;27888
fn:John
end:vcard

--------------0ED228255F832848066B58B3--

Article: 20232
Subject: Re: Lattice isp & FPGA
From: "Number Cruncher" <michel.heuts@pandora.be>
Date: Tue, 01 Feb 2000 22:00:49 GMT
Links: << >>  << T >>  << A >>
Hello Xue Zhong,

                                also notice that Lattice will be soon
releasing their
FPGA Godfather family in Q1 - 2000.
www.latticesemi.com

regards,

Michel
WMU


"#XUE ZHONG#" <P144850500@ntu.edu.sg> wrote in message
news:0CF260C495FED111A6610000F866308D09C8C10E@mail3.ntu.edu.sg...
> Hi folks,
>
> In face, I am familiar with Lattice's ispPLD chip 1000, 2000, 3000
> series:
> Such as 1016, 2032, etc. including there structures, and programming.
>
> How about the difference between FPGA and the same. Where can I find
> (website)
> the information about FPGA, and learn it quickly, I need to develop
> circurts with FPGA
> in the near future.
>
> Thanks.
>


Article: 20233
Subject: Re: Tools and how little guy is treated (was Xilinx Tools)
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Tue, 1 Feb 2000 16:13:43 -0600
Links: << >>  << T >>  << A >>
Something these FPGA companies (who I know monitor this list) should make a
point of remembering that those of use that work at small companies now,
won't ALWAYS be working at small companies (either because our small
companies go big time or we go to another larger company).  I, for one, will
remember which companies treated me well and which ones didn't.

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com
Keith Wootten <Keith@wootten.demon.co.uk> wrote in message
news:Fjn8RCAvgul4EwTT@wootten.demon.co.uk...
> Hi
>
> I've been using Foundation F1.4 for a while, using XC5215 and Spartan
> XCS40.  I want to change to the 3.3V XCS40XL part, but my software won't
> support this part.
>
> Apparently, there is no upgrade path for F1.4 and I'll have to *buy*
> some new software.  To cope with both the XC5215 and the XCS40XL parts,
> I'll need to spend over GBP1000 - yes, one kilopound.  I already spent
> over GBP2000 for the F1.4 stuff, and I'm not a volume user.
>
> Why do they do this?  Surely the small company user has *some* value?
> The support from the dealer was poor and the promised training sessions
> never materialised once the money was paid, so cost of support is no
> justification.
>
> Can anyone recommend a UK dealer who is not a shark?
>
> Cheers
> --
> Keith Wootten


Article: 20234
Subject: Xilinx Virtex Decoupling Cap Guidelines
From: "John Janusson" <jjanusson@nospami-o.com>
Date: Tue, 01 Feb 2000 22:18:51 GMT
Links: << >>  << T >>  << A >>
Hello:

I have read XAPP158 (Powering Virtex FPGAs
http://www.xilinx.com/xapp/xapp158.pdf) and found the following
recommendations:


VCCINT    ->    Guideline
-------------------
0.1 uF    ->    One per VCC
47 uF    ->    Four per device (XCV50 - XCV300)
470 uF    ->    One per device

470uF!!!  In my experience, this seems excessive, even after reading the
disclaimer in Answers record #777
(http://support.xilinx.com/techdocs/777.htm)...  I was planning on following
the guidelines sans 470uF cap.  It's a low power design in a XCV100 running
at mostly 4 to 32 MHz...

Can others comment on power related issues in Virtex parts, particularly
related to decoupling and startup???

Thanks...

John


Article: 20235
Subject: Which is the best HDL book ?
From: David T Le <davidtle@flash.net>
Date: Wed, 02 Feb 2000 01:25:20 GMT
Links: << >>  << T >>  << A >>
Please help to give any info for the best verilog book for self-study.

T.I.A

Article: 20236
Subject: Re: Tools and how little guy is treated (was Xilinx Tools)
From: "Kirk Saban" <ksaban@home.com>
Date: Wed, 02 Feb 2000 04:03:49 GMT
Links: << >>  << T >>  << A >>
Keith,

It cannot possibly cost you that much to upgrade your tools, a new
Foundation Base Express package costs $495 USD.

DS-FND-BSX-PC is the P/N that you want.



Keith Jasinski, Jr. wrote in message ...
>Something these FPGA companies (who I know monitor this list) should make a
>point of remembering that those of use that work at small companies now,
>won't ALWAYS be working at small companies (either because our small
>companies go big time or we go to another larger company).  I, for one,
will
>remember which companies treated me well and which ones didn't.
>
>--
>Keith F. Jasinski, Jr.
>kfjasins@execpc.com
>Keith Wootten <Keith@wootten.demon.co.uk> wrote in message
>news:Fjn8RCAvgul4EwTT@wootten.demon.co.uk...
>> Hi
>>
>> I've been using Foundation F1.4 for a while, using XC5215 and Spartan
>> XCS40.  I want to change to the 3.3V XCS40XL part, but my software won't
>> support this part.
>>
>> Apparently, there is no upgrade path for F1.4 and I'll have to *buy*
>> some new software.  To cope with both the XC5215 and the XCS40XL parts,
>> I'll need to spend over GBP1000 - yes, one kilopound.  I already spent
>> over GBP2000 for the F1.4 stuff, and I'm not a volume user.
>>
>> Why do they do this?  Surely the small company user has *some* value?
>> The support from the dealer was poor and the promised training sessions
>> never materialised once the money was paid, so cost of support is no
>> justification.
>>
>> Can anyone recommend a UK dealer who is not a shark?
>>
>> Cheers
>> --
>> Keith Wootten
>
>


Article: 20237
Subject: Re: Which FPGA to learn with?
From: "Joel Kolstad" <Joel.Kolstad@USA.Net>
Date: Tue, 1 Feb 2000 20:22:39 -0800
Links: << >>  << T >>  << A >>
Dave Vanden Bout <devb@xess.com> wrote in message
news:389589F9.27B3C708@xess.com...
> Our software for testing, programming, and debugging the XS40 Board runs
under Win95/98/NT in both a DOS window and using the GUI.  You can read more
about that at http://www.xess.com/gxstools-v3_0.pdf.

Cool, that's really great.  Now if only the XS40 had a way to get more data
back into the PC...



Article: 20238
Subject: Foundation 1.5 VHDL compiler command line
From: Jamie Honan <jhonan@mpx.com.au>
Date: Wed, 02 Feb 2000 15:37:39 +1100
Links: << >>  << T >>  << A >>

I have the Xilinx Student Edition Foundation 1.5, which includes
a VHDL and Verilog compiler.

I want to drive this from the command line, using a makefile (eventually
using wine).

The fndmake package from Xess has the command line params for the
hitop, plus6, ndgbuild commands, which is fine, but for the compiler
includes
Tcl code for fe_shell, which is not in the student edition.

The 'command' is probably something like dpmcomp.

Thanks in advance,
Jamie
Article: 20239
Subject: Re: PCI core in public domain
From: rob_dickinson@my-deja.com
Date: Wed, 02 Feb 2000 11:19:14 GMT
Links: << >>  << T >>  << A >>
Back in the days when fpga's were too small to be full masters with dma
etc Xilinx gave it all away.  I nearly used it recently and it looked
very good.

ftp://ftp.xilinx.com/pub/applications/pci


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20240
Subject: Re: Announcement: Xilinx on Linux HowTo
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 02 Feb 2000 11:38:38 GMT
Links: << >>  << T >>  << A >>
On Sun, 30 Jan 2000 20:06:15 -0500, "B. Joshua Rosen"
<bjrosen@polybus.com> wrote:

>I've just put up a HowTo page for running Xilinx place and route tools under Linux.
>
>http://www.polybus.com/xilinx_on_linux.html

Very nice work, but what about the overhead of running the windows
emulator? Is this significant?

Thanks

Evan

Article: 20241
Subject: Re: Virtex boards
From: david gilchrist <david.gilchrist@gecm.ccom>
Date: Wed, 02 Feb 2000 11:50:26 +0000
Links: << >>  << T >>  << A >>
smithers12@my-deja.com wrote:
> I was wondering if anyone has had any experience with the various
> Virtex-based prototyping boards out on the market (e.g., Avnet, VCC,
> etc.).  Any recommendations would be appreciated.  Thanks.
> 

We've just bought in a Virtex developement board from VCC.  I've not had
much chance to use it yet but we've powered it up and downloaded a
design (via Multilinx Cable) and it seemed to work fine.  I know that
Nallatech (www.nallatech.com) also produce a board, I think it's a PCI
type board.

Cheers

David
Article: 20242
Subject: FreeCore.com has been restored
From: "Rune Baeverrud" <fpga@iname.com>
Date: Wed, 02 Feb 2000 12:17:35 GMT
Links: << >>  << T >>  << A >>
http://freecore.com has now been fully restored.

Rune Baeverrud


Article: 20243
Subject: Re: Tools and how little guy is treated (was Xilinx Tools)
From: "Keith Jasinski, Jr." <jasinski@mortara.com>
Date: Wed, 2 Feb 2000 08:33:45 -0600
Links: << >>  << T >>  << A >>
My comments did not refer to any particular manufacturer.

--
Keith F. Jasinski, Jr.
kfjasins@execpc.com
Kirk Saban <ksaban@home.com> wrote in message
news:F0Ol4.32585$up4.565141@news1.rdc1.ab.home.com...
> Keith,
>
> It cannot possibly cost you that much to upgrade your tools, a new
> Foundation Base Express package costs $495 USD.
>
> DS-FND-BSX-PC is the P/N that you want.
>
>
>
> Keith Jasinski, Jr. wrote in message ...
> >Something these FPGA companies (who I know monitor this list) should make
a
> >point of remembering that those of use that work at small companies now,
> >won't ALWAYS be working at small companies (either because our small
> >companies go big time or we go to another larger company).  I, for one,
> will
> >remember which companies treated me well and which ones didn't.
> >
> >--
> >Keith F. Jasinski, Jr.
> >kfjasins@execpc.com
> >Keith Wootten <Keith@wootten.demon.co.uk> wrote in message
> >news:Fjn8RCAvgul4EwTT@wootten.demon.co.uk...
> >> Hi
> >>
> >> I've been using Foundation F1.4 for a while, using XC5215 and Spartan
> >> XCS40.  I want to change to the 3.3V XCS40XL part, but my software
won't
> >> support this part.
> >>
> >> Apparently, there is no upgrade path for F1.4 and I'll have to *buy*
> >> some new software.  To cope with both the XC5215 and the XCS40XL parts,
> >> I'll need to spend over GBP1000 - yes, one kilopound.  I already spent
> >> over GBP2000 for the F1.4 stuff, and I'm not a volume user.
> >>
> >> Why do they do this?  Surely the small company user has *some* value?
> >> The support from the dealer was poor and the promised training sessions
> >> never materialised once the money was paid, so cost of support is no
> >> justification.
> >>
> >> Can anyone recommend a UK dealer who is not a shark?
> >>
> >> Cheers
> >> --
> >> Keith Wootten
> >
> >
>
>


Article: 20244
Subject: Re: Announcement: Xilinx on Linux HowTo
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: 2 Feb 2000 14:44:56 GMT
Links: << >>  << T >>  << A >>
In comp.emulators.ms-windows.wine eml@riverside-machines.com.NOSPAM wrote:
: On Sun, 30 Jan 2000 20:06:15 -0500, "B. Joshua Rosen"
: <bjrosen@polybus.com> wrote:

:>I've just put up a HowTo page for running Xilinx place and route tools under Linux.
:>
:>http://www.polybus.com/xilinx_on_linux.html

: Very nice work, but what about the overhead of running the windows
: emulator? Is this significant?

W_ine I_s N_ot an E_mulator.
Wine is a reimplementation of the Windows Api with a  loader for window
programs. So the code in your programm runs as fast as in Window, only calls
from your program to the windows API are treated different. They may be
slower, but must not.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 20245
Subject: Re: Which FPGA to learn with?
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 02 Feb 2000 09:49:21 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------25755396617441B1751D0F3B
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Joel Kolstad wrote:

> Dave Vanden Bout <devb@xess.com> wrote in message
> news:389589F9.27B3C708@xess.com...
> > Our software for testing, programming, and debugging the XS40 Board runs
> under Win95/98/NT in both a DOS window and using the GUI.  You can read more
> about that at http://www.xess.com/gxstools-v3_0.pdf.
>
> Cool, that's really great.  Now if only the XS40 had a way to get more data
> back into the PC...

Data goes from the XS40 to the PC through the five parallel port status lines.  You can use another six data lines if you have a bidirectional parallel port.  That's not enough for many applications, but the XS40 is not intended to operate as a coprocessor to the PC.  For that, you need to select one of the many fine PCI-based boards listed at the optimagic site.




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--------------25755396617441B1751D0F3B--

Article: 20246
Subject: Re: Which FPGA to learn with?
From: Dave Vanden Bout <devb@xess.com>
Date: Wed, 2 Feb 2000 09:49:21 -0500
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------ =_NextPart_000_01BF6DF3.79EA22F4
Content-Type: text/plain

Joel Kolstad wrote:

> Dave Vanden Bout <devb@xess.com> wrote in message
> news:389589F9.27B3C708@xess.com...
> > Our software for testing, programming, and debugging the XS40 Board
runs
> under Win95/98/NT in both a DOS window and using the GUI.  You can
read more
> about that at http://www.xess.com/gxstools-v3_0.pdf.
>
> Cool, that's really great.  Now if only the XS40 had a way to get more
data
> back into the PC...

Data goes from the XS40 to the PC through the five parallel port status
lines.  You can use another six data lines if you have a bidirectional
parallel port.  That's not enough for many applications, but the XS40 is
not intended to operate as a coprocessor to the PC.  For that, you need
to select one of the many fine PCI-based boards listed at the optimagic
site.





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------ =_NextPart_000_01BF6DF3.79EA22F4--

Article: 20247
Subject: XC9536 and Abel
From: "Björn Lindegren" <bjorn.lindegren@home.se>
Date: Wed, 2 Feb 2000 16:52:57 +0100
Links: << >>  << T >>  << A >>
Hi.
Using Xilinx Foundation series 2.1i, and I want to build a program with tree
states to XC9536 in the programming language Abel via State Editor.

In state number one outport q1 activates and all the others are deactivated.
In state no two outport q2 activate and q1, q2 is activated and in the last
state is only q3 activated.

When I program XC9536 with the code in the end of this message, all outports
(q1, q2, q3) are activated.

What's wrong?

Thankful for help

Björn Lindegren
"
"  File: E:\PROGRAM\XFS2.1\ACTIVE\PROJECTS\95360130\delay.abl
"  created: 02/02/00 16:31:30
"  from: 'E:\PROGRAM\XFS2.1\ACTIVE\PROJECTS\95360130\delay.asf'
"  by:  fsm2hdl - version: 2.0.1.53
"
module delay
Title 'delay'

Declarations

"clocks
CLK PIN 43;

"input ports

"output ports
q1 PIN 22;
q2 PIN 21;
q3 PIN 13;

"******** SYMBOLIC state machine: Sreg0 ******
Sreg0 STATE_REGISTER;
S1, S2, S3 STATE;


"diagram ACTIONS

"************* state machine: Sreg0 *************

Equations
" clock signals definitions
 Sreg0.clk = CLK;

State_diagram Sreg0


State S1:

    q1=1;
    q2=0;
    q3=0;
    x=x+1;
     IF ('x<1000') THEN
    S1
     ELSE  IF ('x=1000') THEN
        S2;


State S2:

    q1=0;
    q2=1;
    q3=0;
    x=x+1;
     IF ('x<2000') THEN
    S2
     ELSE  IF ('x=2000') THEN
        S3;


State S3:

    q1=0;
    q2=0;
    q3=1;
    x=x+1;
     IF ('x<3000') THEN
    S3
     ELSE  IF ('x=3000') THEN
        S1 WITH
     x=1;
     ENDWITH;

" end of state machine - Sreg0


end delay


Article: 20248
Subject: FPGA x DPGA x TSFPGA
From: anoriaki@comp.ufscar.br
Date: Wed, 02 Feb 2000 16:20:36 GMT
Links: << >>  << T >>  << A >>
Hi people,

    I'm looking for some informations about FPGA, DPGA and TSFPGA.
    If someone could help me, mail to: anoriaki@comp.ufscar.br

thanks,

Nori.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 20249
Subject: Re: Tools and how little guy is treated (was Xilinx Tools)
From: richard@XYradix-design.co.uk (Richard Dungan)
Date: Wed, 02 Feb 2000 17:55:42 +0000
Links: << >>  << T >>  << A >>
"Keith Jasinski, Jr." <jasinski@mortara.com> wrote:

>Something these FPGA companies (who I know monitor this list) should make a
>point of remembering that those of use that work at small companies now,
>won't ALWAYS be working at small companies (either because our small
>companies go big time or we go to another larger company).  I, for one, will
>remember which companies treated me well and which ones didn't.

Me too. For my own part as a one man business I think Xilinx are generally
better than average. The support is generally good and (running Foundation Base
Express) I think the software is good value for money.

I didn't see the start of the thread but there are said to be ways of getting
discounts on software from Xilinx, for example by taking part in their
consultant programs, or dropping heavy hints about the volumes of the final
sales of the design.

One of the problems that the companies who provide poor support for small
businesses face, is that they do not know who the final customer might be. For
example my current design will ultimately be used by a major UK telecoms
operator.

And on the next project I'll happily use Xilinx but there will be a good deal
more soul-searching regarding TI DSPs. :(

Richard

------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
      Spamtrapped: Remove the XY
---------------------------------------


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