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Messages from 21575

Article: 21575
Subject: Re: FPGA & single point failure
From: John Larkin <jjlarkin@highlandSnipSniptechnology.com>
Date: Sat, 25 Mar 2000 10:11:56 -0800
Links: << >>  << T >>  << A >>
On Sat, 25 Mar 2000 10:23:43 GMT, Tom Burgess <tom.burgess@home.com>
wrote:

|Seeing the lack of responses, I can guess that many were mystified by your
|use of the unfamiliar terms "clue point" and "redound". The context is
|not sufficient to make them clear, to me at least. What's disconcerting
|is that the rest of the message appears to be mostly coherent English.
|
|regards, tom
|
|EDM wrote:
|> 
|> I've got a problem with a space mission payload system.  I want to use a
|> FPGA as a clue point of a payload electronic unit. Can anybody clarify me
|> how do I manage the concept of "single point failure tolerant" in the
|> system, If I cannot redound the board where this FPGA is included. Do I
|> redound the FPGA itself inside the board? Is it possible? And is it normally
|> foreseen? Or is there anything else that I have to take into account? Or
|> other good solutions that you can suggest me?
|> 
|> Thanks for any advice and suggestion you can give me
|> 
|> --
|> 
|> edemarchi@hotmail.com

Tom,

I love the verb 'redound'; it'll make an excellent post to one of my
English-usage newsgroups.

If a system node is not a 'clue point', is it clueless?

(no derision intended, just having fun)

John

Article: 21576
Subject: Re: Clock disabling
From: z80@ds2.com (Peter)
Date: Sat, 25 Mar 2000 19:43:17 +0000
Links: << >>  << T >>  << A >>

Gating clocks is dodgy, because the current Xilinx parts are very fast
and if building e.g. a counter or a shift register you really need to
use the global clock nets to make it work. With old slow parts this
wasn't a problem, I think because the D-type ck->q propagation delay
was longer than the local interconnect delay, so local interconnects
could be used for e.g. the clock net of a shift reg.

Years ago I did a few years of ASIC prototyping with the XC3000
devices, and I was gating clocks all over the place - to get low
power. An ASIC has probably got a 3x to 10x dynamic Icc advantage over
an FPGA anyway, and gating clocks can give you another very big
factor. 

I used the old Viewlogic 4 tools, with APR place/route, and I used the
SC=1 and L attributes on any gated clock nets. Those tools would use
this to force the gated clocks onto a longline and this worked fine.
But XACT6 (which used PPR) broke this behaviour and unsuprisingly the
designs no longer worked even in the old slow parts; I had to to the
FPGA prototyping with clock gating and unit-delay simulation (which
always worked of course:)) but actually use the global clock nets in
the FPGA, and then edit the schematic back and generate a new netlist
(with gates clocks) to give to the ASIC company.

Presumably with hand FPGA layout you can do what you need, using local
interconnect and cascade e.g. shift reg stages so that the clock net
travels in the opposite direction to the shifting (an old trick), but
then you lose much of the rapid ASIC prototyping which FPGAs give you.

I don't know how people these days use FPGAs for ASIC prototyping,
without taking a huge power hit. For PC cards this doesn't matter but
anything battery powered is a real problem. Maybe they use antifuse
FPGAs for such projects.

>Hi all
>I am working on a design which may be used in two products, one of which
>won't need some functions of the design. I don't want to have 2 designs
>(we won't make 2 ASICs).
>I was wondering if it was possible to have 2 clock domains (same
>frequency) with the possibility to turn one of them off to reduce power
>consumption (this would be done by pulling a pin high or low for
>example)


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 21577
Subject: Anyone using Philips (now Xilinx) Coolrunner PLDs?
From: z80@ds2.com (Peter)
Date: Sat, 25 Mar 2000 19:43:18 +0000
Links: << >>  << T >>  << A >>

I designed the P3Z22V10 into a product about a year ago, now Xilinx
have bought that part of Philips, and I will soon have to buy some
production quantities. It is a product with a market life of maybe 10
years.

I just wonder if everything is still OK, lead times are OK, no parts
have been dropped, etc. A disti probably won't tell me of problems.


Peter.
--
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but remove the X and the Y.
Please do NOT copy usenet posts to email - it is NOT necessary.
Article: 21578
Subject: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
From: "david garnett" <dave.garnett@metapurple.co.uk>
Date: Sat, 25 Mar 2000 19:57:19 -0000
Links: << >>  << T >>  << A >>
We have the PZ128C in a design and are having extreme difficulties. The
problem is that Philips seem to have stopped making it, or at least declared
it obsolete so that Philips dealers no longer have any stock, whereas Xilinx
don't seem to have ramped up yet ... sigh!
dave

Peter <z80@ds2.com> wrote in message
news:7r4qdsspfn4tf4hm5ck24v77tp5mookl2q@4ax.com...
>
> I designed the P3Z22V10 into a product about a year ago, now Xilinx
> have bought that part of Philips, and I will soon have to buy some
> production quantities. It is a product with a market life of maybe 10
> years.
>
> I just wonder if everything is still OK, lead times are OK, no parts
> have been dropped, etc. A disti probably won't tell me of problems.
>
>
> Peter.
> --
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.


Article: 21579
Subject: Re: FPGA openness
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Sat, 25 Mar 2000 20:07:33 GMT
Links: << >>  << T >>  << A >>
On Fri, 24 Mar 2000 18:55:46 GMT, eml@riverside-machines.com.NOSPAM
wrote:

>It's not my company - they're just currently paying my bills. They're
>good employers, cubicles notwithstanding, pay well, they're
>leading-edge (3G wireless), and they've got an IPO on the way. The
>problem is simply that it's very difficult to find *any* engineers in
>the UK at the moment. If anyone wants to relocate to Cambridge mail

Evan, I would like to re-qualify this ever so "slightly":

"It's very difficult to find any _good_ engineers in the UK"

The emphasis is on good as I can always find you average "grind-away"
guys that will move "for a few dollars more". Smart engineers are
already working out that have a significantly higher "worth" than
previously many of the giants of Electronic Engineering employment
would have them believe. Good engineers can be found but will only be
prepared to work for you if you are willing to offer the following:

Attractive workplace
Appropriate tools for the job
Responsibility and direct control ("make a difference" culture)
Challenge and variety in the job
Sensible salary
Bonuses/stock
Possibly even company cars (where required) or additional perks.

>me, and I'll give you details. They've got positions in FPGA/ASIC,
>DSP, and algorithm development.

Just out of interest, what DO they pay Evan?

Being a small (in number) organisation, Saros does not have to suffer
the trauma of recruiting that often. However, it just so happens that
we now have a new opening for an additional Internal
Application/Support Engineer to be based in our Wallingford Offices.
So if you are reading this and may be interested, contact me on my
work mail:

stuart "at" saros "dot" co "dot" uk

Cheers
Stuart
An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk
Article: 21580
Subject: DLL
From: Anurag Tiwari <atiwari@cs.wright.edu>
Date: Sat, 25 Mar 2000 18:32:16 -0500
Links: << >>  << T >>  << A >>

Does anybody know how the DLL in Xilinx Virtex Series of FPGA could
multiplay the clock i.e double and four times the original clk frequency

--AT

Article: 21581
Subject: Re: DLL
From: Peter Alfke <palfke@earthlink.net>
Date: Sat, 25 Mar 2000 23:40:39 GMT
Links: << >>  << T >>  << A >>
The DLL is really two cascaded delay "lines", with identical control.
So, by utilizing the mid-point, one can double the frequency. Quadrupling
requires two DLLs.
This is a highly oversimplified description, but I think it serves the
purpose.

Peter Alfke, Xilinx Applications
===================
Anurag Tiwari wrote:

> Does anybody know how the DLL in Xilinx Virtex Series of FPGA could
> multiplay the clock i.e double and four times the original clk frequency
>
> --AT

Article: 21582
Subject: FPGA chip for PalmPilot
From: Oliver King-Smith <oliverks@tescina.com>
Date: Sun, 26 Mar 2000 01:45:14 GMT
Links: << >>  << T >>  << A >>
I am looking for someone who can help me design an FPGA.  I have never
done anything like this before, and I want to get a part made for
interfacing some electronics to a type of PalmPilot called the Visor
(www.handspring.com).

The Visor interface is very close to a PCMCIA slot.  If you would be
interested in a short term contract doing this please contact me
directly at

Oliver King-Smith
Tescina, Inc.
510-713-8001
oliverks@tescina.com
Article: 21583
Subject: Re: FPGA openness
From: "Robert Carney" <bobcarney@worldnet.att.net>
Date: Sun, 26 Mar 2000 02:06:45 GMT
Links: << >>  << T >>  << A >>

Rickman <spamgoeshere4@yahoo.com> wrote in message
news:38DBF65C.3CFB958A@yahoo.com...
.....snip
>
> As I see it, that is the main reason that a user buys a Xilinx
toolset.
> You get support directly from the source. I looked at buying
Neocad
> software years ago and one of the many reasons that I didn't
was because
> they were "third party" and would never be able to supply a
complete
> support package. They never made any indication that Xilinx
would
> support their products in any way. In fact they said that
Xilinx
> initially was very uncooperative in providing any info on the
bitstream
> or chip designs. But they worked around that and Xilinx
ultimately
> decided that it was in their own interests to provide
information to
> Neocad, very much like what Greg is asking for. Information
without
> obligation for support.
>

Didn't they buy Neocad shortly after that?


Article: 21584
Subject: Re: No- FPGA openness
From: "Kelly Hall" <hall@iname.com>
Date: Sat, 25 Mar 2000 18:09:09 -0800
Links: << >>  << T >>  << A >>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

"Greg Alexander" <galexand@sietch.bloomington.in.us> wrote in message
news:8be3d8$npn$3@jetsam.uits.indiana.edu...
> See, here's an application of eXtreme Programming: the productivity
> increases MORE THAN LINEARLY as your compile/link time decreases
> linearly.

I don't think the function is linear; in fact, I doubt it's even
monotonic.  Once the compile/link time gets below a certain point,
there's a temptation for the brain to never get a chance to stop and
think about what's going on.  This leads to the phenomenon called
'random walk programming' where the programmer starts fiddling with
code until "it works" without taking the time to understand what's
making the thing fail in the first place.  I saw a lot of this
teaching C...  I'm sure the whole thing is highly
programmer-dependent.  Personally, I spend a lot more time running
lint than I do running the linker, or especially the debugger.

Kelly


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Article: 21585
Subject: Re: FPGA & single point failure
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 03:23:57 GMT
Links: << >>  << T >>  << A >>
In article <38DC94F7.D2D0B8D6@home.com>, Tom Burgess wrote:
>Seeing the lack of responses, I can guess that many were mystified by your
>use of the unfamiliar terms "clue point" and "redound". The context is
>not sufficient to make them clear, to me at least. What's disconcerting
>is that the rest of the message appears to be mostly coherent English.

My guess is that "clue point" = "key point" -- simple mental error or
perhaps somehow equivalent term (beats me).  And "redound" is probably a
synonym for "make redundant," perhaps the word even implies some special
method (such as having 3 redundant systems and a comparator).  I would
guess that nobody replied because nobody really knows what type of
standards he needs in terms of reliability so nobody is confident to say
"don't worry about it, just assume the FPGA won't break" or etc.  I would
be very surprised if very many people who have the time to read Usenet are
familiar enough with REALLY critical apps to have much to say to such a
general question.

>EDM wrote:
>> 
>> I've got a problem with a space mission payload system.  I want to use a
>> FPGA as a clue point of a payload electronic unit. Can anybody clarify me
>> how do I manage the concept of "single point failure tolerant" in the
>> system, If I cannot redound the board where this FPGA is included. Do I
>> redound the FPGA itself inside the board? Is it possible? And is it normally
>> foreseen? Or is there anything else that I have to take into account? Or
>> other good solutions that you can suggest me?
>> 
>> Thanks for any advice and suggestion you can give me
>> 
>> --
>> 
>> edemarchi@hotmail.com
Article: 21586
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 03:29:24 GMT
Links: << >>  << T >>  << A >>
In article <8bg59t$474$1@agate.berkeley.edu>, Nicholas C. Weaver wrote:
>	I've come to the conclusion that you are a flamer and a troll,
>your posts are becoming more ridiculous and deliberately inflamative,
>george.

I assure you that I am not a troll.  I came here to get information and
I've stuck around only to correct people when they've obviously
misunderstood my claims.  I am operating on the obviously flawed
assumption that the world would be better if they understood me even
though it's quite clear by now that many of them are too stupid to even
realize that they aren't seeing what I'm typing.

>	You have asked for the advice of the experts, and ignored the
>advice.  

No, I didn't ask for the advice they're giving me.  I asked how to find
information and they told me I didn't need it.

>	You accuse people of not "bothering to understand what's going
>on", when those in this group are intimatly concerned with how the
>tools operate and the architectures being targeted.

No they aren't, they can't be, because they don't know how the tools work,
nor do they have sourcecode to the tools.  Many of them have explicitly
said that they are glad they don't have to worry about what goes on under
the hood.  Obviously many of them are concerned with what goes on under
the hood but they are not attacking me.

>	If I send you a free copy of the student edition Xilinx tools,
>will you go away?  We have a couple of textbook evaluation copies with
>CDs in the back, sitting in our office.  I could also toss you a copy
>of the Altera student tools, same thing there.

If I can convert XDL to bitstream for the XC4005XL using only those tools
and DOS, certainly.

>	To everyone else, let us no longer respond to this thread of
>george's.  Ignore it, and it should go away.

By intentionally calling me george twice when it's clear that my name is
Greg, you are being intentionally inflamatory, asshole.
Article: 21587
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 03:44:18 GMT
Links: << >>  << T >>  << A >>
In article <8bg9eb$f4k$1@info3.fnal.gov>, Don Husby wrote:
>galexand@sietch.bloomington.in.us (Greg Alexander) wrote:
>> In article <8bg2qr$cqp$1@info3.fnal.gov>, Don Husby wrote:
>
>> >galexand@sietch.bloomington.in.us (Greg Alexander) wrote:
>> Getting rid of the bugs is small compared to the peace of mind of
>> understanding the software.
>
>Right, I got it from your first few posts.  This is a spiritual thing
>for you.  Nothing is stopping you from understanding.  I'm just saying
>you'd get a little more credibilty on that point if you took the time
>to do some of that unsderstanding before shooting your mouth off.

I don't mind the time to understand -- I'm a bit embarrassed that I've
said so much before reading the second half of the XC4005XL datasheet, for
example -- I mind the artificial hurdles to understanding.  I don't have any
intention to buy software I don't want just to try to understand it in a
very inefficient fashion (by using it, compared to reading its source or
thinking about it from the author's viewpoint by being the author).  If
someone had said "here's this document, you can download it here -- don't
bother posting again until you've read it" or even "there's a great book
with the information you're looking for, go away until you've read it"
(which was the information necessary to program the chip, not just to
understand how other people say their programmers work -- a well-worded
English description of the code is invaluable, but it is no substitute
for the code, especially from a practical viewpoint), it would be a
totally different matter and I would agree much more thoroughly.  I'm
complaining about intentional secrecy interfering with my understanding.

<snip>
>> I have no clue about FPGA, and at one time, neither did you.
>
>When I had no clue about FPGAs, I had the sense not to go spouting
>off about it.

I have plenty of clue about learning and I know it's not going to happen
very well when there is secrecy.

>> That's why she's your ex-wife.  Your judging of activities by OTHER people
>> as complete wastes of time is stupid.
>
>Stupid? That sounds pretty judgemental.  Pot, kettle, black.
>I reserve the right to make any judgements I want.  I stick by them.
>She was a kook.  She did hard time in the nut house to prove it.
>I thank my lucky stars that she's my ex wife.

If you think that a couple suits saying "she's a kook" is any more valid
than you saying "she's a kook" then she's glad she's not your wife anymore
either.  By saying that the pot is calling the kettle black, you are
admitting to being a kettle.

>> I don't mind if you don't have any
>> intention to do what I'm doing, but I don't see why you mind that I do it.
>
>I don't mind.  But I have an opinion.  Is this a problem?
>
>> Your ex-wife may have an idea there, working as a janitor.
>I don't think she'd agree with that.

Oh well.  Are you judging her for being a slave as a janitor or just for  
beign a janitor?  If it's the former then I apologize for my judgement.

>> >your 13 Gigabyte disk is running out of space, you can probably
>> >afford to delete your Captain Kirk .gif files.  Use the software.
>> 
>> I don't know what the fuck that's all about, I assume you're just
>> comparing me too much to your ex-wife, since none of that has any
>> basis in any reasonable argument.
>
>Yes you do.  It's an ad-hominem attack for the purpose of pointing out
>how silly your disk-space worries are.  That you chose to respond in
>kind *without* apparent purpose allows me you use the "pot,kettle,black"
>rule again.

Does it seem odd to you that I'd rather take on a hassle I'd enjoy
(developing for FPGAs even at a primitive level) than one I would not
enjoy (clearing out space on my HDD, trying to install the software
without windows, then trying to run the software without windows, then
trying to understand how the software works) even though the latter more
painful hassle may take much less time than the longer joyous hassle?
Would you rather an hour of sex or 5 minutes under the whip? (of course,
if you're into BD/SM then the question needs to be rephrased)

>> >Find out what it can and cannot do.  Get back to us in a couple of
>> >weeks and maybe we can have an intelligent discussion about FPGAs.
>> 
>> No we can't because I bet pennies to dollars (you're the high-paid
>> professional) that you don't know shit about what really goes on inside
>> that software because all you're concerned about is the fact that it
>> works.
>
>I'll stack my knowledge of the FPGA and the software internals against
>yours any day.  You'll lose your pennies, but you might learn something.
>Let's do lunch.

Where are you located?  If you'll be in Bloomington Indiana, sure.
Article: 21588
Subject: Re: FPGA openness
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 25 Mar 2000 22:58:41 -0500
Links: << >>  << T >>  << A >>
Gary Watson wrote:
> I don't want to leave the impression that I'm still torqued at Xilinx, in
> fact, to the contrary, they seem to be making all the right noises.  A
> Xilinx FAE is coming to see me next week, and I'm going to go ahead and
> order the tools that I need.  It's just a shame the $100 package wasn't
> around back in 1988.

I understand your frustration. Xilinx has been run in somewhat different
ways over the years. Quite often I have wondered if the people running
it (or not running it as it sometimes appears from the lack of internal
organization or cooperation would indicate) really understand their
customers. 

The $100 is really more of a marketing gimick than a truly useful
evaluation method. For some people this size limitation of this package
is not a problem, but for most, likely such as yourself, they can't do
anything useful in a 10K part (or what ever the largest part is that is
supported by this package). 

As it happened, I got a similar package from Lucent which supports up to
a 30 K gate part. This was just the part that I wanted to use. So I was
set. But I expect that most of the time people basically waste a bit of
time playing with the cheap package and then have to buy the expensive
package to do their real work. The time they spent costs more than the
full package so that they likely should have just bought the thing in
the first place and been working on the full design from the start. 

But I guess you have to come up the learning curve one way or the other
and it is hard to make that time useful to your project. Often the first
project you do ends up as a poor job, so it should be one that does not
tax the parts or the tools. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21589
Subject: Re: No- FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 04:01:56 GMT
Links: << >>  << T >>  << A >>
In article <8bg4gl$daa$1@info3.fnal.gov>, Don Husby wrote:
>galexand@sietch.bloomington.in.us (Greg Alexander) wrote:
>> There are a lot of pompous asses too.  People who stare at disbelief at
>> every newbie constantly insisting that the problems the professionals
>> tackle with on a daily basis are far too difficult for a newbie to even
>> understand are pompous asses and there's no other way around it, no
>> matter how much hardware they've designed.
>
>Usually, comp.arch.fpga is helpful to newbies.  If you want to have a
>sensible discussion about hacking FPGAs, there are many here who could
>participate.  There are many of us who have hacked at the FPGA tools
>and can speak from experience.  You are not one of them.

I don't want to hack at tools I want to write my own.  That's in my first
post to this newsgroup.  I enjoy tackling non-trivial problems when
creating, but I find reverse-engineering tedious.

>We stare at you in disbeleif because it's warranted.  That you seem to
>think you understand the problem without ever having done an FPGA design
>is a measure of how clueless you really are.  "There's no other way around it."
>This is not pomposity.  This is reality.  Pomposity is you taking
>the position that we are the ones who are clueless.

I certainly do not understand the problem, I understand that there are
ARTIFICIAL obstacles to my understanding the problem erected by Xilinx et
al.
	I do not think you are clueless about using the tools and many of
you even know much about how the tools work but anyone who thinks my time
is better spent reverse-engineering tools rather than reading
documentation is at the very least clueless about me.

I have perceived people to be attacking here and I have been harsh in
my words and for that I apologize -- it's obvious in hindsight that I've
only encouraged further attacks.

>>         Everyone here takes the title professional too seriously.  In the
>> software movement we've learned ....
>
>You guys don't own guns do you?  At least we professionals don't take ourselves
>so seriously as to call ourselves a "movement".

Maybe you should.  Every time a large group of people cooperate towards
a common goal they have all sorts of effects.  Much of the free software
movement is cooperating towards a goal of making an OS that we can use
(the original GNU goal, as I understand it).  If they had just made that
OS and shared it they would have inadvertantly affected the whole world by
showing that an open and sharing approach works and causing people to
question the way they think about all forms of software development and in
fact all information flow.  Instead, they're very concious of the fact
that they're changing the way people think about programming, they are
aware of teh fact that they are a movement and changing the world and are
cautious in doing such.
	By being secretive and developing a working lifestyle centered
around reverse-engineering or second-guessing everything that your business
is involved in that wasn't developed in house and by releasing products
that cause others to behave similarly you are also having an affect
on the entire world, you are also a movement, but you don't even know it.
Maybe since it's already standard practice you guys think of it more as
just standing still.
	I do not own a handgun and although some public figures involved
with free software are gun nuts, I do not think any one meaningful would
condone violence to support our movement.  Most (including me) don't even
condone copyright violation to support our movement.
Article: 21590
Subject: Re: FPGA openness
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 25 Mar 2000 23:03:18 -0500
Links: << >>  << T >>  << A >>
Robert Carney wrote:
> 
> Rickman <spamgoeshere4@yahoo.com> wrote in message
> news:38DBF65C.3CFB958A@yahoo.com...
> .....snip
> >
> > As I see it, that is the main reason that a user buys a Xilinx
> toolset.
> > You get support directly from the source. I looked at buying
> Neocad
> > software years ago and one of the many reasons that I didn't
> was because
> > they were "third party" and would never be able to supply a
> complete
> > support package. They never made any indication that Xilinx
> would
> > support their products in any way. In fact they said that
> Xilinx
> > initially was very uncooperative in providing any info on the
> bitstream
> > or chip designs. But they worked around that and Xilinx
> ultimately
> > decided that it was in their own interests to provide
> information to
> > Neocad, very much like what Greg is asking for. Information
> without
> > obligation for support.
> >
> 
> Didn't they buy Neocad shortly after that?

Xilinx did buy Neocad, but it was some years after they started shipping
product. But my point was that when Xilinx decided it was in their best
interest, they provided the support that Neocad needed and that this did
not obligate them to provide any additional support to the end users. 

Also after Xilinx did buy Neocad, they spent literally years reworking
the software to assimilate it into the Xilinx tools. A large part of
this was likely to be sure that they could provide the needed support
for their customers. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21591
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 04:05:19 GMT
Links: << >>  << T >>  << A >>
I want to get this in before anyone else does: I apologize for getting
frustrated.  I hope that I did not start the rude parts of this
conversation, but it's obvious that in this letter I was just responding
in kind and only inviting more flames.  I am only human and as I get
frustrated I sometimes start to act like an asshole.  I hope you can
forgive me for when I do such and if I'm ever doing such please read it as
frustration rather than as an honest dislike or disrespect for any of you.
I will try to do the same.

In article <8bk06k$2h8$2@jetsam.uits.indiana.edu>, Greg Alexander wrote:
>In article <8bg59t$474$1@agate.berkeley.edu>, Nicholas C. Weaver wrote:
>>	I've come to the conclusion that you are a flamer and a troll,
>>your posts are becoming more ridiculous and deliberately inflamative,
>>george.
>
>I assure you that I am not a troll.  I came here to get information and
>I've stuck around only to correct people when they've obviously
>misunderstood my claims.  I am operating on the obviously flawed
>assumption that the world would be better if they understood me even
>though it's quite clear by now that many of them are too stupid to even
>realize that they aren't seeing what I'm typing.
>
>>	You have asked for the advice of the experts, and ignored the
>>advice.  
>
>No, I didn't ask for the advice they're giving me.  I asked how to find
>information and they told me I didn't need it.
>
>>	You accuse people of not "bothering to understand what's going
>>on", when those in this group are intimatly concerned with how the
>>tools operate and the architectures being targeted.
>
>No they aren't, they can't be, because they don't know how the tools work,
>nor do they have sourcecode to the tools.  Many of them have explicitly
>said that they are glad they don't have to worry about what goes on under
>the hood.  Obviously many of them are concerned with what goes on under
>the hood but they are not attacking me.
>
>>	If I send you a free copy of the student edition Xilinx tools,
>>will you go away?  We have a couple of textbook evaluation copies with
>>CDs in the back, sitting in our office.  I could also toss you a copy
>>of the Altera student tools, same thing there.
>
>If I can convert XDL to bitstream for the XC4005XL using only those tools
>and DOS, certainly.
>
>>	To everyone else, let us no longer respond to this thread of
>>george's.  Ignore it, and it should go away.
>
>By intentionally calling me george twice when it's clear that my name is
>Greg, you are being intentionally inflamatory, asshole.
Article: 21592
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 04:10:53 GMT
Links: << >>  << T >>  << A >>
In article <8bg54n$q1m$1@bcrkh13.ca.nortel.com>, Andrew Brown wrote:
>"Greg Alexander" <galexand@sietch.bloomington.in.us> wrote in message
>news:8bfvke$rkd$1@jetsam.uits.indiana.edu...
>> In article <38DB7BC3.889F0994@ids.net>, Ray Andraka wrote:
>> >Not at all.  It's just that I think it makes more sense to first work
>with
>> >what is out there before condemning it.
>
>To be fair - i haven't seen him condem it.  Sure, he thinks it's crap and
>won't install it - but i reckon thats more of a preference for him than a
>bitch at the tools.  I agree he'd learn a lot about the architecture by
>doing it but there's nothing wrong with learning the hard way if thats what
>he wants.
>
>Greg -
>
>As for FPGA vendors releasing specs for things they consider trade secrets -
>forget it.
>Sure, the competition MAY have cracked it already, but that doesn't mean
>that the vendors are going to make it easy for them (they may have missed
>something).  You wouldn't expect Intel to hand AMD the source code for the
>Xeon just because AMD have something compatable !  If they released the
>specs they would be telling us a lot more about the internal architecure of
>the chip than an API would say about the algorithms used in a software
>library.
>So, if your going to do this i'm afraid it's time to reverse engineer the
>bit-stream.  But be careful - and invalid bit stream can physically damage
>the chip, and that's going to cost you more than buying the software.

Thanks.  Larry Doolittle sent me a sample .XDL file and a quick browse
(assuming there's enough documentation for me to figure out the PIP lines)
makes it look liek that format is right enough that I'll drop the issue.
It's been reduced to just a practical problem of obtaining XDL->bitstream
software at low cost and getting it to run without Windows.  I'm still
annoyed but I think the technical aspect of this thread has been nicely
dealt with.  Thanks to all who suggested I look into XDL!

>> Think of how much time Xilinx would have saved you if they'd just
>> released bitstream specs. :)
>
>Actually it wouldn't save them time.  As a (commercial) user, i'd still
>expect Xilinx to produce the tools - even if they produce the specs.  So
>they have to publish more.

I was kidding about how much of this lengthy conversation would have been
avoided if the whole thing could have been stopped by someone saying "look
at datasheet 123 on Xilinx's site, it has the information you need." :)
Article: 21593
Subject: Re: FPGA openness
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 26 Mar 2000 04:11:48 GMT
Links: << >>  << T >>  << A >>
	I'm voilating my own rules here, but.  First, sorry about
messing up your name, a weird error on my part.

>>	You have asked for the advice of the experts, and ignored the
>>advice.  
>
>No, I didn't ask for the advice they're giving me.  I asked how to find
>information and they told me I didn't need it.

	No, more precisely, that the information you want is NOT a
good starting point for what you want to do, that it is simply asking
for a great deal of frustration and problems on your part.  Sometimes
the correct answer for "how do I do X" is "You don't want to do X".

>>	You accuse people of not "bothering to understand what's going
>>on", when those in this group are intimatly concerned with how the
>>tools operate and the architectures being targeted.
>
>No they aren't, they can't be, because they don't know how the tools work,
>nor do they have sourcecode to the tools.  Many of them have explicitly
>said that they are glad they don't have to worry about what goes on under
>the hood.  Obviously many of them are concerned with what goes on under
>the hood but they are not attacking me.

	You don't need to have the source code to understand a great
degree about what the tools are doing.  Do you need the RTL to
understand how the processor runs your code?  Do you need to
understand the physics of CMOS transistors?  When teaching, I have a
term for this: "Mindy Syndrome" (From the Animaniacs, the little girl
who goes "but why", "but why" in response to any answer to a question
she asks).

	Although intellectually interesting, the answers to such
questions do not further the task at hand.  Sometimes you have to
respect the abstractions available.  The bitfile is an abstraction,
except under extreem conditions, the user does not need to break, and
should not break that abstraction barrier.

	Also, the tools DO perform some tasks very well.  EG, given a
good placement, the automated routers can easily meet or exceed what a
human can do.  Thus, the time is better spent in understanding
behaviorally what the tools do, and understanding the targeted
architecture enough to know what is a good placement.

>If I can convert XDL to bitstream for the XC4005XL using only those tools
>and DOS, certainly.

	Where should I send it?  You may need to fire up a windows
emulator to run the installer.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 21594
Subject: Re: No- FPGA openness
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 25 Mar 2000 23:16:59 -0500
Links: << >>  << T >>  << A >>
Kelly Hall wrote:
> 
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA1
> 
> "Greg Alexander" <galexand@sietch.bloomington.in.us> wrote in message
> news:8be3d8$npn$3@jetsam.uits.indiana.edu...
> > See, here's an application of eXtreme Programming: the productivity
> > increases MORE THAN LINEARLY as your compile/link time decreases
> > linearly.
> 
> I don't think the function is linear; in fact, I doubt it's even
> monotonic.  Once the compile/link time gets below a certain point,
> there's a temptation for the brain to never get a chance to stop and
> think about what's going on.  This leads to the phenomenon called
> 'random walk programming' where the programmer starts fiddling with
> code until "it works" without taking the time to understand what's
> making the thing fail in the first place.  I saw a lot of this
> teaching C...  I'm sure the whole thing is highly
> programmer-dependent.  Personally, I spend a lot more time running
> lint than I do running the linker, or especially the debugger.
> 
> Kelly

I agree that speeding up the compile cycle will only gain efficiency to
a point, but we are a long way from that point. But you are right in
principal and I think the principal is much stronger with logic design.
It is very easy to produce some really bad hardware if you are not
careful. I have ended up doing some "random walk programming" when I did
not take the time to really understand a problem that seemed to be
simple. But even when I take a lot of time on logic, I still can produce
a real mess with a tough part. 

But right now a place and route of a mid sized to small part will take
half an hour on a current machine. Large parts can take a day or more.
Of course a lot of this depends on how well the part is placed by the
user, just ask Ray Andraka. So there is so much room for improvement
here that I don't think we will see the limits anytime soon. 

The other issue is that you really should not see many design errors in
your part by the time you have reached place and route. This is one way
that it is different from software compiles. Logic is mostly debugged in
simulation before you place and route the chip. Bugs are much, much
harder to find in a real chip in a real system. Harder to stimulate and
harder to see into. So you had better have had a very exhaustive
simulation done before you get to the chip. 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21595
Subject: Re: No- FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 04:32:22 GMT
Links: << >>  << T >>  << A >>
In article <8jeD4.47$s4.5170@news.pacbell.net>, Kelly Hall wrote:
>-----BEGIN PGP SIGNED MESSAGE-----
>Hash: SHA1
>
>"Greg Alexander" <galexand@sietch.bloomington.in.us> wrote in message
>news:8be3d8$npn$3@jetsam.uits.indiana.edu...
>> See, here's an application of eXtreme Programming: the productivity
>> increases MORE THAN LINEARLY as your compile/link time decreases
>> linearly.
>
>I don't think the function is linear; in fact, I doubt it's even
>monotonic.  Once the compile/link time gets below a certain point,
>there's a temptation for the brain to never get a chance to stop and
>think about what's going on.  This leads to the phenomenon called
>'random walk programming' where the programmer starts fiddling with
>code until "it works" without taking the time to understand what's
>making the thing fail in the first place.  I saw a lot of this
>teaching C...  I'm sure the whole thing is highly
>programmer-dependent.  Personally, I spend a lot more time running
>lint than I do running the linker, or especially the debugger.

I would guess that the fundamental assertions of eXtreme Programming (a
practice I cite with very little knowledge of) are true only for
experienced programmers.  Forth, for example, centers around testing your
code immediately after you write it so you can test each tiny module/etc.,
but at least people who support it would never support random walk
programming even though that is maybe how someone just learning the
language would use the same features.
	In other words, the features may be useful for random walk
programming also, but a fast compile time is useful for competent
programming.
Article: 21596
Subject: Re: FPGA openness
From: galexand@sietch.bloomington.in.us (Greg Alexander)
Date: 26 Mar 2000 04:55:37 GMT
Links: << >>  << T >>  << A >>
In article <38DBF184.C9FEFA10@yahoo.com>, Rickman wrote:
>The only companies that don't charge for their tools are the ones that
>can't compete directly on an equal footing. They get their sales by
>being novel in some way, like Atmel. They have a hard time competing
>with Xilinx or Altera if you just look at the parts. There are a few
>niche applications which they do well, but for the most part if they did
>not give away their tools, they would not get many customers. 

*perks up*

In hopes that if the answer is no someone will tell me before I spend too
much more time reading their site:
	So Atmel tools are free and/or open source and/or there is enough
information for me to do what I want freely available?
Article: 21597
Subject: Re: FPGA openness
From: Ray Andraka <randraka@ids.net>
Date: Sun, 26 Mar 2000 06:31:45 GMT
Links: << >>  << T >>  << A >>


Rickman wrote:

> The $100 is really more of a marketing gimick than a truly useful
> evaluation method. For some people this size limitation of this package
> is not a problem, but for most, likely such as yourself, they can't do
> anything useful in a 10K part (or what ever the largest part is that is
> supported by this package).
> As it happened, I got a similar package from Lucent which supports up to
> a 30 K gate part. This was just the part that I wanted to use. So I was
> set. But I expect that most of the time people basically waste a bit of
> time playing with the cheap package and then have to buy the expensive
> package to do their real work. The time they spent costs more than the
> full package so that they likely should have just bought the thing in
> the first place and been working on the full design from the start.

The gate limited option is enough for you to throw some trial circuits in to
get an idea of how your circuit will perform and what kind of density you'll
get.  Big circuits are comprised of little circuits.  If your designs aren't
that way, they should be.  Also, the cheap seats look and feel like the
expensive ones, so there really isn't any loss there...you'll have to learn the
tool sooner or later anyway.  I think the cheap seats are an excellent way to
evaluate the parts for your application without committing to the big $ until
you are sure which direction you're going to go.  Even the high end FPGA seats
are a small fraction of the cost of nearly any development cycle, and a small
fraction of the equivalent tools needed to develop the same circuit in some
other technology.

>
>
> But I guess you have to come up the learning curve one way or the other
> and it is hard to make that time useful to your project. Often the first
> project you do ends up as a poor job, so it should be one that does not
> tax the parts or the tools.
>

definitely agree here.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21598
Subject: Re: FPGA openness
From: Ray Andraka <randraka@ids.net>
Date: Sun, 26 Mar 2000 06:47:12 GMT
Links: << >>  << T >>  << A >>
Naw, Atmel's bitstream is proprietary too.  They do give away the software
though, so that would avoid the money issue.  A number of years ago I wrote a
generator for a FIR filter in C that worked right above the bitstream in
atmel 6K.  That file was ascii, but without the secret decoder ring I don't
think I'd want to do it either (it was bad enough with information).

That said, the atmel 6K part is not one I'd recommend to a novice designer.
Its cell is not a LUT, rather it is a collection of gates set up more or less
as a half adder with a flip-flop on the sum output and with the carry output
inverted.  A few extra gates in the cell let it realize some but not all
additional 2 and 3 input boolean functions.  The routing is not real robust,
so to really take advantage of that array you wind up doing detailed place
and routing by hand, plus lots of iterations between entry and editor to do
DeMorgan permutations to make it fit better.  The bitstream is quite a bit
simpler than xilinx:  Each cell is 16 bits of configuration and there is not
much extra overhead for the routing, as most of it is nearest neighbor
connections set by the cell configurations.  Greg, you might have some fun
with that array, but you might also get rather frustrated/disappointed with
it if you want to do bit parallel math.  Some of the older papers on my
website deal with that architecture.  The 40K is a quite different
architecture.  It uses 4 input LUTs ala xilinx and altera for its cell, which
makes it considerably easier to use.  The cell is bigger, so it is not as
fast or as dense (smaller number of cells) as the 6K.  Both support partial
reconfiguration, as do their tools.  Atmel would be my first choice for an
application where I needed to do partial reconfiguration and did not require
fast carrys.

Greg Alexander wrote:

> In article <38DBF184.C9FEFA10@yahoo.com>, Rickman wrote:
> >The only companies that don't charge for their tools are the ones that
> >can't compete directly on an equal footing. They get their sales by
> >being novel in some way, like Atmel. They have a hard time competing
> >with Xilinx or Altera if you just look at the parts. There are a few
> >niche applications which they do well, but for the most part if they did
> >not give away their tools, they would not get many customers.
>
> *perks up*
>
> In hopes that if the answer is no someone will tell me before I spend too
> much more time reading their site:
>         So Atmel tools are free and/or open source and/or there is enough
> information for me to do what I want freely available?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21599
Subject: Re: FPGA openness
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 26 Mar 2000 01:47:15 -0500
Links: << >>  << T >>  << A >>
Greg Alexander wrote:
> 
> In article <38DBF184.C9FEFA10@yahoo.com>, Rickman wrote:
> >The only companies that don't charge for their tools are the ones that
> >can't compete directly on an equal footing. They get their sales by
> >being novel in some way, like Atmel. They have a hard time competing
> >with Xilinx or Altera if you just look at the parts. There are a few
> >niche applications which they do well, but for the most part if they did
> >not give away their tools, they would not get many customers.
> 
> *perks up*
> 
> In hopes that if the answer is no someone will tell me before I spend too
> much more time reading their site:
>         So Atmel tools are free and/or open source and/or there is enough
> information for me to do what I want freely available?

I am pretty sure that the tools are free. I have a copy I got a year to
so ago that I never installed. But I have no idea if they are open
source or not. I seriously doubt that they are giving away the source,
but they may give out the programming information. I think they are not
quite as secretive as some of the other companies. In fact, if you tell
them that you are interested in starting development of open source
tools, they may well offer some support. 

One area that Atmel may be very interested in supporting open source
tools in is finding ways to design partial configuration. The Atmel
parts are designed so that any rectangular area of the chip (at least on
the older 6000 series parts) can be reprogrammed on the fly (while the
rest of the chip is still operating). This is a capability that has been
very hard to make use of. The main problem is the way that routing tends
to be hard to keep inside of any given boundries. But this could be a
very useful feature if the right tools are developed. 

You could design chips with logic that changes to match the instructions
being executed as the instruction is decoded! Talk about code morphing! 


-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com


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