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Messages from 21325

Article: 21325
Subject: Employment
From: HR <rmccormiNOrmSPAM@harris.com.invalid>
Date: Thu, 16 Mar 2000 13:14:37 -0800
Links: << >>  << T >>  << A >>
Harris Corporation, a global communications company
providing its customers with product, system, and service
solutions that take their businesses to the next level.

Harris is focused in the wireless, broadcast, government
systems, and network support communications markets.

We have many openings for EE's with FPGA or ASIC desgin
experience.   Would you be interested in FL?  If so,
respond to this message indicating your interest.


* Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful
Article: 21326
Subject: Altera literature misleading
From: Steve Dewey <steve@s-dewey123.demon.co.uk>
Date: Thu, 16 Mar 2000 21:34:38 +0000
Links: << >>  << T >>  << A >>
I've commented here before about how closely you have to read Altera's
literature before you realise how few of their products actually have a
PLL in them. 

I have now come across another example of this. An initial reading of
the APEX publicity, e.g. on Altera's web site, seems calculated to
generate the impression that _ALL_ APEX 20K E series parts have full
support for 16 lines of LVDS input and 16 lines of LVDS output. I
thought that this would be just handy for my current application,
reading 8 lines of parallel data from a line-scan camera at 30 MHz. A
20K200E would do nicely, and my distributer gave me a price of 120 UKP
for a QFP, a package I know we can handle.

BUT it is only when I really drilled down into the 200 page datasheet
that I realised that LVDS I/O is only supported on the 20K300E and
above. 

Then to add insult to injury I looked for a 20K300E part and found that
it's not made yet, despite being listed in the printed "Altera News &
Views" newsletter. The nearest is a 20K400E, which is only available in
BGA and costs 480 UKP.

Am I being naive, or have other people been (nearly) caught out by this?
Does anyone else think that the literature is misleading ?


-- 
Steve Dewey
Remove 123 for mail.
Article: 21327
Subject: Re: Employment
From: HR <rmccormiNOrmSPAM@harris.com.invalid>
Date: Thu, 16 Mar 2000 13:39:44 -0800
Links: << >>  << T >>  << A >>
sfdgfdgfds


* Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping.  Smart is Beautiful
Article: 21328
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 16 Mar 2000 13:42:02 -0800
Links: << >>  << T >>  << A >>
As usual, Ray gave a nice explanation.

I disagree with his definition of a PLD.

In my book , what Ray calls PLD,  is a PAL (as invented by John Birkner at MMI)
with a programmable AND feeding a fixed OR.
Before that we had the unsuccessful PLA, where both AND and OR were programmable.
( If the AND is fixed and the OR programmable, it is a PROM.  :-)

Many of such PALs together on one chip are a CPLD ( formerly EPLD ).

That leaves the nice name PLD available to cover everything together, PALs, CPLDs
and FPGAs. Programmable-Logic Devices

But, as Humpty Dumpty said: I can name anything anyway I want...

Peter Alfke

Article: 21329
Subject: Re: Xilinx configuration current
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 16 Mar 2000 13:55:58 -0800
Links: << >>  << T >>  << A >>
Not quite:.
The FPGA does use its internal oscillator, the one that is later also used
as CCLK geerator, but it does *not* run an N-bit shift register, but rather
clears one frame at a time,i.e. many hundred bits at a time.  And the
second tim around, there is hardly any activity.
This is not where the device will spend a lot of current.
Note that bit-serial configuration is done in a similar way: shift in one
frame, then transfer the whole frame into its destination. No really long
shift register here either.

Peter Alfke,Xilinx Applications
====================================
Greg Neff wrote:

> I
>
> We have seen the same thing.  I suppose that during initialization and
> configuration you can think of the FPGA as an N-bit shift register,
> with N being the number of configuration bits.  While PROGRAM is low,
> the FPGA is repetitively clearing all of these configuration latches.
> The data sheet says that the clear process uses the internal
> oscillator, so the clear process must be synchronous.  If my hypothesis
> is correct, this would be the equivalent of clocking N latches at the
> CCLK rate, for the length of time that PROGRAM is low, plus the
> configuration time.  Clocking a few hundred thousand latches at the
> CCLK rate will definitely warm things up.
>
> It doesn't look like the FPGA will use an external CCLK while PROGRAM
> is low.  Otherwise, you could slow down CCLK (using slave serial mode
> as you said) to reduce current consumption during initialization.
>
> --
> Greg Neff
> VP Engineering
> *Microsym* Computers Inc.
> greg@guesswhichwordgoeshere.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 21330
Subject: Re: Xilinx configuration current
From: Greg Neff <gregneff@my-deja.com>
Date: Thu, 16 Mar 2000 22:31:03 GMT
Links: << >>  << T >>  << A >>
In article <8arh6g$5eu$1@nnrp1.deja.com>,
Greg Neff <gregneff@my-deja.com> wrote:
>
> We have seen the same thing. I suppose that during initialization and
> configuration you can think of the FPGA as an N-bit shift register,
> with N being the number of configuration bits. While PROGRAM is low,
> the FPGA is repetitively clearing all of these configuration latches.
> The data sheet says that the clear process uses the internal
> oscillator, so the clear process must be synchronous. If my hypothesis
> is correct, this would be the equivalent of clocking N latches at the
> CCLK rate, for the length of time that PROGRAM is low, plus the
> configuration time. Clocking a few hundred thousand latches at the
> CCLK rate will definitely warm things up.
>
> It doesn't look like the FPGA will use an external CCLK while PROGRAM
> is low. Otherwise, you could slow down CCLK (using slave serial mode
> as you said) to reduce current consumption during initialization.
>

I received the following e-mail from Peter Alfke, in reply to my post.
For some reason this was not posted as a reply on this thread.

(begin reply from Peter)
Not quite:.
The FPGA does use its internal oscillator, the one that is later also
used as CCLK geerator, but it does *not* run an N-bit shift register,
but rather clears one frame at a time,i.e. many hundred bits at a
time.  And the second tim around, there is hardly any activity. This is
not where the device will spend a lot of current. Note that bit-serial
configuration is done in a similar way: shift in one frame, then
transfer the whole frame into its destination. No really long shift
register here either.

Peter Alfke,Xilinx Applications
====================================
(end reply from Peter)

My hypothesis was obviously wrong, thanks to Peter for clearing that
up.  Unfortunately, Peter didn't shed any light on why there is a big
jump in ICC during configuration.

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21331
Subject: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
From: "HH" <javier_cardona@no.com>
Date: Thu, 16 Mar 2000 15:06:32 -0800
Links: << >>  << T >>  << A >>
I'm new to using newsgroups, but there must be a way to delete this kind of
messages...  Is there?

<Al-Sharptons-HairDresser@wwevn.net> wrote in message
news:DEE81E2D92A7E.jvxeveabln@yeerkdwxybf.edu...
> It's interesting to see how selective the black community can be when it
comes to what they get outraged about.
> -
> A couple of recent examples:
> -
> 1) A four-year-old white boy was dragged 4 miles to his death by a black
man when the automobile his mother was driving got car-jacked. The child was
attached to a seatbelt, hanging out the side of the car, clearly visible to
the perpetrator. The mother frantically pleaded for the life of her son to
no avail. Some other motorists watching this horror unveil eventually
subdued the driver. According to bystanders and police, the man was
completely remorseless.
> -
> Tell me something... How is this man any less of an animal than the 3
rednecks that dragged a black man to his death behind a pickup truck last
year? So, where is all the public outrage and cries of racism here?
> -
> 2) Yesterday, a black man went on a firing rampage, shooting 5 white
people - killing 2 and leaving 1 in critical condition with a bullet lodged
in his brain. When asked why he did it, he told a neighbor and police that
he just wanted to kill as many white people as he could. Again, completely
remorseless.
> -
> Again, where is all the public outrage and cries of racism here?
> -
> Whenever incidents of this type occur, there is a defining silence coming
from the black community. The double standard that seems to apply, suggests
that it's OK for black criminals to victimize whites but not the other way
around and has led to a well deserved lack of credibility for black's when
it comes to criminal justice.
> -
> Americans (law-abiding blacks and whites alike) have finally decided not
to allow this double standard and racial bias to infect the judicial system
any further and this was at the rudiment of the judge's decision to move the
Diallo trial out of The Bronx.
> -
> And since no discussion on this subject would be complete without a
comment on the Diallo verdict;
> -
> For the record, I didn't agree with this verdict. At a minimum, I think
these cops should have been charged with extreme reckless indifference to
human life and they should have been punished.
> -
> This was not murder however...  It was incompetence... If these cops set
out to murder this guy, then would have done it quietly in a back alley or
other such place and they would have quietly gotten away with it.
> -
> The real culprit here is the culture of young, black, African American
males, which engender an atmosphere of fear and lawlessness wherever they
congregate!
> -
> These neighborhoods to which the NYPD Street Crimes Unit are assigned, are
some of the most dangerous in New York City. Kids pull handguns on cops all
the time and many policemen have been shot, killed and maimed.
> -&
> In this highly charged, hair-trigger environment, no cop is going to risk
his or her life if he or she believes someone is about to pull out a gun.
> -
> No degree of sensitivity training, weapons regulations, political
pressure, threats, or other feel-good expedients is going to change a thing
until the black community starts to take responsibility for their children
and their communities.
> -
> In a strange sort of way, one might consider the final outcome of this
trial payback for the O.J. verdict.
> -
> -
> -
> -
> -
> -
> -
>
............................................................................
.........................................
> The following is an encoded message to the Tri-Lateral Commission:
>
............................................................................
.........................................
>
> O vfuzpvq mxs y ieez beo esbnkr esew
> nisblo pyi ekjme dlhiu
> xr ff es slslr dtdmp
> czfh lasr ejfe eke
> myliit ply eunfelb llrtl rb
> npmcfjy tiis lkpb jrdc o oeroen debu
> icrd ep ciny yk lkrk esimk
> ncg pmlfb mwox vdo
> ikd kvfgzb a cpki cm
> gyd sbi lb sj rlij
> dhse eaf zep isfl oy yg
> slm ixz gubr rydk
> vk qm bieiq issrmw ldi kr
> lut ptb pleptq elos.
>
> Sommoh pko fnonk sbcbw tpzri geci
> fs kare eefl a bq eik bpso
> cttc fjhi zmno eebpn
> iefrl kmerx rseab ell plklx qsdp
> cdgs rup dku jrq fc vo
> lnlaj lujlh esg lckpkor hevsop uutrr
> crwas ulas kekk tpfr jabj
> dctfbp mnofea erbere utkp ddb slnf
> gyfppb bjce dr a fre blit
> helxdee emsbi fmen pxjp
> ryfnbf fpk esxb nneag.
>
> Ejabo cvecfim kopfmpc kfs zrf rieww
> nymee fsajui oxuf yneef
> eesebl dpl sxzmgq ks
> lgfsr cegnv lkbcac hdgj yiukf con?
>
> Fdnl rk szg jk noie!
>
> Pnti cpdlz iinls mlepor elpyi eimud
> tico foim dcxaeo mtp?
>
> Zzb rni gelm grs ob!
>
> Wore prk ir o rm hhla mw?
>
> Jblj rccuenm ymxqk aldiyo mefrscn kb?
>
> Cozge vkpg stlo cteml?
>
>
>
>


Article: 21332
Subject: Re: ,,..SAY A PRAYER FOR THE INNOCENT VICTIMS OF BLACK VIOLENCE AND LAWLESSNESS!!..
From: Zoltan Kocsi <root@127.0.0.1>
Date: 17 Mar 2000 11:04:22 +1100
Links: << >>  << T >>  << A >>
"HH" <javier_cardona@no.com> writes:

> I'm new to using newsgroups, but there must be a way to delete this kind of
> messages...  Is there?

Not quoting the whole junk in your message seems to be a fairly good start ...

[ above mentioned junk deleted ]

Zoltan

-- 
+------------------------------------------------------------------+
| ** To reach me write to zoltan in the domain of bendor com au ** |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 21333
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: rk <stellare@nospam.erols.com>
Date: Thu, 16 Mar 2000 21:00:48 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> As usual, Ray gave a nice explanation.
>
> I disagree with his definition of a PLD.
>
> In my book , what Ray calls PLD,  is a PAL (as invented by John Birkner at MMI)
> with a programmable AND feeding a fixed OR.
> Before that we had the unsuccessful PLA, where both AND and OR were programmable.
> ( If the AND is fixed and the OR programmable, it is a PROM.  :-)

I agree with your definition of PAL as having a programmable AND plane and a fixed OR
plane.

I am not entirely in agreement with your term "unsuccessful" for PLA; I used them
back in the mid-'80s and it's been running continously since '89 and just keeps on
ticking [knock on wood].  I would have to find some very old notes to see if it was
yours [AMD] or Signetics and am pretty sure it was one of the two [82S100].

Perhaps it was not a commercial success but for a part that never gave me any trouble
and keeps on ticking I would call that a success. :-)

=========================

> Many of such PALs together on one chip are a CPLD ( formerly EPLD ).
>
> That leaves the nice name PLD available to cover everything together, PALs, CPLDs
> and FPGAs. Programmable-Logic Devices

And a variety of other devices, too.  One of my favorites was the AMD29CPL154.  Also,
having used PROM to make logic [fixed AND, programmable OR] we might wish to call
that a programmable logic device, also.  The 27S29 comes to mind, as the same era as
the 82S100.

==========================

> But, as Humpty Dumpty said: I can name anything anyway I want...

As Shakespeare says, "What's in a name?"

Have a good evening,

rk



Article: 21334
Subject: Re: Actel Design with A42MX36 Help
From: rk <stellare@nospam.erols.com>
Date: Thu, 16 Mar 2000 21:14:06 -0500
Links: << >>  << T >>  << A >>
Andrew batchelor wrote:

> Dear All
>
> I am a hardware engineer down in Rochester, and I am having great
> problems fitting a design to a 42MX36. The problem is that I would like
> my design to run at 55 MHz across the full mil temp range. There is one
> section of an 8 bit bus which I cannot get to go fast enough. Has anyone
> got any ideas on how to improve the fitting performance, or how I could
> increase the speed of the system. Also does any one know what type of
> algorithm they use to place and route, say Genetic Algorithm or some
> other process for optimization?

Of course, there are lots of ways to make things go faster.  Have you
contacted the local FAE?

Perhaps a bit more detail about the logic can help.

Some more general things to do, some not great ideas, but when you're stuck
...

Bias the voltage up higher with tight regulation.

Pick faster speed grade, if available.

Heat sink the part better and see if you can cut the temperature range.
You'll get somewhere around 0.3%/deg C.

Dump MX series and go with SX or SX-A.

Are you using timing driven P&R?

Some versions of the P&R did not give the same P&R solution each time [at
least that was my experience with some SX designs] and varied by a bunch;
try running it several times and see if your "luck" improves or if you get
the same solution each time.

Try a different revision of the P&R software, both older and newer.

Have you used Chipedit and try to improve the placement and help it with the
critical paths?

With the Act 2 logic cell in the MX-series, make sure that if you have logic
between flops the last stage is combinable with the flip-flop that you've
chosen.

Er, try Quicklogic QL3000 series.

Look carefully at fan out loads.

Redundant buffering of signals to cut loads if there's a bunch of fanout.

Sometimes inserting buffers will help (don't forget the preserve property!)
if the lines are long and you wind up long tracks or runs with a bunch of
antifuses.

Using an HDL?  Try schematics! ;-)

Anyways, just a few ideas to get started,

Have a good evening,

rk

p.s. Ah, I think we're up to 6 Actel users on the newsgroup! <g>

Article: 21335
Subject: Re: Difference between FPGA, PLD, CPLD ?
From: steve (Steve Rencontre)
Date: Fri, 17 Mar 2000 03:00 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <953166253.139941@busy.neca.nec.com.au>, 
jaredc@icpdd.neca.nec.com.au (Jared Church) wrote:

> So basically what we are all saying here is that there is no real 
> separation
> between these and the name is usually defined by the manufacturer as 
> opposed
> to strictly fitting in any guidlines as to the structure and other 
> physical
> characteristics of the devices ?

It's a pretty flexible boundary.

My own take is that anything relatively fine-grained (basic blocks 
are small LUTs, multiplexers, registers, etc) is an FPGA and anything with 
big sum-of-products arrays is a [C]PLD. The difference between C and non-C 
is whether there is further higher-level structure imposed on the SoP 
blocks.

This is not a rigorous definition, but TBH, it's not really a big issue. 
There are more important choices to be made when selecting a logic device 
than which set of initials its manufacturer stamps on it.

--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk
Article: 21336
Subject: Re: Altera literature misleading
From: "JPC" <cachemi@cppm.in2p3.fr>
Date: Fri, 17 Mar 2000 09:12:38 +0100
Links: << >>  << T >>  << A >>
I agree with Steve because I experimented the same kind of problem with the
real number of I/O available for each device. I needed to count the number
of LVDS I/O in the 20 pages pinout to exactly know the number.

The problem with the Altera documentation is that they tried to merge in a
single document the feature of *all* their components which is stupid and
very confusing.

To take another example, there is not a single example of how to
interconnect the EPC2 EPROMS for initializing an APEX20K400, and yet it is
not that simple because you beed to daisy chain 3 EPROMS and choose between
JTAG or not JTAG interconnection. You need to search clues in several
documentation to succeed. What would it cost to them to provide an example
per chip.

Are they sparing paper or web space ?

Jean-Pierre


Steve Dewey a écrit dans le message ...

>
>Am I being naive, or have other people been (nearly) caught out by this?
>Does anyone else think that the literature is misleading ?
>
>
>--
>Steve Dewey
>Remove 123 for mail.


Article: 21337
Subject: Re: Actel Design with A42MX36 Help
From: "Alasdair MacLean" <nojunk@gecm.com>
Date: Fri, 17 Mar 2000 08:54:26 -0000
Links: << >>  << T >>  << A >>

rk wrote in message <38D194EE.A5AD0EA5@nospam.erols.com>...
>Andrew batchelor wrote:
>
>> Dear All
>>
>> I am a hardware engineer down in Rochester, and I am having great
>> problems fitting a design to a 42MX36. The problem is that I would like
>> my design to run at 55 MHz across the full mil temp range. There is one
>> section of an 8 bit bus which I cannot get to go fast enough. Has anyone
>> got any ideas on how to improve the fitting performance, or how I could
>> increase the speed of the system. Also does any one know what type of
>> algorithm they use to place and route, say Genetic Algorithm or some
>> other process for optimization?
>
>Of course, there are lots of ways to make things go faster.  Have you
>contacted the local FAE?
>
>Perhaps a bit more detail about the logic can help.
>
>Some more general things to do, some not great ideas, but when you're stuck
>...
>
>Bias the voltage up higher with tight regulation.
>
>Pick faster speed grade, if available.
>
>Heat sink the part better and see if you can cut the temperature range.
>You'll get somewhere around 0.3%/deg C.
>
>Dump MX series and go with SX or SX-A.
>
>Are you using timing driven P&R?
>
>Some versions of the P&R did not give the same P&R solution each time [at
>least that was my experience with some SX designs] and varied by a bunch;
>try running it several times and see if your "luck" improves or if you get
>the same solution each time.
>
>Try a different revision of the P&R software, both older and newer.
>
>Have you used Chipedit and try to improve the placement and help it with
the
>critical paths?
>
>With the Act 2 logic cell in the MX-series, make sure that if you have
logic
>between flops the last stage is combinable with the flip-flop that you've
>chosen.
>
>Er, try Quicklogic QL3000 series.
>
>Look carefully at fan out loads.
>
>Redundant buffering of signals to cut loads if there's a bunch of fanout.
>
>Sometimes inserting buffers will help (don't forget the preserve property!)
>if the lines are long and you wind up long tracks or runs with a bunch of
>antifuses.
>
>Using an HDL?  Try schematics! ;-)
>
>Anyways, just a few ideas to get started,
>
>Have a good evening,
>
>rk
>
>p.s. Ah, I think we're up to 6 Actel users on the newsgroup! <g>
>

A couple of things I'd add to Richard's suggestions:
1) If you have counters, adders or any other generic macros around that
level of complexity, try using ActGen to improve performance.
2) Use asynchronous resets (see the Actel HDL coding guide for details).
3) Try asking your question on the internal MAv newsgroup (ask Howard Jones
if you don't know about it already).
4) Try using a different synthesis tool, even if it's only on one
hierarchical block. ActMap isn't the fanciest tool out there, but for
getting maximum performance from Actel devices, it's hard to beat.
5) I'm sitting in a room with 4 other engineers who regularly use Actel
FPGAs - you're not alone !

        -- Alasdair

Alasdair MacLean,
Senior Development Engineer,
BAE Systems,
Sensor Systems Division,
Silverknowes,
Edinburgh.


Article: 21338
Subject: Is there a cheaper alternative to ByteblasterMV?
From: "Dennis Krupp" <lone-traveler@usa.net>
Date: Fri, 17 Mar 2000 00:54:37 -0800
Links: << >>  << T >>  << A >>
Does anyone know if and where I can get a ByteblasterMV for less than the
bloody $150 that Altera charges short of having to build it myself?
Thanks


Article: 21339
Subject: Re: Xilinx configuration current
From: Peter <peterc@hmgcc.gov.uk>
Date: Fri, 17 Mar 2000 09:08:23 +0000
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Not quite:.
> The FPGA does use its internal oscillator, the one that is later also used
> as CCLK geerator, but it does *not* run an N-bit shift register, but rather
> clears one frame at a time,i.e. many hundred bits at a time.  And the
> second tim around, there is hardly any activity.
> This is not where the device will spend a lot of current.
> Note that bit-serial configuration is done in a similar way: shift in one
> frame, then transfer the whole frame into its destination. No really long
> shift register here either.
> 

Peter,

Are you saying that I should NOT expect to see about 150mA while the
PROGRAM pin is held low to re-program the device? Or are you saying that
the memory clearing is not taking the current?

Is 150mA a reasonable expected current when PROGRAM is held low (it
lasts for 200 to 300ms)?

I'm trying to get a feel for whether this is my circuit, or the design
of the Xilinx (Greg seems to have seen the same as me which suggests
it's maybe the Xilinx part.)

-- 
Peter Crighton
Article: 21340
Subject: Re: Is there a cheaper alternative to ByteblasterMV?
From: "John Renvar" <elka@altavista.net>
Date: Fri, 17 Mar 2000 01:18:31 -0800
Links: << >>  << T >>  << A >>
Several month ago I was searching for a byteblaster online and I came across
a web site that sells a clone of the Altera thing for something like half
price. I bought one and it works just like the real thing. I believe their
web site is at www.amboy.com
J.


> Does anyone know if and where I can get a ByteblasterMV for less than the
> bloody $150 that Altera charges short of having to build it myself?
> Thanks
>
>


Article: 21341
Subject: Re: Is there a cheaper alternative to ByteblasterMV?
From: Leon Heller <leon_heller@hotmail.com>
Date: Fri, 17 Mar 2000 11:59:41 GMT
Links: << >>  << T >>  << A >>
In article <sd3snkb59n45@corp.supernews.com>,
"Dennis Krupp" <lone-traveler@usa.net> wrote:
> Does anyone know if and where I can get a ByteblasterMV for less than
the
> bloody $150 that Altera charges short of having to build it myself?
> Thanks
>
>

I designed a PCB and made my own. I've got a spare PCB you can have if
you want one.

Leon
--
Leon Heller, G1HSM
Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824
Email: leon_heller@hotmail.com
Web: http://www.geocities.com/SiliconValley/Code/1835


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21342
Subject: Re: Actel Design with A42MX36 Help
From: rk <stellare@nospam.erols.com>
Date: Fri, 17 Mar 2000 07:28:16 -0500
Links: << >>  << T >>  << A >>
Alasdair MacLean wrote:

And a few comments (WOW!, not much conversation about these topics here :-)

> A couple of things I'd add to Richard's suggestions:
> 1) If you have counters, adders or any other generic macros around that
> level of complexity, try using ActGen to improve performance.

Agreed.  I stayed off this since he was having problems with a bus.  ActGen, for
many of its functions, is extremely tough to beat.  Normally, I won't even try.
Actmap is pretty good about not trying too hard itself for some functions and
just calls ActGen.  The logic is pretty tight in the macros and they take
advantage of the architecture very well.  For example, parity functions are
*very* well done [and Actmap doesn't always recognize those correctly] and it'll
be tough for a humanoid to beat it, unless one needs to pipeline a function, for
example, for more performance.  In that case, I would take the Actgen output and
then pipeline that.

=============

> 2) Use asynchronous resets (see the Actel HDL coding guide for details).
> 3) Try asking your question on the internal MAv newsgroup (ask Howard Jones
> if you don't know about it already).
> 4) Try using a different synthesis tool, even if it's only on one
> hierarchical block. ActMap isn't the fanciest tool out there, but for
> getting maximum performance from Actel devices, it's hard to beat.

Definitely.  I and a co-worker have found [day job] that different synthesis
tools do better at different problems and that multiple synthesis tools are
required for optimimum performance.  Additionally, performance may improve or
degrade as you update a single tool for the same exact input!  Another finding
was that Actmap is very, very tough to beat when going against the other
synthesis tools for combinational logic.  Another finding was for very large
logic functions, Actmap which is normally slow, beat the pants off [20 minutes
vs. 5 hours] another tool that was highly touted for its speed as well as doing
far, far better for minimizing logic.  It looks like some of the algorithms in
the tools are geared for small functions and break down for large ones [perhaps
to be impressive during sales demos?]  For sequential logic, some of the other
tools do better.  Also, if you use another tool, send that EDIF output through
the Actmap optimizer, that can help quite a bit in some cases, as the Actel
software seems to do a better job of taking advantage of their logic element
(normally a 4:1 mux with AND and OR on the two select lines).

Do note though that in the latest release Actmap is no longer included!  I
thought that it would be included but no more development done on it.
GROWL!!!   I have not yet installed any of the new software for just that
reason, although I will have to since I wish to get access to the newest
devices.  As I have projects that use Actmap and need to be supported, this will
probably result in having to run multiple machines with different versions of
the software.  At day job, I keep one machine with DOS and WIN 3.1 on an old,
slow Pentium since the old software won't run on any modern motherboard [it will
fail to read the key properly from the parallel port] and I need to be able to
support older designs.  The old static timing analyzer had some nice features
too and analyzing old databases is a topic that comes up semi-frequently.

==============

> 5) I'm sitting in a room with 4 other engineers who regularly use Actel
> FPGAs - you're not alone !

[rk keels over, falls out of the chair, then slowly gets up].

Well, enough early morning babble,

Have a nice day,

rk


Article: 21343
Subject: SV: Atmel censors web access
From: "Ulf Samuelsson" <ulf@atmel.spammenot.com>
Date: Fri, 17 Mar 2000 13:55:14 +0100
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> skrev i
diskussionsgruppsmeddelandet:38CEE6E2.770947B3@xilinx.com...
> Mine was not a cry for help, it was a cry of outrage.

It *could* be also a filter inside Xilinx based on the principle
of how to avoid the famous "Ravenous Bug Blatter beast of Thraal", which
is so immensly stupid that it assumes if You can't see it, it can't see you
...  :-)
/ulf



> Hell, I used to exchange printed data books with Altera, while our two
> companies are not the best of friends ...  Why make life difficult for
each
> other when there are well-travelled ways around any such obstacle.
> To think that anybody can be so dumb, trying to restrain access to a
> website, and hope that will keep out the competition...
> If its on the web, it's public.
>
> Peter Alfke
> =====================
>
> Larry Doolittle wrote:
>
> > So look at them from home, or use a redirector service
> > like www.anonymiser.com.
> >
> >     - Larry Doolittle   <LRDoolittle@lbl.gov>
>




Article: 21344
Subject: Re: SpartanXL Express mode configuration
From: "Stewart, Nial [HAL02:HH00:EXCH]" <stewartn@europem01.nt.com>
Date: Fri, 17 Mar 2000 13:31:57 +0000
Links: << >>  << T >>  << A >>
Keith R. Williams wrote:
> 
> (yellow-wires are a part of the job). 

I've always wondered why someone doesn't produce cut and
strap wire in "PCB Green with a hint of white solder
mask and a touch of solder colour". It would be alot less
noticeable on boards :-).

Nial.
Article: 21345
Subject: Re: Virtex DLL inoperability
From: "Austin Franklin" <austin@darkroom99.com>
Date: 17 Mar 2000 14:37:54 GMT
Links: << >>  << T >>  << A >>
> >Steve, do you have the latest Service Pack (which is SP4).

I believe the latest is now SP5...

Article: 21346
Subject: Re: Actel Design with A42MX36 Help
From: "Richard I. Guerin" <guerin@IEEE.org>
Date: 17 Mar 2000 06:49:51 -0800
Links: << >>  << T >>  << A >>

You may also want to try setting the placeovernight variable to 1 in the Designer Series P&R tool.

-Rick

Article: 21347
Subject: Re: SV: Atmel censors web access
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 17 Mar 2000 09:35:16 -0800
Links: << >>  << T >>  << A >>

--------------9EEBF1A71EFF69D360CDE86D
Content-Type: text/plain; charset=iso-8859-1; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 8bit

Ulf Samuelsson wrote:

> It *could* be also a filter inside Xilinx based on the principle
> of how to avoid the famous "Ravenous Bug Blatter beast of Thraal", which
> is so immensly stupid that it assumes if You can't see it, it can't see you
> ...  :-)

Hej, Ulf.
It may look unbelievable from your point in good old Sweden that anybody in
your company can be so stupid to do this, but it's true.
This is the response I get:

Forbidden
You don't have permission to access / on this server.
Apache/1.3.9 Server at www.atmel.com Port 80

Perhaps you can straighten out your buddies in Silicon Valley that this is not
the way to behave. Tack för hjälpen !

Peter Alfke

P.S. Can we terminate this silly thread? We have embarrassed poor Atmel
enough.
As somebody suggested, most likely just one idiot manager is responsible for
this.




--------------9EEBF1A71EFF69D360CDE86D
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Ulf Samuelsson wrote:
<blockquote TYPE=CITE>It *could* be also a filter inside Xilinx based on
the principle
<br>of how to avoid the famous "Ravenous Bug Blatter beast of Thraal",
which
<br>is so immensly stupid that it assumes if You can't see it, it can't
see you
<br>...&nbsp; :-)</blockquote>
Hej, Ulf.
<br>It may look unbelievable from your point in good old Sweden that anybody
in&nbsp; your company can be so stupid to do this, but it's true.
<br>This is the response I get:
<p><b><font color="#FF0C29">Forbidden</font></b>
<br><b><font color="#FF0C29">You don't have permission to access / on this
server.</font></b>
<br><b><font color="#FF0C29">Apache/1.3.9 Server at www.atmel.com Port
80</font></b>
<p>Perhaps you can straighten out your buddies in Silicon Valley that this
is not the way to behave. Tack f&ouml;r hj&auml;lpen !
<p>Peter Alfke
<p>P.S. Can we terminate this silly thread? We have embarrassed poor Atmel
enough.
<br>As somebody suggested, most likely just one idiot manager is responsible
for this.
<br>&nbsp;
<br>&nbsp;
<br>&nbsp;</html>

--------------9EEBF1A71EFF69D360CDE86D--

Article: 21348
Subject: Looking for informations about VCC's EVC1 architecture.
From: Riad BOURGUIBA <bourguiba@ensea.fr>
Date: Fri, 17 Mar 2000 19:33:05 +0100
Links: << >>  << T >>  << A >>
Does any one have have any electronic document about the EVC1's
architecture, from Virtual Computer Corp. ?

Thanks

Riad

Article: 21349
Subject: Xilinx Foundation 1.5 Question
From: Nick <nkbrownKNOT@hotmail.com>
Date: Fri, 17 Mar 2000 23:50:15 GMT
Links: << >>  << T >>  << A >>
I've been trying to learn VHDL with Xilinx Foundation Series 1.5
(Student Edition).
After some initial problems with installation, everything seemed to work
all right. I was entering a new VHDL design and now there seems to be a
file missing again. Even older projects that had worked are experiencing
this problem This is what happens:

Synthesis -> Force Analysis of All HDL Source Files doesn't show
any problems.

Attempting to run a simulation however, I get:
"Cannot find file pcmdos.pif", Clicking ok opens the Simulator window
and the dialog "Netlist Fatal Error
was Detected, Would you like to browse the netlist.log for details",
clicking yes brings up:
"...
D:\......\tcount.edf: cannot open
Error 9432: Netlist fatal error was detected"

Does anyone know what the problem might be ? Do I have to re-install
again (to get pcmdos.pif back)? I have installed at least 5 time now.
None of the files were changed since I last used the software.
Thanks for any help.
-Nick



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