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Messages from 21225

Article: 21225
Subject: Re: Virtex and Virtex E package availability
From: "John L. Smith" <jsmith@visicom.com>
Date: Fri, 10 Mar 2000 17:41:48 -0800
Links: << >>  << T >>  << A >>
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We've been told 8-10 wks for a couple of FG680 Virtex-E. It'll take
that long to work out the rest of the board and what we throw into
the parts anyway. These things are getting BIG inside :oO.

Don McCarley wrote:
> 
> Has anyone been able to actually obtain the larger packages for Virtex and
> Virtex E devices?  Like the FG456, FG676, and FG680 for the 2.5V Virtex or
> the FG456, FG676, FG680, FG860, FG900, and FG1156 for the 1.8V Virtex-E.
> I'm interested in the lower io-count package availability experiences also.
> Thanks, DM
--------------7507BBFF15930032111DAA7A
Content-Type: text/x-vcard; charset=us-ascii;
 name="jsmith.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for John L. Smith
Content-Disposition: attachment;
 filename="jsmith.vcf"

begin:vcard 
n:Smith;John L.
tel;work:858-320-4102
x-mozilla-html:FALSE
url:http://www.visicom.com
org:Visicom;Imaging Products
adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA
version:2.1
email;internet:jsmith@visicom.com
title:Principal Engineer
x-mozilla-cpt:;30864
fn:John L. Smith
end:vcard

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Article: 21226
Subject: Re: Extremely fault tolerant strategies
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Sat, 11 Mar 2000 03:01:59 +0000
Links: << >>  << T >>  << A >>
Tom Burgess wrote:
> 
> Maybe
> 
>     von Neumann, J. (1963).
>     Probabilistic logics and the synthesis of reliable organisms from unreliable components.
>     In Collected works, (Taub, A. H., ed.), vol. 5, pp. 341-342, The MacMillan Company, New York.
> 
> Mark Thorson wrote:
> >
> > I vaguely recall a paper with a title something like
> > "On Building A Reliable System From Unreliable Nodes"
> > by von Neumann.  Does anyone remember that more clearly?

Another good place to check out is information on computers used in
space craft.
My question is once you find the fault what do you do then?  You can't
fix the faulty
part in a VLSI chip and you can't switch in a new circuit cause the
switching logic
may be faulty. Run 3 separate computers systems and pick the best 2 out
of 3?
Ben.
Why does programmable logic remind me of the problems with the computer
systems
found on star trek? 
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
The Lagging edge of technology:
http://www.jetnet.ab.ca/users/bfranchuk/woodelf/index.html

Article: 21227
Subject: Re: SpartanXL route and place
From: krw@attglobal.net (Keith R. Williams)
Date: 11 Mar 2000 03:40:55 GMT
Links: << >>  << T >>  << A >>
On Thu, 9 Mar 2000 15:36:34, Jonathan Bromley 
<jsebromley@brookes.ac.uk> wrote:

> "Keith R. Williams" wrote:
> <snip> 
> > I am rather surprised that P&R is so coupled to processor
> > performance. 
> 
> Why?  P&R is about the only thing that people do on PCs
> that's nearly 100% compute bound :-)

Well, I would assume that 100% CPU efficiency would be highly 
dependant on the memory subsystem (including caches).  It may be 
a coincidence that these two systems are related, but it 
surprised the hell out of me that the numbers were so close to 
MHz.

Remember, my office system is a PII-333 (one of the original 
Deschutes processors).  It's running at 3.5x66MHz.  The memory 
subsystem of this thing is crippled, at best.  The other system 
is a PIII (Katmai, I presume) running at 6x100MHz, with a faster 
cache and all that goes with it.  Yes, I am surprised when 
*anything* scales with just the processor clock.  

..not a big deal, I have a room full of these things waiting for
my design to actually *do* something.  I can put them to work on 
the P&R while I do other things.  Meanwhile, I have ammunition to
justify a better computer. I'd really like a useful laptop.  ;-)

----
  Keith  
Article: 21228
Subject: Synthesis question ( PCI based ASIC )
From: yang_li1 <yang_li1NOyaSPAM@yahoo.co.uk.invalid>
Date: Sat, 11 Mar 2000 05:10:29 -0800
Links: << >>  << T >>  << A >>
I have a design which is to be targeted to ASIC.

This design is synthesized with 66 Mhz PCI constraint. Timings
are not met with a slack of approx -4 ns
I gave worst case constraints from PCI side. and best case
synthesis cell selection options(timingwise)
As the code changes will take a lot time again to simulate, I
have another quick option

I am sure that this design will work on 33 Mhz clock.

Now what method I am following is
1) Synthesis with 66 Mhz constraint with worst case PCI delays.
Let the logic be generated with max efforts.
2) Generate timing reports for 66 Mhz , 33 Mhz . ( Ofcource 66
mhz will fail. )
3) Target it to ASIC. with a facility on board made for 33 Mhz,
66 Mhz. ( PCI66EN and Config space bit reset from board
jumpers ).
4) Assume that PCI chipset will give me best timings ( If I put
the card nearer to chipset ), I will give a try on 66 Mhz enable
via board jumpers.


Is this method appropriate ? What I am assuming is bus will not
give me worst timings.


---Yang Li
yang_li1@yahoo.co.uk



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Article: 21229
Subject: Xilinx IP Protection
From: "peter dudley" <padudle@worldnet.att.net>
Date: Sat, 11 Mar 2000 15:32:01 GMT
Links: << >>  << T >>  << A >>
Hello,

I am looking for a way to protect intellectual property inside a Xilinx
Virtex FPGA. We have developed a proprietary function and have applied for a
patent on it but now we need to do a design where the customer can modify
the non-proprietary parts of the FPGA.

One way to deal with the problem is to separate the design into two chips
with our proprietary logic in one chip and the customer specific logic in
the other. We could then give them the full source code to their chip and
only the compiled design for the chip that contains our IP. However, with
this approach we lose some of the advantage of integration such as size,
power, flexibility.

It occurred to us that perhaps we could combine all the logic into one chip
if we could convert our proprietary IP into a core. This way the customer
could modify the circuitry around the core and we could protect our IP.

Does anyone here have experience with creating a Xilinx core? We are not
really interested in going through formal qualification of the core, just IP
protection.

Are there simpler methods to protect IP that might be sufficient? For
example, could we protect the function by supplying only an edif netlist?

Thanks in advance for your advice.

--
Pete Dudley

Arroyo Grande Systems



Article: 21230
Subject: Xilinx Foundation Series and FSM designs
From: Enrico Migliore <enrico.migliore@fatti.com>
Date: Sat, 11 Mar 2000 16:15:33 GMT
Links: << >>  << T >>  << A >>
hi
 I need a tool that has a state editor and is
 able to produce D-type flip-flop equations: no VHDL
 or VERILOG code, but equations like

 y2+ = (y1 AND z) + (y2 EXOR z)

 where y2+ is the next state and y2 is present state.

 Does Xilinx Foundation do this job?

 thanks for any help
Enrico
Article: 21231
Subject: Re: Xilinx Foundation Series and FSM designs
From: Dave Vanden Bout <devb@xess.com>
Date: Sat, 11 Mar 2000 13:54:32 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------BA7EA10B1EC8EA03BFBBA6D1
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Content-Transfer-Encoding: 7bit

> hi
>  I need a tool that has a state editor and is
>  able to produce D-type flip-flop equations: no VHDL
>  or VERILOG code, but equations like
>
>  y2+ = (y1 AND z) + (y2 EXOR z)
>
>  where y2+ is the next state and y2 is present state.
>
>  Does Xilinx Foundation do this job?
>
>  thanks for any help
> Enrico

I know if you use the FSM editor in Foundation and output the design as ABEL and implement it in a CPLD, then the report file will have the boolean equations in it.

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||


--------------BA7EA10B1EC8EA03BFBBA6D1
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;Dave
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;-16464
fn:Dave Vanden Bout
end:vcard

--------------BA7EA10B1EC8EA03BFBBA6D1--

Article: 21232
Subject: Re: Synplicity for sale
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Sat, 11 Mar 2000 20:39:03 GMT
Links: << >>  << T >>  << A >>
On Thu, 09 Mar 2000 13:22:09 +0000, Rick Filipkiewicz
<rick@algor.co.uk> wrote:

>I was thinking more of Mentor buying Synplicity as a way of reducing the
>competition!

Believe me Rick, from where I'm standing, it really isn't necessary!

The incremental business that would result would _not_ be worth the
large "valuation" that I have heard that Synplicity management would
want to realise. Not by a looooong way!

Cheers
Stuart
An employee of Saros Technology:
Model Technology, Exemplar Logic, TransEDA, Renoir.
www.saros.co.uk
Article: 21233
Subject: Re: Xilinx IP Protection
From: Ray Andraka <randraka@ids.net>
Date: Sat, 11 Mar 2000 21:52:26 GMT
Links: << >>  << T >>  << A >>
The edif netlist is about all the security you'd get with a core too.  A
determined person can reverse engineer the edif netlist fairly easily.  You can
make his job harder by obfuscating the names of signals and functions, and by
making the edif netlist flat.  The fixed cores, at least in coregen 1.5 are
delivered as an edif netlist.  What makes them a core is the extra
stuff...documentation, simulation models, instantiation templates etc.

peter dudley wrote:

> Hello,
>
> I am looking for a way to protect intellectual property inside a Xilinx
> Virtex FPGA. We have developed a proprietary function and have applied for a
> patent on it but now we need to do a design where the customer can modify
> the non-proprietary parts of the FPGA.
>
> One way to deal with the problem is to separate the design into two chips
> with our proprietary logic in one chip and the customer specific logic in
> the other. We could then give them the full source code to their chip and
> only the compiled design for the chip that contains our IP. However, with
> this approach we lose some of the advantage of integration such as size,
> power, flexibility.
>
> It occurred to us that perhaps we could combine all the logic into one chip
> if we could convert our proprietary IP into a core. This way the customer
> could modify the circuitry around the core and we could protect our IP.
>
> Does anyone here have experience with creating a Xilinx core? We are not
> really interested in going through formal qualification of the core, just IP
> protection.
>
> Are there simpler methods to protect IP that might be sufficient? For
> example, could we protect the function by supplying only an edif netlist?
>
> Thanks in advance for your advice.
>
> --
> Pete Dudley
>
> Arroyo Grande Systems

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21234
Subject: Freeware Newsreader
From: isubmit@ientry.com (NTM)
Date: Sun, 12 Mar 2000 06:47:23 GMT
Links: << >>  << T >>  << A >>
Freeware Newsreader

Newsreader freeware at http://www.webmasterfree.com/xnews.html
is worth looking into.  Multiple ID and server support.  It's 
full version freeware.
ICQ 67129994
Article: 21235
Subject: Synthesis question ( PCI based ASIC )
From: yang_li1 <yang_li1NOyaSPAM@yahoo.co.uk.invalid>
Date: Sun, 12 Mar 2000 02:17:45 -0800
Links: << >>  << T >>  << A >>
I have a design which is to be targeted to ASIC.

This design has been synthesized with 66 Mhz PCI
constraint. Timings are not met with a slack of approx
-4 ns
I gave worst case constraints from PCI side.

As the code changes will take a lot time again to
simulate, I have another quick option
I am sure that this design will work on 33 Mhz clock.

Now what method I am following is
1) Synthesis with 66 Mhz constraint with worst case
PCI delays. Let the logic be generated with max
efforts.
2) Generate timing reports for 66 Mhz , 33 Mhz . (
Ofcource 66 mhz will fail. )
3) Target it to ASIC. with a facility on board made
for 33 Mhz, 66 Mhz. ( M66EN and Config space bit to be
tied from board jumpers ).
4) Assume that PCI chipset will give me best timings (
If I put the card nearer to chipset ), I will give a
try on 66 Mhz enable via board jumpers.


Is this method appropriate ? What I am assuming is bus
will not give me worst timings.


Thanks in advance

Yang Li







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Article: 21236
Subject: Altera LPM from VHDL
From: Tobin Fricke <tobin@cory.eecs.berkeley.edu>
Date: Sun, 12 Mar 2000 11:07:15 GMT
Links: << >>  << T >>  << A >>
I'm looking for a quick example of how to use an LPM module from VHDL in
Altera.. thanks, Tobin.
Article: 21237
Subject: SIGDA Ph.D. Forum at DAC'2000 -- new deadline Fri Mar.17
From: daforum@malibu.ece.uci.edu (Pai H Chou)
Date: 12 Mar 2000 11:15:44 GMT
Links: << >>  << T >>  << A >>
                            Call for Participation:
                        SIGDA Ph.D. Forum at DAC'2000

    ********************************************************************
    *     EXTENDED Submission Deadline:    Friday, March 17, 2000      *
    ********************************************************************

                       http://www.eng.uci.edu/~daforum/
                        Tuesday, June 6, 2000, 7-9pm
                        Los Angeles Convention Center

The Ph.D. Forum at the Design Automation Conference is a poster session
hosted by SIGDA for Ph.D. students to present and discuss their thesis
work with people in the DA community.  It is a great chance for the Ph.D.
students to get feedback on their work, and for the industry to preview
academic work-in-progress.  Travel grants will be available to select
students.

Eligible students are

  * those within 1-2 years from completion of thesis, with
    - either a university-approved thesis proposal,
    - or at least one published conference paper.

  * those who have completed their theses in the 1999-2000 academic year

What to Submit

  * A one-page abstract of the thesis in PDF, not including figures or
    references, and not to exceed 750 words.

  * A university-approved thesis proposal, or a published paper.
    this is required of ALL students.

  * Names of five reviewers whom the student would like to review the
    abstract

Dates

  * Submission deadline (extended): Friday, March 17, 2000
  * Travel Grants Notification:     April 30, 2000
  * Forum Presentation:             Tuesday, June 6, 2000, 7-9pm

Article: 21238
Subject: Re: Xilinx Foundation Series and FSM designs
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sun, 12 Mar 2000 11:23:08 -0500
Links: << >>  << T >>  << A >>
Enrico Migliore wrote:
> 
> hi
>  I need a tool that has a state editor and is
>  able to produce D-type flip-flop equations: no VHDL
>  or VERILOG code, but equations like
> 
>  y2+ = (y1 AND z) + (y2 EXOR z)
> 
>  where y2+ is the next state and y2 is present state.
> 
>  Does Xilinx Foundation do this job?
> 
>  thanks for any help
> Enrico

I don't know of any tools that will output a generic equation that you
are asking for. But I will offer my 2 cents worth on how to design FSMs
in FPGAs. 

I assume that you are working with Xilinx FPGAs or something similar and
using schematic capture. These devices have 4 input LUTs and lots of
registers. I find that FSMs are best done one hot encoded. This allows
each state to be represented by one signal. The state diagrams can be
easily translated with a one to one correspondence between the trasition
lines and logic elements. 

Each trasistion is an AND gate with the from state as one input and the
transistion condition as another input. The outputs of all the AND gates
for a given state are ORed together. This signal must be negated on the
exit conditions (another AND gate). This signal then defines the state.
If you change the transitions into a state, you only have to add or
delete the AND gates feeding the OR gate. Changing the output from a
state affects the negation of the OR output. 

This is actually not hard to do in schematic form. I would bet that Ray
A. can describe it better. I believe he even has some functional blocks
to make these elements. 

-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 21239
Subject: Re: Xilinx Foundation Series and FSM designs
From: Ray Andraka <randraka@ids.net>
Date: Sun, 12 Mar 2000 17:02:35 GMT
Links: << >>  << T >>  << A >>
I do.  I've got the basic elements as hierarchical schematics.  The symbols
for those components look like flow chart items.  For example, the decision
diamond is drawn as you'd expect with an input a yes branch output and a no
branch output.  Addtionally, there is a condition input.  Underneath the
symbol, the schematic is a pair of and gates with the condition and input
wired to both.  The no output and has its condition input inverted.  I have
the OR gates separate, and these have a symbol that looks like a wire
junction.

This works out nicely because you wind up with a schematic that looks for
all the world like a flowchart. It is easy to grok what it does and almost
as easy to make changes.  Even complicated state machines are quick to
design and easy to enter.

Rickman wrote:

> Each trasistion is an AND gate with the from state as one input and the
> transistion condition as another input. The outputs of all the AND gates
> for a given state are ORed together. This signal must be negated on the
> exit conditions (another AND gate). This signal then defines the state.
> If you change the transitions into a state, you only have to add or
> delete the AND gates feeding the OR gate. Changing the output from a
> state affects the negation of the OR output.
>
> This is actually not hard to do in schematic form. I would bet that Ray
> A. can describe it better. I believe he even has some functional blocks
> to make these elements.

The credit for this technique goes to the guys at highgate though.  I just
adopted it very early on.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21240
Subject: FPGA Prototype Boards/System Listing Updated
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sun, 12 Mar 2000 14:54:43 -0800
Links: << >>  << T >>  << A >>
Hi Folks,

Just a quick note that the list of FPGA prototype boards and systems has
been updated on The Programmable Logic Jump Station
(http://www.optimagic.com/boards.html).

If you know of some boards that are missing, please let me know.  Ideally,
we're trying to limit the list to those that are commercially available.
Thanks.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 21241
Subject: Re: Book recommendations?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sun, 12 Mar 2000 14:57:23 -0800
Links: << >>  << T >>  << A >>
There is a list of VHDL books on The Programmable Logic Jump Station at
http://www.optimagic.com/books.html.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

<stang99@my-deja.com> wrote in message news:89gro4$vbo$1@nnrp1.deja.com...
> I am in need of a good book covering VHDL techniques for synthesis in
> PLD's, especially FPGA's.  A more general book covering VHDL for
> synthesis (not PLD's specifically) would be just as good. If anyone has
> any suggestions I would greatly appreciate it.  Thanks in advance.
>
> John M.
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 21242
Subject: DSP with FPGA
From: "Jean-Réginald Louis" <louis.reginaldjean@teccart.qc.ca>
Date: Mon, 13 Mar 2000 00:15:14 -0500
Links: << >>  << T >>  << A >>
Hi. I'm new to this field. I have a good idea of what we can do with FPGA
but I saw something that I can understand. I found a companie (in the Web)
that do DSP with FPGA. If I'm not wrong DSP are like MCU, but specifically
designed to handle analog data. So how can we handle analog data in FPGA
pins. What's worst, I saw (in the same compagny) "Modulation and
demodulation with FPGA". How can we do this?




Article: 21243
Subject: Standalone EEPROM memories
From: dnardi <dnardiNOdnSPAM@engdiv.iai.co.il.invalid>
Date: Sun, 12 Mar 2000 22:00:43 -0800
Links: << >>  << T >>  << A >>
Does anyone know of a prewired standalone EEPROM memory that can
be used for
storing data logging information in a hostile environment,
unpowered, for long
periods of time?  We are after about 1MByte of storage area.
   If not all of those features, than what would you suggest?




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Article: 21244
Subject: Re: DSP with FPGA
From: Jonas Thor <thor@NO.SPAM.sm.luth.seNO.SPAM>
Date: Mon, 13 Mar 2000 08:01:30 +0100
Links: << >>  << T >>  << A >>
Hi!

DSP is *Digital* signal processor or processing.

You can not handle analog data in with an FPGA, you first have to
convert the analog signal to a digital signal and then process it.

/ Jonas

On Mon, 13 Mar 2000 00:15:14 -0500, "Jean-Réginald Louis"
<louis.reginaldjean@teccart.qc.ca> wrote:

>Hi. I'm new to this field. I have a good idea of what we can do with FPGA
>but I saw something that I can understand. I found a companie (in the Web)
>that do DSP with FPGA. If I'm not wrong DSP are like MCU, but specifically
>designed to handle analog data. So how can we handle analog data in FPGA
>pins. What's worst, I saw (in the same compagny) "Modulation and
>demodulation with FPGA". How can we do this?
>
>
>

Article: 21245
Subject: Xilinx FPGA densities
From: Steven Derrien <sderrien@irisa.fr>
Date: Mon, 13 Mar 2000 15:59:12 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm looking for data concerning the various Xilinx FPGA devices (from
XC3000 to Virte-E). Specifically i'm looking for their year of
introductions (i'd like to see how FPGA density evolve with time). I
have been looking on Xilinx web site but did not find what I was looking
for. Can someone help me with this ?

Steven


Article: 21246
Subject: Re: DSP with FPGA
From: Ray Andraka <randraka@ids.net>
Date: Mon, 13 Mar 2000 15:44:15 GMT
Links: << >>  << T >>  << A >>
Jean,

DSP is DIGITAL signal processing.  An Analog to Digital converter (ADC) is
used to convert the analog signal to a discrete time series of digital values
representing the analog signal.  The digital values are typically 8-16 bits
each.  Some modern ADC's can sample at 200MHz or more.  The basic math theory
is pretty much the same with the exception of dealing with discrete time
signals instead of continuous time.  With that in mind, the FPGA is simply
doing the math needed to demodulate the signal into a discrete digital
base-band signal.  By performing the signal processing digitally, we gain
advantages in the flexibility of the system, and at the same time eliminate
many of the analog calibration headaches.

"Jean-Réginald Louis" wrote:

> Hi. I'm new to this field. I have a good idea of what we can do with FPGA
> but I saw something that I can understand. I found a companie (in the Web)
> that do DSP with FPGA. If I'm not wrong DSP are like MCU, but specifically
> designed to handle analog data. So how can we handle analog data in FPGA
> pins. What's worst, I saw (in the same compagny) "Modulation and
> demodulation with FPGA". How can we do this?

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 21247
Subject: Re: DSP with FPGA
From: "Jean-Réginald Louis" <louis.reginaldjean@teccart.qc.ca>
Date: Mon, 13 Mar 2000 12:06:38 -0500
Links: << >>  << T >>  << A >>
Excuse me! I didn't have a clear idea of what it's a DSP. In my course, I'm
learning microcontroller. I have friends studying telecom (college level)
and they using DSP to manipulate signal (like sound) and I automatically
made an association between telecom and DSP.

Can someone tell me the difference between a MCU (microcontroller), a DSP
and a CPU. What type of processing unit are use in what type of
project/environement/situation/etc ? Why a graphics card use a DSP (like the
nVidia GeForce (if I'm not wrong)) ?

> Hi!
>
> DSP is *Digital* signal processor or processing.
>
> You can not handle analog data in with an FPGA, you first have to
> convert the analog signal to a digital signal and then process it.
>
> / Jonas
>
> On Mon, 13 Mar 2000 00:15:14 -0500, "Jean-Réginald Louis"
> <louis.reginaldjean@teccart.qc.ca> wrote:
>
> >Hi. I'm new to this field. I have a good idea of what we can do with FPGA
> >but I saw something that I can understand. I found a companie (in the
Web)
> >that do DSP with FPGA. If I'm not wrong DSP are like MCU, but
specifically
> >designed to handle analog data. So how can we handle analog data in FPGA
> >pins. What's worst, I saw (in the same compagny) "Modulation and
> >demodulation with FPGA". How can we do this?
> >
> >
> >
>


> Hi!
>
> DSP is *Digital* signal processor or processing.
>
> You can not handle analog data in with an FPGA, you first have to
> convert the analog signal to a digital signal and then process it.
>
> / Jonas
>
> On Mon, 13 Mar 2000 00:15:14 -0500, "Jean-Réginald Louis"
> <louis.reginaldjean@teccart.qc.ca> wrote:
>
> >Hi. I'm new to this field. I have a good idea of what we can do with FPGA
> >but I saw something that I can understand. I found a companie (in the
Web)
> >that do DSP with FPGA. If I'm not wrong DSP are like MCU, but
specifically
> >designed to handle analog data. So how can we handle analog data in FPGA
> >pins. What's worst, I saw (in the same compagny) "Modulation and
> >demodulation with FPGA". How can we do this?
> >
> >
> >
>


Article: 21248
Subject: Testbench for a modulator and a demodulator
From: "Björn Lindegren" <e97bjli@thn.htu.se>
Date: Mon, 13 Mar 2000 20:39:07 +0100
Links: << >>  << T >>  << A >>
Hi

I write two VHDL programs, one for a modulator and one for a demodulator
(for sound transmission).

I know that the modulator works good.

And now I want to test the demodulator, so I have to write a testbench for
it.

I have never written a testbench and I don't know if my idea is the best.

If I use structural VHDL and use the modulator as component no 1, then the
modulator as component no 2 and then look at the output of the demodulator.

Is this a "simple" way to check the demodulator or does anyone else know a
better way?


Björn Lindegren





Article: 21249
Subject: Re: Testbench for a modulator and a demodulator
From: raja <raja@elec.uq.edu.au>
Date: Tue, 14 Mar 2000 12:28:58 +1000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Transfer-Encoding: 8bit

Hi,
To my knowledge , you can write testbench  for any type of description . if you
want to verify the demodulator , you can seperately simulate that . otherwise
you can interface the modulator and demodulator in the structural description .
Well , the book " the designers guide for Vhdl  " by peter ashenden  explains
clearly about testbench with lot of examples or you can refer Vhdl primer by
jayaram bhaskar .
if i am wrong , please correct me
hope this helps

kamal

"Björn Lindegren" wrote:

> Hi
>
> I write two VHDL programs, one for a modulator and one for a demodulator
> (for sound transmission).
>
> I know that the modulator works good.
>
> And now I want to test the demodulator, so I have to write a testbench for
> it.
>
> I have never written a testbench and I don't know if my idea is the best.
>
> If I use structural VHDL and use the modulator as component no 1, then the
> modulator as component no 2 and then look at the output of the demodulator.
>
> Is this a "simple" way to check the demodulator or does anyone else know a
> better way?
>
> Björn Lindegren

--------------CBCE2188E38A687915F5A540
Content-Type: text/x-vcard; charset=us-ascii;
 name="raja.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for raja
Content-Disposition: attachment;
 filename="raja.vcf"

begin:vcard 
n:kamalanathan;Raja
tel;home:07  38761962
tel;work:07 33658849
x-mozilla-html:FALSE
adr:;;;;;;
version:2.1
email;internet:raja@elec.uq.edu.au
fn:Raja kamalanathan
end:vcard

--------------CBCE2188E38A687915F5A540--



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