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Messages from 23400

Article: 23400
Subject: Re: Looking for 'FREE' FPGA software
From: steve (Steve Rencontre)
Date: Sat, 24 Jun 2000 03:00 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <395290D2.9DA46960@xilinx.com>, peter@xilinx.com (Peter Alfke) 
wrote:

> 
> 
> Without arguing specifically for Xilinx, Altera, Atmel, or any other:
> 
> The primary consideration should be the silicon performance, 
> availability, and
> pricing.
> The secondary consideration should be the software learning curve, and 
> ease of
> use.
> And third you look at software price.
> 
> If you are halfway serious about achieving something meaningful,
> and learning something valuable,
> the difference between $100 and zero is "peanuts", i.e. irrelevant.

This is fine if you're a company building something to sell, but for a 
hobbyist learning about FPGAs in their spare time, the priorities are 
somewhat different.

MaxPlus2 is a nice package to learn on and the price can't be beaten. And 
if you're buying one-off from a catalogue company, the chip prices won't 
bear much resemblance to the numbers in the press releases :-)

--
Steve Rencontre		http://www.rsn-tech.demon.co.uk
//#include <disclaimer.h>

Article: 23401
Subject: CAE Software and Internet Access
From: rk <stellare@nospamplease.erols.com>
Date: Fri, 23 Jun 2000 22:52:49 -0400
Links: << >>  << T >>  << A >>
Hi,

I recently at day job, in an attempt to increase security, installed a
software firewall on my PC.  Now, when running Viewdraw, for instance, I
note that when it starts it attempts to access the Internet.  Why does
it do this?  What do you'all* think about a company sending you a .exe,
giving it access to your machine, and then it goes ahead and goes on the
Internet to do who-knows-what?

Comments?

Winston Smith

* - I am currently living on the Eastern coast, south of the Mason-Dixon
line.

Article: 23402
Subject: Re: a lot of basic questions - where's the FAQ?
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Fri, 23 Jun 2000 22:59:01 -0400
Links: << >>  << T >>  << A >>
goto the Xilinx website http://www.xilinx.com and download the
literature, everything that you need to know is there.


Eric L wrote:
> 
> >Don't. You really don't need a separate programmer since all "modern" CPLDs
> can
> >be
> >programmed in the system, and SRAM-based FPGAs never needed a programmer. That
> >leaves only the antifuse parts in need of a programmer. But since they are not
> >even reprogrammable, you might as well let the distributor program them for
> you.
> >
> >>
> 
> So how would I do it if I bought a Xilinx XC9500?
> 
> >> If I wanted to make a system say using a microcontroller with a PLD or FPGA
> to
> >> configure, how would I do it? I know xilinx sells their test boards but
> those
> >> are for one chip use and soldering and desolering would be a pain.
> >
> >I don't understand what you mean.
> >
> >>
> >>
> 
> well let's say I have a robot that has a xilinx FPGA in it and I program it to
> be an AND-gate (for discussion purposes) and then I suddenly need it to act as
> an OR-gate. How would I do something like that? Perhaps the previous question
> and this question are the same..
> 
> Thanks
> eric
Article: 23403
Subject: Re: Xilinx xc4000
From: eefox@uxmail.ust.hk ( WU Chi Hang FOX )
Date: 24 Jun 2000 04:25:39 GMT
Links: << >>  << T >>  << A >>
Rickman (spamgoeshere4@yahoo.com) 矗:
: The XC4000 can do any function of 4 variables in the 4 input LUTs. It
: can do any function of 3 variables in the 3 input LUT. The combination
: connected in the default manner does 3_func(4_func(a,b,c,d),
: 4_func(e,f,g,h), j). 

	Many thanks Rickman. So, if I got one more 4input LUT feed into
the 3 input LUT, (i.e. j is changed to  4_func(w,x,y,z) The total number
of functions will be   65536 * 65536 * 65536 * 256 ? 
My math is poor.... so welcome your teaching.....
	
-- 
*************************************************************************
*       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
*       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * 
*       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
*     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
*       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
*************************************************************************
Article: 23404
Subject: Different ?
From: eefox@uxmail.ust.hk ( WU Chi Hang FOX )
Date: 24 Jun 2000 04:38:15 GMT
Links: << >>  << T >>  << A >>
Dear all,
	If I implement the LUT like the followings, is it the true 
number of functions ?

	1) a 2-bit LUT    = 2exp4 functions
	2) 2 1-bit LUTs feeds to a 2-bit LUT
	   2_input(1_input(a),1_input(b))
	   = 2exp2 * 2exp2 * 2exp4 ?

	Seems stupid Q, but as I am new to it.so,please comment... 
	Many thanks.
	   
-- 
*************************************************************************
*       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
*       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * 
*       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
*     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
*       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
*************************************************************************
Article: 23405
Subject: Re: What tools do people use for Xilinx FPGAs?
From: Phil Hays <spampostmaster@sprynet.com>
Date: Fri, 23 Jun 2000 22:34:24 -0700
Links: << >>  << T >>  << A >>
James Kennedy wrote:

> At risk of starting a religious war, I'd like to ask all you people out
> there who do _real_ designs with Xilinx FPGA's, what tools do you
> currently use, and/or recommend?

=====================================================================

Simulation:       Modeltech PE
Synthesis:        Synplify, for the best quality of results.
Place and Route:  Xilinx 2.1i


-- 
Phil Hays
Article: 23406
Subject: Re: Xilinx xc4000
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 01:59:57 -0400
Links: << >>  << T >>  << A >>
It would be close to that. As Philip pointed out, there are some
functions that are indistinguishable and so the total number is somewhat
less. For example in each of the 4 LUTs there is a function where the
output is zero for all input combinations (likewise there is a function
with the output at a one). In the 3 LUT there are functions where that
input is a don't care. So these overall functions are indistinguishable
since the same sets of inputs give the same outputs. But the number of
these is small. 

As Philip also pointed out there are some trivial functions. These are
the ones where swapping the inputs give you the same outputs. I have not
tried to count these, but I think there are many. For example, if the
two 4 LUTs implement a pass through on input 1 and 4 respectively, and
the 3 LUT implements a symetrical function (I forget the mathematical
term for that, associative maybe?), you can swap the two 4 LUTs and the
two inputs and you get the same function. This is of no interest to
logic synthesis and so the two function are logically the same. 

There are also functions that will be the same due to logic
distribution. For example if the 4 LUTs are NAND functions and the 3 LUT
is a NOR, this would be equivalent to ANDs in both the 4 LUTs and the 3
LUT. 

So there are a lot of equivalent functions in that 2^40 set. 


WU Chi Hang FOX wrote:
> 
> Rickman (spamgoeshere4@yahoo.com) 矗:
> : The XC4000 can do any function of 4 variables in the 4 input LUTs. It
> : can do any function of 3 variables in the 3 input LUT. The combination
> : connected in the default manner does 3_func(4_func(a,b,c,d),
> : 4_func(e,f,g,h), j).
> 
>         Many thanks Rickman. So, if I got one more 4input LUT feed into
> the 3 input LUT, (i.e. j is changed to  4_func(w,x,y,z) The total number
> of functions will be   65536 * 65536 * 65536 * 256 ?
> My math is poor.... so welcome your teaching.....
> 
> --
> *************************************************************************
> *       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
> *       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) *
> *       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
> *     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
> *       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
> *************************************************************************

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23407
Subject: Re: a lot of basic questions - where's the FAQ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 02:12:36 -0400
Links: << >>  << T >>  << A >>
"B. Joshua Rosen" wrote:
> 
> goto the Xilinx website http://www.xilinx.com and download the
> literature, everything that you need to know is there.


I think that is a little like telling someone who is trying learn
english to get a dictionary. 

FPGAs are volatile. They do not hold their program when the power goes
off. So you have to load it everytime you power up the board. Likewise,
if you want the chip to do something different, you can reload a
different design into it. This is done by a fairly archane process which
is different for each brand of chip, but it basically clocks each bit or
byte into the chip until all the data is in. Not a big deal. When you
want to do it again, you just pull the Program pin low and start over. 

Just make sure your design is not controlling a motor or something
dangerous when you reprogram the part!




> Eric L wrote:
> >
> > >Don't. You really don't need a separate programmer since all "modern" CPLDs
> > can
> > >be
> > >programmed in the system, and SRAM-based FPGAs never needed a programmer. That
> > >leaves only the antifuse parts in need of a programmer. But since they are not
> > >even reprogrammable, you might as well let the distributor program them for
> > you.
> > >
> > >>
> >
> > So how would I do it if I bought a Xilinx XC9500?
> >
> > >> If I wanted to make a system say using a microcontroller with a PLD or FPGA
> > to
> > >> configure, how would I do it? I know xilinx sells their test boards but
> > those
> > >> are for one chip use and soldering and desolering would be a pain.
> > >
> > >I don't understand what you mean.
> > >
> > >>
> > >>
> >
> > well let's say I have a robot that has a xilinx FPGA in it and I program it to
> > be an AND-gate (for discussion purposes) and then I suddenly need it to act as
> > an OR-gate. How would I do something like that? Perhaps the previous question
> > and this question are the same..
> >
> > Thanks
> > eric

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23408
Subject: Re: Different ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 02:16:02 -0400
Links: << >>  << T >>  << A >>
This is starting to sound like homework now. How many equivalent
functions do you think are implemented in this structure?

To break it down a little more, how many and what are all of the
functions of a 1 bit LUT?


WU Chi Hang FOX wrote:
> 
> Dear all,
>         If I implement the LUT like the followings, is it the true
> number of functions ?
> 
>         1) a 2-bit LUT    = 2exp4 functions
>         2) 2 1-bit LUTs feeds to a 2-bit LUT
>            2_input(1_input(a),1_input(b))
>            = 2exp2 * 2exp2 * 2exp4 ?
> 
>         Seems stupid Q, but as I am new to it.so,please comment...
>         Many thanks.
> 
> --
> *************************************************************************
> *       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
> *       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) *
> *       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
> *     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
> *       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
> *************************************************************************

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23409
Subject: Re: Problem copying text from the Spartan II data sheet
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Sat, 24 Jun 2000 10:22:17 +0100
Links: << >>  << T >>  << A >>


Simon wrote:

> Since one of the objectives of copying is to extract the
> pinouts, perhaps pinout tables could be provided
> on the web site in a plain text format.

If Xilinx did that it would be a first in the history of digital IC data
sheets. Extracting pinout info from the PDF tables is a total PITA & does not
lend it self very easily to Perl script automation. In fact I find it easier
to get the info by making a dummy design that uses all the possible IOs in a
package, runing through to place&route and then extracting the info from the
.pad file + .par for banking into.

Article: 23410
Subject: Re: a lot of basic questions - where's the FAQ?
From: fliptron@netcom.com (Philip Freidin)
Date: 24 Jun 2000 09:47:52 GMT
Links: << >>  << T >>  << A >>
In article <2BD5A243F6E26BAF.8703E40D1AC625C5.30FAF4CC6B1CAB65@lp.airnews.net>,
Eric L <lamb_baa@hotmail.com> wrote:
>I have a lot of questions which I'm sure are asked constantly so let me just go 
>ahead and ask where the FAQ is located or if someone would repost it?

The www.optimagic.com site is the ideal place to start. Then you can
drill down by going to various vendor's sites and get their data sheets.

>
>Here are the questions anyway if someone doesn't mind answering them.
>

It's 2:00 am, I can't sleep, so why not  :-)

>1) Where do you find FPGA programmers? Are there schematics to build your own? 
>If I wanted to make a system say using a microcontroller with a PLD or FPGA to 
>configure, how would I do it? I know xilinx sells their test boards but those 
>are for one chip use and soldering and desolering would be a pain.

No desoldering devices to put in a programmer, no programmer to buy or 
build. Here's why:

FPGA's come in many flavors, and some are called CPLDs too. All these
devices though let you take an arbitrary design created either with
schematis or with an HDL like Verilog or VHDL, and map the design to the
resources within the device. The result of this translation process is
usually called a bit-stream. This is equivalent to running a C cross
compiler, and getting an executeable for a machine other than the one the
compiler runs on. When you are done, you have an executeable, but it isn't
running yet, because you have to load it into the target system. For
FPGA's this "loading" process is totally dependent on how the FPGA vendor
designed the FPGA/CPLD. The most common are: 

FPGAs: Xilinx/Altera/Atmel/Lucent    The bitstream is stored in the FPGA
                                     in what appears to be a very long shift 
                                     register. Sometimes this is incorrectly 
                                     referred to as SRAM, and these FPGAs are
                                     often referred to as SRAM based FPGAs.
                                     This memory is described as volatile,
                                     because when you turn off the power, the
                                     the device forgets what it was told.
                                     This also means you can reload it an 
                                     infinite number of times, and the 
                                     bitstreams dont have to be the same.
                                     Since the memory is volatile, you can 
                                     only program these devices (load the
                                     bitstream) after the device is on the 
                                     board, and the board is powered up.
                                     The bitstream is loaded using a small
                                     number of the device's pins.
                                     These vendors supply 'download' cables 
                                     that connect either to the parallel or 
                                     serial or USB port of your PC, and with 
                                     appropriate software take the bitstream 
                                     file and present it the right way to 
                                     the device.

CPLDs: Xilinx/Altera/Cypress/Lattice/
       Atmel                         The storage for the bitstream (for these
                                     devices, it is often called a program
                                     rather than a bitstream, but the
                                     difference is irrelevant) is stored in
                                     non-volatile storage cells that are 
                                     either EPROM, EEPROM, or FLASH-EEPROM.
                                     Most of these devices can be 
                                     programmed after they have been 
                                     installed on a board, by connecting a 
                                     programming cable to a few pins. Often 
                                     this is called JTAG programming, 
                                     although there are other names. Again,
                                     this cable is supplied by the vendor,
                                     but both Xilinx and Altera supply 
                                     schematics for their cables, and they 
                                     aren't very complex.

Other FPGAs: Actel/Quicklogic        These two companies use a storage 
                                     technology called antifuse, which is
                                     non-volatile, and can only be 
                                     programmed once. Also, they can only be 
                                     programmed off board in a device
                                     programmer. Given the capabilities of
                                     all the other devices available, I
                                     have never found a compelling reason
                                     to use these devices. Others have
                                     found them usefull, and so both these
                                     companies are still alive. 




>2) PLDs and FPGAs - When you remove them do they keep their data? For instance, 
>I program them with say a simple register and remove it from the programmer 
>would it still be usable on another system?

I think I covered this in the above answer.


>3) Off-Topic (sorry, no PLD newsgroup or is there?) - In digikey's catalog the 
>Xilinx XC9500 CPLDs have registers but no mention of flip-flops. What's the 
>difference? I know the difference as far as any digital design book will tell 
>me but what does that mean when programming it?

In this case the terms are used synonymously. Note that the XC9500 CPLDs 
are among the devices that can be "in-system" programmed via the JTAG 
protocol. So you can reprogram these devices without removing them from 
your board. Lattice calls this ISP, but most vendors support some form of 
this for their CPLDs, so this is not a differentiating factor.


>4) What's a good site to learn more about PLDs and/or PGAs? 

www.optimagic.com
www.xilinx.com
www.altera.com
www.latticesemi.com
www.atmel.com


>Thanks,
>Eric


Your welcome.

Philip Freidin



Article: 23411
Subject: Re: Xilinx xc4000
From: murray@pa.dec.com (Hal Murray)
Date: 24 Jun 2000 10:35:08 GMT
Links: << >>  << T >>  << A >>

> But parity check over 9 bits is one interesting application that can be
> done. And there are many more.

9 input ANDs or ORs seem pretty interesting to me on occasions.

There are also the obvious extensions of NAND, NOR, and
inversions on any set of inputs.

-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 23412
Subject: Re: a lot of basic questions - where's the FAQ?
From: murray@pa.dec.com (Hal Murray)
Date: 24 Jun 2000 10:40:57 GMT
Links: << >>  << T >>  << A >>

> well let's say I have a robot that has a xilinx FPGA in it and I program it to 
> be an AND-gate (for discussion purposes) and then I suddenly need it to act as 
> an OR-gate. How would I do something like that? Perhaps the previous question 
> and this question are the same..

The answer is that you reprogram it.

Traditionally, programming a PAL has been a big deal.  You needed
a programmer with the right flavor of magic for the PAL you were
using.

Many FPGAs are SRAM based.  They forget their program when you
turn off power.  So you have to reprogram them each time you
turn your board on.

One way to do that is to store the program in a ROM and use
a few junk IO pins from a convenient processor.  Changing the
program then turns into a subroutine call asking the program-it
subroutine to use a different program.




-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 23413
Subject: Re: How to cut the power disipation down ?
From: murray@pa.dec.com (Hal Murray)
Date: 24 Jun 2000 10:52:30 GMT
Links: << >>  << T >>  << A >>

> All modern Xilinx FPGA permanently disable all "vertical" clock branches
> that are not used in the design. This saves power, but does not help you in
> changing things dynamically.

Is there any reason that you haven't put an AND gate in the
little box that connects up the vertical clock line?  The idea
would be to use it as a clock-enable for those times when low
power is really important and you need to avoid flapping the
clock when you don't need it.

Would that mess up the column to column skew?  Could you get
the enable signal there from a nearby CLB in time to still run
things at full speed?

It would also be another level of logic for clock-enable gating,
but I expect the software would have troubles figuring out when
to use it that way.  (But manual control would make it available
when really necessary.)


-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 23414
Subject: Re: 500 million transistor FPGA's
From: murray@pa.dec.com (Hal Murray)
Date: 24 Jun 2000 11:10:38 GMT
Links: << >>  << T >>  << A >>

> Well, nobody is joking or pulling anybody's leg.
> This thread started by some incredulous amazement about 500 million
> transistors in next year's FPGA, and I answered that this was actually a
> conservative extrapolation.

Early in this thread, you said >100 million transistor devices were
shipping in volume today.

500 is a couple of factors of 2 beyond 100 and I generally think that
it takes more than a year for each doubling.  So I'm off by a few years.

What's the doubling time for transistor count?

Are the 100 and 500 more than a year apart?  Is the 500 first prototypes
vs volume?  When did prototypes of the 100 million transistor device
first ship?  ...

-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 23415
Subject: Re: F2.1i
From: erika_uk@my-deja.com
Date: Sat, 24 Jun 2000 11:55:01 GMT
Links: << >>  << T >>  << A >>
any reply please...peter

In article <8j0os5$oco$1@nnrp1.deja.com>,
  erika_uk@my-deja.com wrote:
> hey all,
>
> I want to install the F2.1i at home. Unfortunately, i can't have
> internet connection. Will the F2.1i be fully functionnal if i use just
> a schematic entry
>
> Thanks.
>
> --Erika
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23416
Subject: Re: Different ?
From: eefox@uxmail.ust.hk ( WU Chi Hang FOX )
Date: 24 Jun 2000 12:54:48 GMT
Links: << >>  << T >>  << A >>
Rickman (spamgoeshere4@yahoo.com) 矗:
: This is starting to sound like homework now. How many equivalent
: functions do you think are implemented in this structure?
: 
: To break it down a little more, how many and what are all of the
: functions of a 1 bit LUT?
: 
: > 
: >         1) a 2-bit LUT    = 2exp4 functions
: >         2) 2 1-bit LUTs feeds to a 2-bit LUT
: >            2_input(1_input(a),1_input(b))
: >            = 2exp2 * 2exp2 * 2exp4 ?
	First, thanks Rickman. However, I am really stucked at that, I am
not asking about HW questions, I really want to count how many fuctions
that a cascaded LUTs can implement. 
	For 1-bit LUT, I know there are 4 functions

				Output
	Input  	Function 1	2	3	4	
	0 		 0	0	1	1
	1		 0	1	0	1
	
Function 1 is a zero function, Function 2 is follower, Function 3 is NOT
Function 4 is a one function.
	However, what I am concerning is that, even there are 4 functions,
utimatelly, it is only 0 and 1 pass into the LUT, so, it does not matter.
So, what I think is, no-matter it is cascaded or not, the maximum
function is determined by the last LUT, so for this case, the no. of functions
is 2^4. 

	Then bringing back to the XC4000, if that is the case, then why
the total number of funtions is 2^40 instead of 2^8 ?

	At last, if it is not appropriate to post it here, then .......
.....


-- 
*************************************************************************
*       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
*       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) * 
*       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
*     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
*       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
*************************************************************************
Article: 23417
Subject: Re: Problem copying text from the Spartan II data sheet
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Sat, 24 Jun 2000 14:20:29 +0100
Links: << >>  << T >>  << A >>
On Sat, 24 Jun 2000 10:22:17 +0100, Rick Filipkiewicz <rick@algor.co.uk>
wrote:

>
>
>Simon wrote:
>
>> Since one of the objectives of copying is to extract the
>> pinouts, perhaps pinout tables could be provided
>> on the web site in a plain text format.
>
>If Xilinx did that it would be a first in the history of digital IC data
>sheets. Extracting pinout info from the PDF tables is a total PITA & does not
>lend it self very easily to Perl script automation. In fact I find it easier
>to get the info by making a dummy design that uses all the possible IOs in a
>package, runing through to place&route and then extracting the info from the
>.pad file + .par for banking into.

The BDSL files seem to have the pinouts in a relatively
machine-digestible format, without going to quite such lengths.
I haven't had cause to automate it yet, just noted the possibility.

- Brian

Article: 23418
Subject: Re: F2.1i
From: bkk411@hotmail.com
Date: Sat, 24 Jun 2000 14:09:44 GMT
Links: << >>  << T >>  << A >>


If you have a license/installation key, you can use the sw at
home (assuming you are installing on you home computer).

There is no need to be online to run the sw (to the best of my
knowledge).

bkk

In article <8j27ii$mte$1@nnrp1.deja.com>,
  erika_uk@my-deja.com wrote:
> any reply please...peter
>
> In article <8j0os5$oco$1@nnrp1.deja.com>,
>   erika_uk@my-deja.com wrote:
> > hey all,
> >
> > I want to install the F2.1i at home. Unfortunately, i can't have
> > internet connection. Will the F2.1i be fully functionnal if i use
just
> > a schematic entry
> >
> > Thanks.
> >
> > --Erika
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23419
Subject: Re: F2.1i
From: erika_uk@my-deja.com
Date: Sat, 24 Jun 2000 14:13:11 GMT
Links: << >>  << T >>  << A >>
but the license depend of your PC IP address.
In article <8j2ff1$rmf$1@nnrp1.deja.com>,
  bkk411@hotmail.com wrote:
>
>
> If you have a license/installation key, you can use the sw at
> home (assuming you are installing on you home computer).
>
> There is no need to be online to run the sw (to the best of my
> knowledge).
>
> bkk
>
> In article <8j27ii$mte$1@nnrp1.deja.com>,
>   erika_uk@my-deja.com wrote:
> > any reply please...peter
> >
> > In article <8j0os5$oco$1@nnrp1.deja.com>,
> >   erika_uk@my-deja.com wrote:
> > > hey all,
> > >
> > > I want to install the F2.1i at home. Unfortunately, i can't have
> > > internet connection. Will the F2.1i be fully functionnal if i use
> just
> > > a schematic entry
> > >
> > > Thanks.
> > >
> > > --Erika
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23420
Subject: Re: What tools do people use for Xilinx FPGAs?
From: bkk411@hotmail.com
Date: Sat, 24 Jun 2000 14:20:41 GMT
Links: << >>  << T >>  << A >>
In article <39537990.5B0E30@polybus.com>,
  "B. Joshua Rosen" <bjrosen@polybus.com> wrote:
...
>
> If you are just picking an HDL, go with Verilog. Verilog simulators
are
> much faster than VHDL, Verilog is much easier to read and write,
and
> it's much more concise. A couple of years ago it seemed like the
world
> was about evenly split between Verilog and VHDL, but these
days I don't
> see VHDL anywhere, everyone seems to be using Verilog.
Admitedly my
> sample is limited, and all the companies that I deal with are in
the
> networking industry.

Josh,

I'm a Verilog guy myself. But most of ASIA and Europe do use
VHDL (unfortunatley - I'm a freelancer ;*).

bkk

> Josh
>
> James Kennedy wrote:
> >
> > Hi everyone,
> >
> > At risk of starting a religious war, I'd like to ask all you people
out
> > there who do _real_ designs with Xilinx FPGA's, what tools do
you
> > currently use, and/or recommend?
> >
> > I'm currently in the process (and have been for some time) of
trying to
> > use Xilinx's foundation express but I think it has won the battle
:)
> >
> > So we're thinking of investing in a less buggy tools suite and
I'm
> > looking for any suggestions.
> >
> > Cheers,
> > James.
> >
> > --
> > James Kennedy
> > Electronics/Computer Design Engineer
> > IntelliDesign
> > Brisbane, Australia
> >
> > james (at) intellidesign dot com dot au
> >
> > Tel: (07) 3366 6478
> > Fax: (07) 3366 6471
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 23421
Subject: Re: F2.1i
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 11:20:03 -0400
Links: << >>  << T >>  << A >>
Yes, this gets into the issue of "Why is the software licensed to just
one machine and what do I do if it breaks and the new NIC will have a
different number so I licenced it to my hard drive serial number which
can be set to any value I want". 

I think Xilinx is very much aware of the possible abuse that hard drive
serial number licensing can allow. But I won't license the software any
other way (as long as they will let me). 

I bought development tools for TI DSPs which comes node locked to a
dongle. So now I have a $5000 key with is about the size of a box of
matches. I live in constant fear of losing this @*&$%! thing. I have
heard that the dongle is an artifact of GO DSP and that TI will provide
a copy without the dongle. I need to look into that. 

But the issues are similar. You need the tools to design the chips into
your boards. So restricting heavily the use of the the tools can affect
sales of the chips. On the other hand, letting the software roam around
freely can cost them more in support and loss of revenue. 

So call Xilinx and get a license to the hard drive in your work system.
Then you can make the serial number at home match and install the
software. This will actually be good for both you and them. You will get
more flexibility in where and when you use the software. They will
benifit from your increased experience and knowledge of their products. 

Another way to do it is to change your NIC at work to a PCMCIA card.
Then you can bring the NIC home with you. Xilinx has told me that they
will give you a new key when you change your NIC. This will cost you
about $200 per computer I believe. 


erika_uk@my-deja.com wrote:
> 
> but the license depend of your PC IP address.
> In article <8j2ff1$rmf$1@nnrp1.deja.com>,
>   bkk411@hotmail.com wrote:
> >
> >
> > If you have a license/installation key, you can use the sw at
> > home (assuming you are installing on you home computer).
> >
> > There is no need to be online to run the sw (to the best of my
> > knowledge).
> >
> > bkk
> >
> > In article <8j27ii$mte$1@nnrp1.deja.com>,
> >   erika_uk@my-deja.com wrote:
> > > any reply please...peter
> > >
> > > In article <8j0os5$oco$1@nnrp1.deja.com>,
> > >   erika_uk@my-deja.com wrote:
> > > > hey all,
> > > >
> > > > I want to install the F2.1i at home. Unfortunately, i can't have
> > > > internet connection. Will the F2.1i be fully functionnal if i use
> > just
> > > > a schematic entry
> > > >
> > > > Thanks.
> > > >
> > > > --Erika
> > > >
> > > > Sent via Deja.com http://www.deja.com/
> > > > Before you buy.
> > > >
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> > >
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23422
Subject: Re: Different ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 11:24:59 -0400
Links: << >>  << T >>  << A >>
The difference is that in this case, all of the possible functions that
can be implemented in the 1 bit LUT can be duplicated in the following 2
LUT. The only functions you can use the 1 LUT for (as you have shown)
are stuck at 1/0, invert, or pass. These are not very "interesting"
functions. They all result in overall functions of the array that are
duplicates of what you can do without the 1 LUTs. 

The larger problem is not so simplistic. Only a percentage of the
possible combinations result in duplicated overall functions.



WU Chi Hang FOX wrote:
> 
> Rickman (spamgoeshere4@yahoo.com) 矗:
> : This is starting to sound like homework now. How many equivalent
> : functions do you think are implemented in this structure?
> :
> : To break it down a little more, how many and what are all of the
> : functions of a 1 bit LUT?
> :
> : >
> : >         1) a 2-bit LUT    = 2exp4 functions
> : >         2) 2 1-bit LUTs feeds to a 2-bit LUT
> : >            2_input(1_input(a),1_input(b))
> : >            = 2exp2 * 2exp2 * 2exp4 ?
>         First, thanks Rickman. However, I am really stucked at that, I am
> not asking about HW questions, I really want to count how many fuctions
> that a cascaded LUTs can implement.
>         For 1-bit LUT, I know there are 4 functions
> 
>                                 Output
>         Input   Function 1      2       3       4
>         0                0      0       1       1
>         1                0      1       0       1
> 
> Function 1 is a zero function, Function 2 is follower, Function 3 is NOT
> Function 4 is a one function.
>         However, what I am concerning is that, even there are 4 functions,
> utimatelly, it is only 0 and 1 pass into the LUT, so, it does not matter.
> So, what I think is, no-matter it is cascaded or not, the maximum
> function is determined by the last LUT, so for this case, the no. of functions
> is 2^4.
> 
>         Then bringing back to the XC4000, if that is the case, then why
> the total number of funtions is 2^40 instead of 2^8 ?
> 
>         At last, if it is not appropriate to post it here, then .......
> .....
> 
> --
> *************************************************************************
> *       /\ /\     Name : Wu Chi Hang 璊标  ( FOX )  **  疻 **       *
> *       ^  ^      Job  : ELEC/CPEG Demonstrator (Rm. 2466, Ext. x7037 ) *
> *       .  .      Email: eefox@uxmail.ust.hk  /  eefox@ee.ust.hk        *
> *     =o =               chwu@usa.net / 97Cwch@alumni.ee.ust.hk         *
> *       u         Hpage: http://www.ee.ust.hk/~eefox/index.html 4294435 *
> *************************************************************************

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23423
Subject: Re: Problem copying text from the Spartan II data sheet
From: Rickman <spamgoeshere4@yahoo.com>
Date: Sat, 24 Jun 2000 11:28:22 -0400
Links: << >>  << T >>  << A >>
Rick Filipkiewicz wrote:
> 
> Simon wrote:
> 
> > Since one of the objectives of copying is to extract the
> > pinouts, perhaps pinout tables could be provided
> > on the web site in a plain text format.
> 
> If Xilinx did that it would be a first in the history of digital IC data
> sheets. Extracting pinout info from the PDF tables is a total PITA & does not
> lend it self very easily to Perl script automation. In fact I find it easier
> to get the info by making a dummy design that uses all the possible IOs in a
> package, runing through to place&route and then extracting the info from the
> .pad file + .par for banking into.

I don't think it is completely easy, but I did it once from a Lucent
data sheet into excel just by copying with cut and paste. I first put it
into a text file and then brought that into Excel. From there I could
manipulate the data in many ways rearranging the columns and rows,
sorting and manually moving entries with a simple click of the mouse.
Try it on one of the unprotected Xilinx sheets!

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 23424
Subject: Re: Powerup problem to 9500XL part @ -40 deg
From: "Elftmann" <elftmann@pacbell.net>
Date: Sat, 24 Jun 2000 10:02:32 -0700
Links: << >>  << T >>  << A >>
Eirik--

Try running a free running clock into TCK and insure that TMS is tied high,
this will insure that the TAP controller state machine returns to
the IDLE state.  Assuming it is in an unknown state.  If this corrects the
problem then most likely the Xilinx JTAG tap controller is not
getting sufficient power on reset at low temperature and is getting left in
an unknown state, which will most likely leave all I/Os tri-stated.

"Eirik Esp" <eirik.n.esp@lmco.com> wrote in message
news:394F8CF0.590E9D@lmco.com...
> Technically a CPLD problem, but I thought to post it here anyway.  I am
> having a problem with a XC9572XL @ -40 degrees.  It seems that when I
> cycle power, the JTAG controller becomes confused and takes over the
> chip.  The only way I can reset the JTAG controller is to power down and
> up at room temp.  Once the JTAG controller is confused, if I warm the
> part to room, it still misbehaves (TAP controller is in control).  I do
> have a switching power supply on the board, so the +5v starts coming up
> about 6 ms before the 3.3v, but if I apply a cap between the 3.3 and +5
> so the 3.3 starts coming up with the +5v, it still doesn't fix it.  I
> tried shorting the TCK directly to gnd and through a 1.1K pulldown, and
> I tied the TMS to +5 through 4.7K and to 3.3 through a wire.  I am
> really starting the suspect a ground bounce problem, or the TAP
> controller in the chip itself.  Anyone else have similar experiences the
> the 9500XL family at cold?  If so, how did you address it?  Also, anyone
> know how Xilinx tests the industrial rated parts at cold?  Any chance
> the JTAG controller is not tested?  If I access the JTAG port in the
> right way at cold, the parts seems to come back to life, so maybe if the
> testing uses the JTAG port, then it wouldn't demonstrate the fault we
> are experiencing?
>
>




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