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Messages from 22975

Article: 22975
Subject: Re: 3.3V I/O TO 5V LOGIC?
From: "Dalip K. Singh" <singh@hns.com>
Date: Tue, 06 Jun 2000 16:22:18 -0400
Links: << >>  << T >>  << A >>
I apologise, will be careful next time.

Andy Peters wrote:

> Dalip K. Singh wrote in message <393C0819.DDDED147@hns.com>...
> >I have used Quickswitch for 3.3/5V xlation and it works great.
> >P/n: QS34X2245.  I had to interface altera max7032aelc 3.3v part to 5v
> >ttl logic.
> >
> >-Dalip.
> >[Image]
>
> Please don't post data sheets here.  It's annoying.  Post a link to a web
> site instead.
> --
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) noao \dot\ edu
>
> "A sufficiently advanced technology is indistinguishable from magic"
>      --Arthur C. Clarke

Article: 22976
Subject: Re: 3.3V I/O TO 5V LOGIC?
From: Peter Alfke <palfke@earthlink.net>
Date: Wed, 07 Jun 2000 02:55:21 GMT
Links: << >>  << T >>  << A >>

--------------7607B5902295183738F8A6DC
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Jim Granville wrote:

> Peter Alfke wrote:
> >
> >Q: What about the reverse PFET CMOS diode - does this not clamp to
> Vccio+0.6v ?
>

No, that diode was "eliminated" when the output was designed to be "5-V
tolerant". You can pull the output to 6 V with only microamps of current. Even
when the 3.3-V supply is at zero volt!
That took some effort and circuit trickery, but it works.

Peter Alfke, Xilinx Applications


--------------7607B5902295183738F8A6DC
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<p>Jim Granville wrote:
<blockquote TYPE=CITE>Peter Alfke wrote:
<br>>
<br>>Q: What about the reverse PFET CMOS diode - does this not clamp to
<br>Vccio+0.6v ?
<br><a href="http://www.DesignTools.co.nz"></a>&nbsp;</blockquote>
No, that diode was "eliminated" when the output was designed to be "5-V
tolerant". You can pull the output to 6 V with only microamps of current.
Even when the 3.3-V supply is at zero volt!
<br>That took some effort and circuit trickery, but it works.
<p>Peter Alfke, Xilinx Applications
<br>&nbsp;</html>

--------------7607B5902295183738F8A6DC--

Article: 22977
Subject: VHDL code works in foundation 1.5, dosen't work in 2.1?
From: James Kennedy <spam@this.com>
Date: Wed, 07 Jun 2000 03:29:02 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------7CECC5631362FF15E6498E58
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

I've recently upgraded to the 2.1 version of the Xilinx foundation
tools, and I'm having some problems with a very simple design.  This
VHDL code works when compiled using the version 1.5 tools, but does not
work when using the 2.1 tools.  Has anybody else experienced this?  

I have got the latest patches for the tools, and all the licence stuff
is working OK.

The design is a simple 8 bit register mapped onto the I/O space on a
PC/104 bus (ISA bus).  I've attatched the code for anybody interested.

If anyone could help me with this it would be greatly appreciated.

Cheers,
James


-- 
James Kennedy
Electronics/Computer Design Engineer
IntelliDesign
Brisbane, Australia.

james at intellidesign dot com dot au

Tel: +61 7 3366 6478
Fax: +61 7 3366 6471
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--------------7CECC5631362FF15E6498E58--

Article: 22978
Subject: Xilinx Spartan; CLB's run out
From: "Jukka Pöppönen" <jukka.popponen@newel-elektro.com>
Date: Wed, 7 Jun 2000 09:48:18 +0300
Links: << >>  << T >>  << A >>
Hi,

I have try to designed the FPGA for digital picture processing (a very
simple one) using schematic editor. I have  problem that count of used CLB's
is too high. I tried to simplify the design, but  nothing seems to affect to
the used CLB count. Does anyone know what 'compnents' I shouldn't use for
not wasting CLB resources ?

Of course,a bigger Spartan would solve this problem, but is it really
necessary ?
Now I have used XCS10-version of Spartan.

Jukka Popponen
Finland


Article: 22979
Subject: Info on Ballynuey 2
From: Giuseppe Baruffa <baruffa@diei.unipg.it>
Date: Wed, 07 Jun 2000 09:12:20 +0200
Links: << >>  << T >>  << A >>
Hi all.

Since we are going to buy a Virtex development board,
we would like to know what do you think of a Ballynuey 2
from Nallatech.
Is there anybody using it? Is it worth the price?

We intend to use it for developping software radio
algorithms (downconverter).

Is there a link (beyond the official Nallatech site) where
we can get more information?

Thanks,

			Giuseppe.

-- 
 __________________________________________________________________ 
|                                                                  |
|Ing. Giuseppe Baruffa,                                            |
|                                                                  |
|c/o Dipartimento di Ingegneria Elettronica e dell'Informazione    |
|Università degli Studi di Perugia,                                |
|via G. Duranti 93, 06125 Perugia (Italy).                         |
|__________________________________________________________________|
|                       |                                          |
|Tel.: +39  75 5853626  |E-mail:baruffa@diei.unipg.it              |
|Fax:  +39  75 5853654  |                                          |
|                       |Home Page:                                |
|                       | http://dante.diei.unipg.it/~baruffa      |
|_______________________|__________________________________________|
Article: 22980
Subject: Re: Free tools "OpenTech cdrom"
From: Andrew MacCormack <andrewm@cadence.com>
Date: Wed, 07 Jun 2000 10:16:30 +0100
Links: << >>  << T >>  << A >>
iglasner@my-deja.com wrote:
>>    Even tho' I'm not looking for any free tool/hw/sw etc I was still
> wondering why should a CD be made which for sure will mean a certain
> cost.
> 
> If the intension was to make those kind of thing free the way I would
> think should be used is simple putting all the "staff" on the web maybe
> on several server and than it will really be free.
>

From the distributors' point of view: why is disk space and web server
maintainance free?

From the downloader's point of view: which ISP is free? And who wants to
spend ages downloading 650Mb (a CD's worth) over the net. Even at
30Kbytes a second (the fastest I've ever got anything over the net, even
with a fixed connection) that would take 6 hours. And for us poor ppl
with 56Kbit modems, its at least 26 hours. Since I rarely get better
than 28.8, it would be quicker and cheaper for somebody to post me a CD.


-- Andrew MacCormack                      email:  andrewm@cadence.com
-- Senior Design Engineer
-- Cadence Design Systems, Alba Campus, Livingston EH54 7HH, Scotland
-- Phone: +44 1506 595360                        Fax: +44 1506 595959
Article: 22981
Subject: Re: to make few modifications on a design
From: "disk" <personne@microsoft.com>
Date: Wed, 7 Jun 2000 12:13:05 +0200
Links: << >>  << T >>  << A >>
Hi,
I think that you can use floor planner editor, you can move blocs et
generate a place constraint file. I think, It will be better just moving
element that required short delay. Put as near as possible elements that
communicate together... And good luck.
For information, be carefull, timing simulator is really bad and tri-state
timing are false, so you will prefer using something like model-sim to have
good timing results...
See you

Paul

<jthioude@my-deja.com> a écrit dans le message :
8h8jei$pfa$1@nnrp1.deja.com...
> First of all, exuse me for my poor english.I've got a disign on a
XC4044XLA
> , implemented with Foundation 1.5i. This design is "critiqal in delay".I'd
> like to make few modifications on this design if possible, without
modifying
> the first routing. What is the best method??
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.


Article: 22982
Subject: Re: Where's OptiMagic?
From: fliptron@netcom.com (Philip Freidin)
Date: 7 Jun 2000 10:32:26 GMT
Links: << >>  << T >>  << A >>

I had the honor of talking to Mr. Optimagic today, and asked if he was 
aware that his web presence was sub-optimal. He told me that he was aware 
of the problem (incompetence at network solutions), and that he hoped 
that things would be restored in a day or two.

Ping early, and Ping often:  www.optimagic.com

Philip Freidin
Article: 22983
Subject: FC2 v3.4 & Selcet Block RAM in Virtex(E)
From: bkk411@my-deja.com
Date: Wed, 07 Jun 2000 10:53:39 GMT
Links: << >>  << T >>  << A >>


It appears that FPAG compiler is ignoring timing specs
of the select rams in the vertex fpgas.
Xilinx design manager properly points out those path
in the timing analysis tool.

I looked at all the obvoius places for answers but could not
find anything.

Anyone else experienced that, or knows what I'm doing wrong ?
I tryed both, directly insantiating RAM block (in my verilog)
code, and use memories generated with core gen.
Both times, there appear to be notiming constrains on clock
to output (and I presume on input).

Thanks for any tips suggestion !
bkk


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22984
Subject: Re: VHDL code works in foundation 1.5, dosen't work in 2.1?
From: Joshua Lamorie <jpl@xiphos.ca>
Date: Wed, 07 Jun 2000 10:07:50 -0400
Links: << >>  << T >>  << A >>


James Kennedy wrote:

> I've recently upgraded to the 2.1 version of the Xilinx foundation
> tools, and I'm having some problems with a very simple design.  This
> VHDL code works when compiled using the version 1.5 tools, but does not
> work when using the 2.1 tools.  Has anybody else experienced this?
>
> I have got the latest patches for the tools, and all the licence stuff
> is working OK.
>
> The design is a simple 8 bit register mapped onto the I/O space on a
> PC/104 bus (ISA bus).  I've attatched the code for anybody interested.

I have a fairly large project that builds and works perfectly on my target hardware with F1.5i,
however everything goes to hell after I upgraded to F2.1i.  However, my problem is that the
design does not build at all.  I am doing an HDL flow, but with a top-level schematic generated
VHDL netlist.  The bus handling seems different between the two versions, and I don't understand
how to connect a bus to a pin with a different number of lines.  The method for 1.5i doesn't
seem to work in 2.1i.

I also have a problem with some RLOC_ORIGIN requirement that has magically appeared because of a
tri-state buffer.

I currently have two cases open at Xilinx support, and for about a week or two for both, and
they are not moving at all.

I can't find any decent documentation about upgrading projects from 1.5i to 2.1i.  I've
re-installed 1.5i until these things are sorted out, but if any others have experience with
this, I'd also appreciate it.

When my cases are resolved, I'll make sure to post the results to this group.

thanks in advance

Joshua Lamorie
Systems Designer
Xiphos Technologies Inc.

Article: 22985
Subject: Xilinx foundation Student Edition problem.
From: "Seiya" <valid@email.address.com>
Date: Wed, 7 Jun 2000 08:03:02 -0700
Links: << >>  << T >>  << A >>
Hey, I bought a copy of Xilinx Foundation Student Ed.
and went through the registration process, received the stuff
for license.dat. I then plugged it into the path it should be by the command
line parameter, and I am not able to run anything other than Xilinx Design
manager. (Even then, when it starts to init, it gives errors) Generally the
error is that there are no "server" lines in my license.dat  however, this
means very little to me other than "no im not going to work."
Any ideas on what I might have missed?

(I've done the web-support, but have yet to get a response)
_seiya_ @ nergal.org (just remove spaces)

for the spam bots, try abuse@fbi.gov



Article: 22986
Subject: Re: Xilinx foundation Student Edition problem.
From: "disk" <personne@microsoft.com>
Date: Wed, 7 Jun 2000 17:10:12 +0200
Links: << >>  << T >>  << A >>
Try to check
--> the path for license.dat file in autoexec.bat
--> if you HD id or Network ID is correct into the license file

I haven't more idea !!

Paul


Article: 22987
Subject: XCV vs. XCV-E ?
From: "Domagoj" <domagoj@engineer.com>
Date: Wed, 7 Jun 2000 17:11:59 +0200
Links: << >>  << T >>  << A >>
Hi,
 I've noticed a strange relation in Virtex prices. XCV50E
has more system gates, more available IO pins, and more blockram,
and it's still cheaper than XCV50 (the same is for bigger chips) !!
Why ? How ?
 Maybe it's just a promotional trick. What do you think,
how will the prices (and price relations) behave in the next two
years ?

regards,
-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------


Article: 22988
Subject: Re: XCV vs. XCV-E ?
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 7 Jun 2000 15:22:51 GMT
Links: << >>  << T >>  << A >>
In article <8hlor8$b6l$1@bagan.srce.hr>, Domagoj <domagoj@engineer.com> wrote:
>Hi,
> I've noticed a strange relation in Virtex prices. XCV50E
>has more system gates, more available IO pins, and more blockram,
>and it's still cheaper than XCV50 (the same is for bigger chips) !!
>Why ? How ?

	The E series is fabricated on a .18 instead of a .25uM
process, uses 1.8 instead of 2.5 volt power supply, and does not
support 5V tolerant I/O.

	Since this is largely a process shrink, the die size is
smaller for the Virtex E.

> Maybe it's just a promotional trick. What do you think,
>how will the prices (and price relations) behave in the next two
>years ?

	It's more a process trick.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 22989
Subject: Synplify constrains
From: John Smithhhhh <gfsd@dgfhb.fr>
Date: Wed, 07 Jun 2000 18:25:58 +0300
Links: << >>  << T >>  << A >>
Help, I need somebody

Badly need exact format/examples for Synplicity design time constrains.
Pls Help!

Article: 22990
Subject: Re: Where's OptiMagic?
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Wed, 07 Jun 2000 17:36:24 +0200
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
> 
> I had the honor of talking to Mr. Optimagic today, and asked if he was
> aware that his web presence was sub-optimal. He told me that he was aware
> of the problem (incompetence at network solutions), and that he hoped
> that things would be restored in a day or two.
> 
> Ping early, and Ping often:  www.optimagic.com
> 
> Philip Freidin

Why didn't you post the resurrection of optimagic?
I think thats more efficient than polling ;-)


Patrick
-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713
Article: 22991
Subject: Re: XCV vs. XCV-E ?
From: "Domagoj" <domagoj@engineer.com>
Date: Thu, 8 Jun 2000 02:44:18 +0200
Links: << >>  << T >>  << A >>
Hi,

> The E series is fabricated on a .18 instead of a .25uM
> process, uses 1.8 instead of 2.5 volt power supply, and does not
> support 5V tolerant I/O.
> Since this is largely a process shrink, the die size is
> smaller for the Virtex E.

I've assumed that , but it still doesn't make sense to me. Xilinx probably
wants to squeeze every last drop of juice from plain old Virtex , so why
would they sell better chips cheaper. This doesn't help them selling
plain Virtex , except if someone needs 5V tolerant IOs.

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------



Article: 22992
Subject: Re: Xilinx Spartan; CLB's run out
From: Ray Andraka <ray@andraka.com>
Date: Thu, 08 Jun 2000 01:28:29 GMT
Links: << >>  << T >>  << A >>
What is the nature of your "digital picture processing"?   What kind of data
rates do you need to handle?  Answers to these questions will dictate the design
architecture.  If the processing is relatively complex and you need to work at a
video frame rate you may not have enough logic resources in an XCS10 no matter
how you slice it.  If it is less demanding, you might consider reconfiguration
to do the processing in steps and/or using bit serial techniques to reduce the
size of the hardware.  In any event, it is not so much what components not to
use, as much as designing to the requirements and to the architecture.

"Jukka Pöppönen" wrote:

> Hi,
>
> I have try to designed the FPGA for digital picture processing (a very
> simple one) using schematic editor. I have  problem that count of used CLB's
> is too high. I tried to simplify the design, but  nothing seems to affect to
> the used CLB count. Does anyone know what 'compnents' I shouldn't use for
> not wasting CLB resources ?
>
> Of course,a bigger Spartan would solve this problem, but is it really
> necessary ?
> Now I have used XCS10-version of Spartan.
>
> Jukka Popponen
> Finland

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 22993
Subject: TTL device Libraries
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Thu, 08 Jun 2000 17:16:05 +1200
Links: << >>  << T >>  << A >>
Hello,
 I am looking for TTL device libraries (macros), ideally in CUPL, but
other HDL's would do..
 There must be dusty archives of these things somewhere..
CUPL comes with only about 30 TTL equiv macros, other systems 
may come with more..
TIA - Jim G.
Article: 22994
Subject: difference between fpga and epld
From: "John Smith" <jsmith@home.com>
Date: Thu, 08 Jun 2000 06:11:03 GMT
Links: << >>  << T >>  << A >>
Hi

What are the differences (if any) between an fpga and an epld?


Article: 22995
Subject: Re: Xilinx foundation Student Edition problem.
From: Klaus Falser <kfalser@durst.it>
Date: Thu, 08 Jun 2000 06:19:36 GMT
Links: << >>  << T >>  << A >>
In article <OYVt$EJ0$GA.311@cpmsnbbsa07>,
  "Seiya" <valid@email.address.com> wrote:
> Hey, I bought a copy of Xilinx Foundation Student Ed.
> and went through the registration process, received the stuff
> for license.dat. I then plugged it into the path it should be by the
command
> line parameter, and I am not able to run anything other than Xilinx
Design
> manager. (Even then, when it starts to init, it gives errors)
Generally the
> error is that there are no "server" lines in my license.dat  however,
this
> means very little to me other than "no im not going to work."
> Any ideas on what I might have missed?
>
> (I've done the web-support, but have yet to get a response)
> _seiya_ @ nergal.org (just remove spaces)
>
> for the spam bots, try abuse@fbi.gov
>
>

Which command line parameters?
You need to set up an environment variable LM_LICENSE_FILE, which
points to the license file.

Example :
set LM_LICENSE_FILE=C:\flexlm\license.dat

--
Klaus Falser
Durst Phototechnik AG
I-39042 Brixen


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22996
Subject: Re: XCV vs. XCV-E ?
From: "Olaf Birkeland" <Olaf_Birkeland@coldmail.com>
Date: Thu, 8 Jun 2000 09:30:43 +0200
Links: << >>  << T >>  << A >>
"Domagoj" <domagoj@engineer.com> wrote in message
news:8hmqcd$gq0$1@bagan.srce.hr...
> Hi,
>
> > The E series is fabricated on a .18 instead of a .25uM
> > process, uses 1.8 instead of 2.5 volt power supply, and does not
> > support 5V tolerant I/O.
> > Since this is largely a process shrink, the die size is
> > smaller for the Virtex E.
>
> I've assumed that , but it still doesn't make sense to me. Xilinx probably
> wants to squeeze every last drop of juice from plain old Virtex , so why
> would they sell better chips cheaper. This doesn't help them selling
> plain Virtex , except if someone needs 5V tolerant IOs.
>

When looking at the entire range of Xilinx parts, including
package/speed/temperature variations, I'm pretty sure they would have
preferred to have far fewer types. So they probably want to discourage use
of XCV by pricing XCV-E lower. And if someone complaints about XCV-E not
being 5V tolerant, they could always argue that you could spend some of the
savings on external level translators..... ;-)

Regards,
- Olaf


Article: 22997
Subject: Deficiencies in Actel 40mx tools?
From: "Frank Madison" <madisonfj@uswest.net>
Date: Thu, 8 Jun 2000 01:34:00 -0700
Links: << >>  << T >>  << A >>
I hope that this situation seems familiar to someone with more vhdl/fpga
experience
than I.  If it does, I would be interesting in seeing your opinion or
advice.

I have just completed the design of a data acquisition system that
incorporates two Actel
parts: a 40mx04 and a 42mx09.  The development tools that I used are the
"Actel DeskTop".
They include a subset of Synplicity.  I have found that Synplicity makes
only limited use of
the library macros in 40mx compilation as compared to 42mx compilations.

A specific example is that 42mx outputs will include and2, and2a, and and2b
while the 40mx
output will contain only and2.  and2a and and2b are both available in the
40mx macro
library, and they are implemented in a single cell.  An and2a is a 2-input
and gate with one of the
inputs inverted; the and2b has both inputs inverted.  To implement the
equivalent of an and2a
in 40mx, Synplicity creates an inverter and an and2.  The problem here is,
of course, that 2
cells instead of 1 are needed, and there is a greater propogation delay.

The back-end Actel "place and route" tools evidently take care of some, but
not all, of this
problem in post-systhesis optimization.  I have verified this by
synthesizing the same behavioral
VHDL code using both 40mx and 42mx compilers.  In instances where the 42mx
compiler
has output macros that are not available in the 40mx library, I edited the
structural output by
instantiating equivalent 40mx macros or macro combinations.  I then
processed both structural
outputs through the Actel back-end tools.  The code that was processed with
the 42mx Synplicity
compiler produced smaller and faster outputs.  The performance was verified
under simulation
(in ModelSim) and in actual hardware implementation.

Being relatively new to fpga design, I initially suspected that deficiencies
in the size and
performance of my designs were due to my limited experience with and
knowledge of the
process.  I scrutinized my work thoroughly before looking at the perfomance
of my tools.  Does
my assesment seem to be valid?  Have any of you had these experiences?  And,
if so, what
approach enabled you to overcome the problems?

Thanks for looking this over,

Frank Madison


Article: 22998
Subject: Re: Deficiencies in Actel 40mx tools?
From: rk <stellare@nospamplease.erols.com>
Date: Thu, 08 Jun 2000 06:59:38 -0400
Links: << >>  << T >>  << A >>
Frank Madison wrote:

> I hope that this situation seems familiar to someone with more vhdl/fpga
> experience than I.  If it does, I would be interesting in seeing your opinion
> or advice.

Not too familiar with this exact problem but interesting trouble you have.  :-)

=================================

> I have just completed the design of a data acquisition system that
> incorporates two Actel parts: a 40mx04 and a 42mx09.  The development tools
> that I used are the "Actel DeskTop".  They include a subset of Synplicity.  I
> have found that Synplicity makes only limited use of the library macros in
> 40mx compilation as compared to 42mx compilations.

Remember that the 40mx is really an Act 1 architecture and a 42mx is an Act 2
architecture.  The 40mx, for combinational logic, has a slightly different logic
element than the 42mx.  (the two muxes up front have separate selects in Act 1;
in Act 2, they give you an extra AND gate on one of the mux selects, making it a
bit better for up and down counters.  Often, the Act 1 element seems to be more
useful and powerful).

======================================

> A specific example is that 42mx outputs will include and2, and2a, and and2b
> while the 40mx output will contain only and2.  and2a and and2b are both
> available in the 40mx macro library, and they are implemented in a single
> cell.  An and2a is a 2-input and gate with one of the inputs inverted; the
> and2b has both inputs inverted.  To implement the equivalent of an and2a
> in 40mx, Synplicity creates an inverter and an and2.  The problem here is,
> of course, that 2 cells instead of 1 are needed, and there is a greater
> propogation delay.
>
> The back-end Actel "place and route" tools evidently take care of some, but
> not all, of this problem in post-systhesis optimization.  I have verified this
> by synthesizing the same behavioral VHDL code using both 40mx and 42mx
> compilers.  In instances where the 42mx compiler has output macros that are
> not available in the 40mx library, I edited the structural output by
> instantiating equivalent 40mx macros or macro combinations.  I then
> processed both structural outputs through the Actel back-end tools.  The code
> that was processed with the 42mx Synplicity compiler produced smaller and
> faster outputs.  The performance was verified under simulation
> (in ModelSim) and in actual hardware implementation.

There is an optimizer in the Combiner which tries to eliminate logic that is not
necessary and will handle a bunch of these things.  Another trick is to take the
output of the VHDL synthesizer and then run it through Actmap, in netlist
optimizer mode. It has been shown for some VHDL synthesizers that this will
produce very large performance gains; for others, it has almost no effect.  It
depends on the structure of the logic generated by the synthesizer.

==============================================

> Being relatively new to fpga design, I initially suspected that deficiencies
> in the size and performance of my designs were due to my limited experience
> with and knowledge of the process.  I scrutinized my work thoroughly before
> looking at the perfomance of my tools.  Does my assesment seem to be valid?
> Have any of you had these experiences?  And, if so, what approach enabled you
> to overcome the problems?

It seems that you have looked at this carefully and it does seem to be valid.
If you have some free time on your hands, you can try running the code using Act
3 and SX technologies.    Act 3 is the same as Act 2 with the addition of
another input to the S-module so that the clear signal isn't shared, helping
combinability.  The SX does have a more powerful logic module.

In one test that was run with a particular version of software, it was found
that setting the target to Act 3, with the less powerful logic module, got
better results, for a purely combinational design, than SX.  Why was this?  SX
was new and all the algorithms were not yet implemented in that version of the
software.  I suspect, but have no evidence, that this may be the source of your
problem.  Act 1/40MX are relatively small devices and as such have the least
suitability for HDL synthesis.  Also, the Act 1 module is different, by a bunch,
from Act 2 and Act 3.  So, given limited resources, one can suspect that
Synplicity, at least for the version that you have, simply did not put much time
in developing and optimizing their synthesis engine for Act 1 technology.  Did
the Synplicity folks have anything else to say about this?

Here are some options that may enable you to eliminate your problem.

     1. Like the old joke with the doctor, how to fix the problem when your
     arm hurts when you lift it funny, don't do that.  How about using the
     A1225A (or whatever the 42MX equivalent is) instead of the 40MX
     device, as these are comparable device densities.  This will actually
     help you out in board level simulations since they will both reference
     the same Actel models.

     2. Design with schematics.

     3. If you did not update to the latest version of software, use the
     freebie Actel VHDL synthesizer, Actmap.  For combinational logic, this
     seems to be the best tool for synthesis (although I most use it for
     Act 2/3/SX).

> Thanks for looking this over,

No problem, interesting story.

Have a good day,

----------------------------------------------------------------------
rk                               But Mother Nature, unlike Congress
stellar engineering, ltd.        and the press and even the space
stellare@erols.com.NOSPAM        workers, can't be bluffed.
Hi-Rel Digital Systems Design    -- James Oberg, 2000


Article: 22999
Subject: [JOB] Designer / FPGA
From: "IPSIS.news" <Commercial@ipsis.com>
Date: Thu, 8 Jun 2000 15:18:21 +0200
Links: << >>  << T >>  << A >>
POSTE : Ingénieur Électronicien Design Numérique

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