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# Messages from 23250

Article: 23250
Subject: Re: XILINX RAM Useless
From: David Hawke <dhawke@xilinx.com>
Date: Mon, 19 Jun 2000 12:21:32 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

This can be done in two ways.

1) Use 3.1i FPGA Editor and edit the RAM contents directly, instead of recompiling with a new
ucf INIT value, or,

2) Use XDL and change it in the xdl version by searching for the RAM block and changing the
INIT string...

Dave Hawke

eugenir wrote:

> How about any utility for configurating Virtex BLOCK RAM AFTER implementation? For example,
> to change program of internal microcontroller.

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begin:vcard
n:Hawke;David Hawke
tel;cell:(+44) 778 875 5002
tel;work:(+44) 870 7350 517
x-mozilla-html:TRUE
org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx">
version:2.1
email;internet:dhawke@xilinx.com
title:XILINX   Field Applications Engineer
x-mozilla-cpt:;2672
fn:David Hawke
end:vcard

--------------ABB395498BF5CF3F48035D92--


Article: 23251
Subject: Recherche =?iso-8859-1?Q?ing=E9nieur?= telecom/FPGA
From: "francois.hamon" <francois.hamon@sacet.com>
Date: Mon, 19 Jun 2000 13:19:05 +0000
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------B2E22B8607798811FDF91E9F
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

La SACET est un laboratoire privé de R&D en  transmissions numériques
sans fils implanté à Rennes (Bretagne).
Dans le cadre d'un projet de developpement de modem radio haut débit
pour le secteur de la défense, SACET recherche
un ingénieur expérimenté en conception fpga et ayant un background
telecom.
Les personnes interessées peuvent me retourner un mail afin de recevoir
des infos complémentaires.
Merci
Francois.

--------------B2E22B8607798811FDF91E9F
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begin:vcard
n:Hamon;François
x-mozilla-html:FALSE
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version:2.1
email;internet:francois.hamon@sacet.com
x-mozilla-cpt:;19264
fn:François Hamon
end:vcard

--------------B2E22B8607798811FDF91E9F--


Article: 23252
Subject: Does anyone know of a PC Card macro for Xilinx Spartan series?
From: jsloot@gtran.com (Jim)
Date: 19 Jun 2000 10:59:02 -0700
Links: << >>  << T >>  << A >>
Not the host side, but the card side. The one listed on the Xilinx site is out


Article: 23253
Subject: Re: 3.1i
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Mon, 19 Jun 2000 11:07:15 -0700
Links: << >>  << T >>  << A >>
Brian Drummond wrote in message
<4tsmks4nrtgp1u0h1nj0qkgcv5srh2gnpv@4ax.com>...
>On Fri, 16 Jun 2000 15:27:30 +0300, Utku Ozcan <ozcan@netas.com.tr>
>wrote:
>
>>erika_uk@my-deja.com wrote:
>>
>>> why the version 3.1i has been already issued ???????
>>
>>I think 3.1i is only being shipped to North America.
>>It might take 1 quarter to come to overseas.
>>
>>Utku
>
>It reached Scotland about a week ago, I guess the 3.1i wavefront should
>be somewhere around Austria by now
>
>;-)

Which means that it'll hit Tucson by January.

-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke


Article: 23254
Subject: Re: Hand soldering a PQ208 - It looks tough to do.
From: Terry Harris <terry.harris@iname.com>
Date: Mon, 19 Jun 2000 19:15:41 +0100
Links: << >>  << T >>  << A >>
"Larry Edington" <larrye_Spam_Me_Not_@centurytel.net> wrote:

>My method is tack 4 leads down with a fine tipped iron to hold the chip in
>place, or use SMT glue to hold it in position.
>
>Put a small bead of solder paste around the complete part at the far end of
>the leads ( away from the component body )
>
>Use a hot air iron to melt the paste. Done deal.

I have also done this with and think it is by far the
quickest/neatest/easiest way.

I pre-tin the pads, I don't think I could get anything like a consistent
bead of solder paste on them and would be concerned about solder balls
being stuck behind the legs (and being able to see them).

Solder paste is quite good for tinning the pads its runny flux seems to be
active at lower temperatures than rosin cored solder. Make sure there is
some flux on the part legs.

Place the part very carfully on the pads, it will tend to slip off becuase
of the solder beads on the pads. Hold it down with firm pressure from
tweezers or something in the middle of the part then run round the legs
with hot air - a mini reflow system.

I use a hot 'air' nozzle from a portable gas soldering iron. I think it
works significantly better than hot air because the exhaust gasses contain
less (little?) oxygen and tend not to oxidise the legs or solder.

Cheers, Terry.

Article: 23255
Subject: Re: How to cut the power disipation down ?
From: "Domagoj" <domagoj@engineer.com>
Date: Mon, 19 Jun 2000 21:08:45 +0200
Links: << >>  << T >>  << A >>
Hi Peter,

Peter Alfke <palfke@earthlink.net> wrote in message

Thanks for the answer. I have some extra questions:

> Then there are "dirty" tricks like clock gating that do miracles, but
> require a deeper understanding of clock delay and hold-time issues.

I hear so often about clock gating and all the "tricks" but I don't have
deeper knowledge about, so where I should look for some articles/books
which could point me in right direction how to design clock gated circuits.

> In general:
> Any node that moves consumes power. Make sure that there is no
> unnecessary movement.

Node that moves ?? I don't understand what do you mean by that.

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------


Article: 23256
Subject: Re: Problem copying text from the Spartan II data sheet
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 19 Jun 2000 20:40:42 +0100
Links: << >>  << T >>  << A >>


John Larkin wrote:

>
> I will *not* install special viewers or plugins everytime somebody sends
> me a CD... Windows is fragile enough without adding this level of chaos.
>
> John

Not to mention the possibility of viruses. For that reason I refused to
install the 2.1i documentation brower when it asked for extra Java
permissions - just copied the PDF files from the CD. It didn't help that the
so-called security certificate timed out at the end of August and we didn't
get our 2.1i copy until near the end of Sept.


Article: 23257
Subject: Wanted: Xilinx VirtexE
From: "Younes Leroul" <leroul@worldonline.dk>
Date: Mon, 19 Jun 2000 20:06:11 GMT
Links: << >>  << T >>  << A >>
Since I am in desperate need of a certain Xilinx VirtexE chip and Xilinx
cannot help me for at least 3 weeks (I had already been waiting for 3 weeks
before they told me, I had to go for a lower speed grade), I try this forum
as a last resort:
I need only one (1)  XCV1000E-7 BG560, but I need it yesterday. Notice it is
speed grade 7 (well 8 is also OK!). If, for some reason you should have a
(almost) no object.

Younès Leroul


Article: 23258
Subject: cpld
From: zee <zkshan1@yahoo.com>
Date: Mon, 19 Jun 2000 13:38:25 -0700
Links: << >>  << T >>  << A >>
can anybody tell me "what is the differnce b/w a
Programmable Logic Device and a Microcontroller.
Which of them is powerful.

Article: 23259
Subject: Re: cpld
From: "Alun" <alun101@DELETEtesco.net>
Date: Mon, 19 Jun 2000 22:30:03 +0100
Links: << >>  << T >>  << A >>

zee <zkshan1@yahoo.com> wrote in message news:ee6ccf0.-1@WebX.sUN8CHnE...
> can anybody tell me "what is the differnce b/w a
> Programmable Logic Device and a Microcontroller.
> Which of them is powerful.

Mr Andraka, I believe you know the answer to this one.

Alun


Article: 23260
Subject: Re: How to cut the power disipation down ?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 19 Jun 2000 15:06:46 -0700
Links: << >>  << T >>  << A >>


Domagoj wrote:

> Node that moves ?? I don't understand what do you mean by that.
>

Mayb that's bit colloquial:
make that: ...any node that changes its voltage... ( moves up and down in
voltage)

Peter


Article: 23261
Subject: Re: Xilinx Foundation 2.1 error
From: "Bryan Jones" <bryan@rice.edu>
Date: Mon, 19 Jun 2000 15:55:34 -0700
Links: << >>  << T >>  << A >>
Yall,

I'm still trying to get the hang of instantiating Xilinx macros/primitives in my VHDL designs.  I've gotting IBUF/OBUF/BUFG to work, but am now having trouble with ADSU16 on a Virtex part.  Has anyone else gotten this to work?  My code looks something like this:

port (
a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
ci: in std_logic;
co: out std_logic;
ofl: out std_logic;
s: out std_logic_vector(15 downto 0)
);
end component;

Then, I instantiate it as usual:

a, b, ci, co, ofl, s);

However, when I Implement the design, ngdbuild complains that "logical block adsu16_1 of type adsu16 is unexapnded."  Since this is a standard Virtex macro, and the virtex library is part of my project, shouldn't this work?

Thanks for the help!

Bryan Jones
bryan@rice.edu

Article: 23262
Subject: Re: cpld
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 20 Jun 2000 11:46:13 +1200
Links: << >>  << T >>  << A >>
zee wrote:
>
> can anybody tell me "what is the differnce b/w a
> Programmable Logic Device and a Microcontroller.
> Which of them is powerful.

That's easy - both together is the (most) powerful.

Microcontroller fetch opcodes, and decode/execute them one at
a time. So, they are well suited to human interface tasks, and
many control applications, but sub-mS, and certainly sub uS
responses are very hard to achieve.

PLDs have hardwired logic, so can be in 'many places at once',
and are most comfortable in the sub uS world, and are driving
down to the low nS end of the scale.

Between the mS and uS worlds, there is some overlap.

So, they are quite complementary, and that is why many large/new
FPGAs promote uC soft/hard cores, and products from Triscend and
Atmel already exist that have 8 bit uC, with ProgLogic on one die.

Our web site has more info, on using SPLDs as uC expansion, and
that will give you some more idea of the 'task split' between
the two.

-jg

--
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 23263
Subject: Re: Problem copying text from the Spartan II data sheet
From: John Larkin <jjlarkin@highlandSnipSniptechnology.com>
Date: Mon, 19 Jun 2000 19:05:05 -0700
Links: << >>  << T >>  << A >>
On Mon, 19 Jun 2000 20:40:42 +0100, Rick Filipkiewicz <rick@algor.co.uk>
wrote:

|
|
|John Larkin wrote:
|
|>
|> I will *not* install special viewers or plugins everytime somebody sends
|> me a CD... Windows is fragile enough without adding this level of chaos.
|>
|> John
|
|Not to mention the possibility of viruses. For that reason I refused to
|install the 2.1i documentation brower when it asked for extra Java
|permissions - just copied the PDF files from the CD. It didn't help that the
|so-called security certificate timed out at the end of August and we didn't
|get our 2.1i copy until near the end of Sept.

Rick,

the idea of FPGA software 'expiring' is terrifying. What do we do three
years from now when we have to upgrade or fix a design, the part is no
longer supported, and the tools have expired? WHY would any part vendor
design tools that expire? Makes no sense to me.

John


Article: 23264
Subject: Re: How to cut the power disipation down ?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 19 Jun 2000 22:25:45 -0400
Links: << >>  << T >>  << A >>
I guess I was thinking that using the CE vs. might save power rather
than asking if it used more power. But it sounds like the two methods
are equivalent.

From my past experiences, if you are doing HDL design, it can be hard to
control whether the CE is used or not. Or in some cases like with FPGA
Express which is the packaged VHDL compiler in the Foundation package,
the CE can be overused. I found that if you put any type of conditional
logic (if statements) inside the "if (risingedge(xxx))...endif"
statement it would turn those other if statements in logic feeding the
CE input. So it was not always easy to control when the CE got used or
not.

So if there is little difference in power consumption, I will structure
all of my code to not use the CE unless I see a clear advantage in speed
or LUT usage.

Peter Alfke said in an email...
> CE-inputs in Xilinx FPGAs really do nothing to the clock. They control
> a multiplexer in front of the D input, so that the flip-flop loads its
> existing value. Thus there is no advantage in implementing CE in a LUT
> (and CE saves you either one or two LUT inputs ).
>
> XC4000, Spartan, and Virtex global clocks ar distributed along a
> horizontal "spine" with "ribs" going up and down in each column. The
> software is smart enough to drive a rib only if there is a clock
> destination in this column.  Vertically aligning register etc banks can
> thus save power, and the carry structure automatically enforces that
> kind of alignment for counters and accumulators.
>
> Peter Alfke, Xilinx Applications
> ================================================
> Rickman wrote:
>
> > On this issue, I have never figured out about using the CE vs. gating
> > the input with the LUT. Is there a difference in power consumption in
> > the two cases? That is does a FF use any more power if it is enabled,
> > but the input is the same as the current output so that it does not
> > change state?

--

Rick Collins

rick.collins@XYarius.com

removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 23265
Subject: Re: Problem copying text from the Spartan II data sheet
From: Rickman <spamgoeshere4@yahoo.com>
Date: Mon, 19 Jun 2000 22:36:59 -0400
Links: << >>  << T >>  << A >>
John Larkin wrote:
> On Mon, 19 Jun 2000 20:40:42 +0100, Rick Filipkiewicz <rick@algor.co.uk>
> wrote:
> |John Larkin wrote:
> |> I will *not* install special viewers or plugins everytime somebody sends
> |> me a CD... Windows is fragile enough without adding this level of chaos.
> |>
> |> John
> |
> |Not to mention the possibility of viruses. For that reason I refused to
> |install the 2.1i documentation brower when it asked for extra Java
> |permissions - just copied the PDF files from the CD. It didn't help that the
> |so-called security certificate timed out at the end of August and we didn't
> |get our 2.1i copy until near the end of Sept.
>
> Rick,
>
> the idea of FPGA software 'expiring' is terrifying. What do we do three
> years from now when we have to upgrade or fix a design, the part is no
> longer supported, and the tools have expired? WHY would any part vendor
> design tools that expire? Makes no sense to me.
>
> John

I don't think the software "expired" in either sense of the word. The
software certificate is a cerification that the software is genuine and
has not been tampered with. For example, it can't contain a virus. The
ceritificates have an expiration date to allow for the possibility that
they could be cracked after some amount of time. So they are
periodically changed, just like a password should be.

On the other hand, the new license from Xilinx says you only rent the
don't know that the tools stop working.

This may be a moot point. If you really want to get support on software
that is three years old, you are in trouble. I believe that all of the
FPGA vendors are pretty reluctant to support old tools and many don't
provide support for really old (>3 or so years) parts.

I don't want to step on any toes here, so you can ask your FAE or
true statement that you will be hard pressed to use the new 3.1 toolset
to work XC4000 designs, for example. And of course you will get nothing
but blank stares if you ask for support on the F5.x toolset (or whatever
the last pre-Mx.x release was).

--

Rick Collins

rick.collins@XYarius.com

removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 23266
Subject: Re: Problem copying text from the Spartan II data sheet
Date: Tue, 20 Jun 2000 04:20:26 GMT
Links: << >>  << T >>  << A >>


Rickman wrote:

> On the other hand, the new license from Xilinx says you only rent the
> tools for a year. Then you must pay up or your license is dead. But I
> don't know that the tools stop working.

They do NOT stop working.

Peter Alfke

>


Article: 23267
Subject: Re: Xilinx config over parallel port ?
From: Robert Binkley <robert.binkley@xilinx.com>
Date: Mon, 19 Jun 2000 22:26:09 -0700
Links: << >>  << T >>  << A >>
GB wrote:

> I don't recall the App Note number, but there is an XAPP###
> on the Xilinx web site which includes source code for
> configuring an FPGA over the parallel port (in DOS).  The
> app note title is something like "Xilinx FPGA Configuration
> using 8051 microcontroller".

<snip>
Xilinx In-System Programming Using an Embedded Microcontroller
http://support.xilinx.com/apps/xapp.htm#xapp058

There is example code available that can be touched up and compiled for
windows to drive the parallel port.  However, the interface is serial
(JTAG) and assumes you will save your data in xilinx binary svf (xsvf).

Robert


Article: 23268
Subject: Re: Designing a narrowband bandpass filter to pass a tone (analog
From: Dominique SZYMIK <szymik@nospam.univ-lille1.fr>
Date: Tue, 20 Jun 2000 08:33:28 +0200
Links: << >>  << T >>  << A >>
Hello,

To your problem there might be two basic solutions:

- A PLL
To lock to a single tone buried in noise you have to use a PLL with an
analog
phase comparator (analog multiplier, analog switch or a mixer).
The problem with a carrier buried in a populated spectrum is you can't
pass
it through limiters to square it, the useful signal would disappear
(capture
effect). Thence you must ensure the whole input signal (wanted and
unwanted)
is kept in the linear zone of the phase comparator.
In that type of PLL to get a lock without special circuits you must have
the
command range of vco within loop banwidth (around 100Hz would be fine in
your
case).
The obvious choice for vco would be a VCXO (voltage controlled crystal
oscillator) the command range and stability are just fine.
You can do a Colpitts vcxo with a varicap a (parallel resonant) crystal
one inverting gate and some capacitors.

- A crystal filter
First thing to compute in a bandpass filter is the loaded Q=dF/Fo.
Here Q=1.5 E6/500 = 6000. There is a rule of thumb to know if your
filter
could be synthetized, Qc of components > 10*Q with a butterworth or Qc
of
components > 10*Q with an elliptical type...
Inductors are ruled out. You must use quartz crystals.
For mention crystal elliptic filters does exist but those can only be
designed by crystal manufacturers.
Let us try to keep simple. You can use a single crystal between input
and
output, only you need to cancel the parallel capacitance of the crystal
with a capacitor of the same value between load and a source of opposite
phase (ct transformer). You just measure the crystal // cap with a
multimeter.
if one crystal is not enough you can add a second cell back to back.
The frequency of the crystals must specified for serial resonance.
Also you must add a wide band LC filter to cut out the spurious
responses of
the crystals.

Those are only guidelines you may find many more falltraps I think.
On PLLs you can find useful ANs at Motorola NS Philips etc...
crystal filter in a ARRL book I think.
Look also at crystal manufacturers sites KVG, Tele Quarz etc...

d.

Nestor wrote:
>
> Thanks for everyone's replies.
>
> Here are some details of what I wish to do using the narrowband BPF:
>
> 1) I would like to synchronize to a tone of 1.5625MHz that is
> generated from another node on a network.  I do not have access to the
> transmitting node, and the tone will always be present on the line.
> 2) Because of noise on the channel, I need to perform very narrowband
> filtering so that I may be able to distinguish and lock to the tone
> only with a Phase-Locked Loop (PLL).
> 3) I am thinking of at least a 35dB out-of-band rejection, and a
> passband (3dB frequencies) in say +/-150ppm % of the center of
> 1.5625MHz (or ~+/-250Hz relative to the center).
>
> Because I am fairly new to analog design I am not sure what would be
> the best approach: elliptic filters, crystal/resonator filters?
>
> Also, if a single component solution does not exist, do you know of a
> good reference or application note which explains how to build my own
> narrowband BPF?  I have a good reference for elliptic filters, but not
> for the other kinds.
>
> Thanks in advance for any further suggestions.
>
> Nestor

Article: 23269
Subject: Re: FIFO design
From: Jamil Khatib <Khatib@opencores.org>
Date: Tue, 20 Jun 2000 09:22:43 +0200
Links: << >>  << T >>  << A >>


> Great site , man . As I understand, ADD_WIDTH (2**ADD_WIDTH) defines the
> length of the FIFO, and WIDTH defines width. Are all the architectures
> working ? In FIFO_v7 you used " ADD_WIDTH : integer := 4;" in component
> DPMEM. In all other architectures you used  "ADD_WIDTH : integer := 4" . Why
> the change ?

Yes the ADD_WIDTH defines the length of the fifo and WIDTH the width (no. of
bits"
regarding the last change it is not a problem I used it to synthesize the code
on a small FPGA and forgot to reupdate the code.

You can also get the latest update from the OpenCores CVS
you will find test bench and test vectors that you can modify to test the core

> Is the code synthesizable ?

The last architecture should be synthesizable FIFO_V7 the others may not.
As I remeber all versions are working but with different size and speed but I
prefer to use only the last arch. and if you are able to get the last files from
the cvs

please feel free to modify the code and test it and let me know with your
changes and test results. Also if you implement it on HW

Regards,
Jamil Khatib
OpenCores org
http://www.opencores.org

>
> regards,
> Dave.
>
> In article <39487175.46DFC43C@yahoo.com>,
>   khatib@ieee.org wrote:
> > Try to visit my memory cores page at
> > http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html
> > You can also check http://www.opencores.org and http://www.free-ip.com
> > You can find Free Open design cores
> >
> > Let me know if you are going to use my FIFO core
> >
> > Regards
> > Jamil Khatib
> > OpenCores Organization
> >
> >
> > > Hi,
> > >
> > > Can somebody give me an example of FIFO design with width >1 ?
> > > If it is parameterizable, even better.
> > > VHDL is preferable, but Verilog is fine too.
> > >
> > > regards,
> > > Dave.
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> >
>
> Sent via Deja.com http://www.deja.com/


Article: 23270
From: Steven Sanders <sanders@imec.be>
Date: Tue, 20 Jun 2000 11:01:44 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------A57626EBAB50B39199787FC1
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello,

When I try to access the XC4000X library in VHDL by this syntax
:"library xc4000x;", I get following error message:

Library logical name XC4000X is not mapped to a host directory.

although the library is clearly added and specified in the project.

Any ideas?

Steven.

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Article: 23271
Subject: Re: Wanted: Xilinx VirtexE
From: Ray Andraka <ray@andraka.com>
Date: Tue, 20 Jun 2000 11:34:47 GMT
Links: << >>  << T >>  << A >>
What are you doing that requires a -7, or is it just to make up for less than
optimal design???

Younes Leroul wrote:

> Since I am in desperate need of a certain Xilinx VirtexE chip and Xilinx
> cannot help me for at least 3 weeks (I had already been waiting for 3 weeks
> before they told me, I had to go for a lower speed grade), I try this forum
> as a last resort:
> I need only one (1)  XCV1000E-7 BG560, but I need it yesterday. Notice it is
> speed grade 7 (well 8 is also OK!). If, for some reason you should have a
> (almost) no object.
>
> Younès Leroul

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com  or http://www.fpga-guru.com


Article: 23272
Subject: Single Floating point adder ansd multiplier core
From: Steven Derrien <sderrien@irisa.fr>
Date: Tue, 20 Jun 2000 15:52:11 +0200
Links: << >>  << T >>  << A >>
Hi,

I was wondering if anyone had heard about some free cores for flotaing
point operators such as addition, multiplication, divission  in VHDL or
Edif targeted over Xilinx Virtex series ?

Thanks

Steven


Article: 23273
Subject: Re: Xilinx Foundation 2.1 error
From: "Bryan Jones" <bryan@rice.edu>
Date: Tue, 20 Jun 2000 08:09:09 -0700
Links: << >>  << T >>  << A >>
FYI, I got a couple of helpful responses from Dr. Dave Van den Bout (devb@xess.com) and Stan Ramsden (sramsden@hoflink.com).  With their thoughts, and a little more fooling around, I fixed the problem by doing the following.  These instructions are for the Foundation Express 2.1i tools:

1. Open the Virtex library by double-clicking on it (I'm using a Virtex part), and copy the desired macro (adsu16) to my local project's library.

2. Right-click on the desired macro in the local library, then select Export Netlist | EDIF.

3. Now, re-run the Implement process, and everything works!

Thanks for the help...

Bryan Jones

bryan@rice.edu

Article: 23274
Subject: Powerup problem to 9500XL part @ -40 deg
From: Eirik Esp <eirik.n.esp@lmco.com>
Date: Tue, 20 Jun 2000 11:25:36 -0400
Links: << >>  << T >>  << A >>
Technically a CPLD problem, but I thought to post it here anyway.  I am
having a problem with a XC9572XL @ -40 degrees.  It seems that when I
cycle power, the JTAG controller becomes confused and takes over the
chip.  The only way I can reset the JTAG controller is to power down and
up at room temp.  Once the JTAG controller is confused, if I warm the
part to room, it still misbehaves (TAP controller is in control).  I do
have a switching power supply on the board, so the +5v starts coming up
about 6 ms before the 3.3v, but if I apply a cap between the 3.3 and +5
so the 3.3 starts coming up with the +5v, it still doesn't fix it.  I
tried shorting the TCK directly to gnd and through a 1.1K pulldown, and
I tied the TMS to +5 through 4.7K and to 3.3 through a wire.  I am
really starting the suspect a ground bounce problem, or the TAP
controller in the chip itself.  Anyone else have similar experiences the
the 9500XL family at cold?  If so, how did you address it?  Also, anyone
know how Xilinx tests the industrial rated parts at cold?  Any chance
the JTAG controller is not tested?  If I access the JTAG port in the
right way at cold, the parts seems to come back to life, so maybe if the
testing uses the JTAG port, then it wouldn't demonstrate the fault we
are experiencing?