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Messages from 24475

Article: 24475
Subject: ASIC SCAN TEST
From: Austin Tempany <ATempany@iss-dsp.com>
Date: Thu, 10 Aug 2000 13:46:43 +0100
Links: << >>  << T >>  << A >>

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Hi,
Could someone please explain the whole process of Scan Test with
reference to ASIC implementation.
Apparently during Scan Testing (if the implementation has memory) the
memory blocks are bypassed while the remaining circuitry is Scan Tested.

Thanks in Advance.
Austin

--
------------------------------------------------------------
Integrated Silicon Systems Ltd.       Tel: +44 28 90 50 4000
50 Malone Road                        Fax: +44 28 90 50 4001
Belfast  BT9 5BS                      Web:   www.iss-dsp.com


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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<br>Could someone please explain the whole process of <u>Scan Test</u>
with reference to ASIC implementation.
<br>Apparently during Scan Testing (if the implementation has memory) the
memory blocks are bypassed while the remaining circuitry is Scan Tested.
<p>Thanks in Advance.
<br>Austin
<p>--
<br>------------------------------------------------------------
<br>Integrated Silicon Systems Ltd.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Tel: +44 28 90 50 4000
<br>50 Malone Road&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Fax: +44 28 90 50 4001
<br>Belfast&nbsp; BT9 5BS&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Web:&nbsp;&nbsp; www.iss-dsp.com
<br>&nbsp;</html>

--------------000E2A3D41DC22DA2D3C5CDC--

Article: 24476
Subject: Gigabit Ethernet controller
From: "Ron" <skalarv@usa.net>
Date: Thu, 10 Aug 2000 15:22:27 +0200
Links: << >>  << T >>  << A >>
I'm looking 4 vhdl code which impliment interface to Gigabit Ethernet
controller
 (LsiLogic 8101, Xaqti 11800),any suggestions ?

Regards
Ron


Article: 24477
Subject: Xilinx of Linux Howto Updated
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Thu, 10 Aug 2000 11:31:09 -0400
Links: << >>  << T >>  << A >>
The Xilinx on Linux howto has been updated. There are new scripts which
handle the changes in Wine that were introduced in June.

http://www.polybus.com/xilinx_on_linux.html
Article: 24478
Subject: 2001 Reed-Muller Workshop CFP
From: Mitch Thornton <mitch@ece.msstate.edu>
Date: Thu, 10 Aug 2000 10:52:45 -0500
Links: << >>  << T >>  << A >>

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5th International Reed-Muller Workshop
          (Reed-Muller 2001)

Mississippi State University
Starkville, Mississippi
August 10-11, 2001

http://www.ece.msstate.edu/reed-muller

reed-muller@ece.msstate.edu

This workshop focuses on the application of new techniques in the
representation
and realization of discrete functions.  AND-XOR based representations
are
often simpler than AND-OR based representations, and have other
important
properties. Decision diagrams are being extensively studied, and have
offered
powerful new techniques for verification and synthesis.  The goal of the
workshop
is to bring together researchers in these and related fields to provide
a forum for
discussion and presentation of new approaches and results. The first
workshop was held in September 1993, in Hamburg, the second in August
1995,
in Tokyo, the third in September 1997, in Oxford and the fourth in
August 1999 in
Victoria, B.C.

A non-restrictive list of interests includes the following topics:

-Graph-based representation of logic functions:
  Binary decision diagrams,
  Functional decision diagrams etc
-XOR-based logic synthesis
-Reed-Muller expressions, Kronecker expressions, Exclusive-OR,
            Sum-of-Products Expressions (ESOPs), Multi-level circuits
-Spectral techniques
-New representations for discrete functions
-AND-OR vs. AND-XOR complexity
-Easily testable circuits using XORs
-Implementation in silicon (FPLDs, FPGAs, ...)
-Applications, both inside and outside circuit design

Authors are invited to submit draft papers not exceeding 20 pages by
April
1, 2001.   Each submission should be accompanied by a statement that if
the
paper is accepted the author(s) will present it at the workshop.
Notifications
of acceptance will be sent by 1 June, 2001. A workshop handout will be
distributed to the workshop attendees, and it is planned to publish
selected
papers in a more widely distributed form. Camera-ready papers are due 15
July
2001.

Submissions should be sent to the RM2001 Workshop Chair, Mitch
Thornton, to be received on or before April 1, 2001. Submissions should
be
sent by e-mail to reed-muller@ece.msstate.edu as attached
postscript or PDF files if possible.   If necessary, mailed submissions
(5 copies) will be accepted.  Please do not submit papers
by fax. All submissions should be formatted for 8.5 by 11 inch paper.


Program Committee:

Jon Butler, Naval Postgraduate School, U.S.A.
Gerhard Dueck, University of New Brunswick, Canada
Masahiro Fujita, University of Tokyo, Japan
Udo Kebschull, University of Leipzig, Germany
Parag Lala, University of Arkansas, USA
Christoph Meinel, University of Trier, Germany
D. Michael Miller, University of Victoria, Canada
Marek A Perkowski, Portland State University, Oregon, USA
Tsutomu Sasao, Kyushu Institute of Technology, Iizuks, Japan
Christoph Scholl, University of Freiburg, Germany

Organization:

Workshop Chair: Mitch Thornton, Mississippi State University, USA
Workshop Co-Chair: Rolf Drechsler, Siemens Corp., Munich, Germany
Local Arrangements: Bob Reese, Mississippi State University, USA
Treasurer: Jim Harden, Mississippi State University, USA

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
&nbsp;
<br>5th International Reed-Muller Workshop
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (Reed-Muller
2001)
<p>Mississippi State University
<br>Starkville, Mississippi
<br>August 10-11, 2001
<p><a href="http://www.ece.msstate.edu/reed-muller">http://www.ece.msstate.edu/reed-muller</a>
<p><a href="mailto:reed-muller@ece.msstate.edu">reed-muller@ece.msstate.edu</a>
<p>This workshop focuses on the application of new techniques in the representation
<br>and realization of discrete functions.&nbsp; AND-XOR based representations
are
<br>often simpler than AND-OR based representations, and have other important
<br>properties. Decision diagrams are being extensively studied, and have
offered
<br>powerful new techniques for verification and synthesis.&nbsp; The goal
of the workshop
<br>is to bring together researchers in these and related fields to provide
a forum for
<br>discussion and presentation of new approaches and results. The first
<br>workshop was held in September 1993, in Hamburg, the second in August
1995,
<br>in Tokyo, the third in September 1997, in Oxford and the fourth in
August 1999 in
<br>Victoria, B.C.
<p>A non-restrictive list of interests includes the following topics:
<p>-Graph-based representation of logic functions:
<br>&nbsp; Binary decision diagrams,
<br>&nbsp; Functional decision diagrams etc
<br>-XOR-based logic synthesis
<br>-Reed-Muller expressions, Kronecker expressions, Exclusive-OR,
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Sum-of-Products Expressions (ESOPs), Multi-level circuits
<br>-Spectral techniques
<br>-New representations for discrete functions
<br>-AND-OR vs. AND-XOR complexity
<br>-Easily testable circuits using XORs
<br>-Implementation in silicon (FPLDs, FPGAs, ...)
<br>-Applications, both inside and outside circuit design
<p>Authors are invited to submit draft papers not exceeding 20 pages by
April
<br>1, 2001.&nbsp;&nbsp; Each submission should be accompanied by a statement
that if the
<br>paper is accepted the author(s) will present it at the workshop. Notifications
<br>of acceptance will be sent by 1 June, 2001. A workshop handout will
be
<br>distributed to the workshop attendees, and it is planned to publish
selected
<br>papers in a more widely distributed form. Camera-ready papers are due
15 July
<br>2001.
<p>Submissions should be sent to the RM2001 Workshop Chair, Mitch
<br>Thornton, to be received on or before April 1, 2001. Submissions should
be
<br>sent by e-mail to reed-muller@ece.msstate.edu as attached
<br>postscript or PDF files if possible.&nbsp;&nbsp; If necessary, mailed
submissions
<br>(5 copies) will be accepted.&nbsp; Please do not submit papers
<br>by fax. All submissions should be formatted for 8.5 by 11 inch paper.
<br>&nbsp;
<p>Program Committee:
<p>Jon Butler, Naval Postgraduate School, U.S.A.
<br>Gerhard Dueck, University of New Brunswick, Canada
<br>Masahiro Fujita, University of Tokyo, Japan
<br>Udo Kebschull, University of Leipzig, Germany
<br>Parag Lala, University of Arkansas, USA
<br>Christoph Meinel, University of Trier, Germany
<br>D. Michael Miller, University of Victoria, Canada
<br>Marek A Perkowski, Portland State University, Oregon, USA
<br>Tsutomu Sasao, Kyushu Institute of Technology, Iizuks, Japan
<br>Christoph Scholl, University of Freiburg, Germany
<p>Organization:
<p>Workshop Chair: Mitch Thornton, Mississippi State University, USA
<br>Workshop Co-Chair: Rolf Drechsler, Siemens Corp., Munich, Germany
<br>Local Arrangements: Bob Reese, Mississippi State University, USA
<br>Treasurer: Jim Harden, Mississippi State University, USA</html>

--------------766197F39A6AEE699EBF06FB--

Article: 24479
Subject: Re: some basic rules on FPGA design
From: Ray Andraka <ray@andraka.com>
Date: Thu, 10 Aug 2000 17:09:48 GMT
Links: << >>  << T >>  << A >>
They are listed in
http://www.andraka.com/highperf.htm

shoran@my-deja.com wrote:
> 
> Though FPGA designs are complicate, for a good design there must be
> some basic rules you should abide by, such as synchronous design,
> pipeline design etc. All those methods could optisize your design. So
> could you professionals tell me more basic rules?
> 
> Thanks very much in advance.
> 
> Cheers
> 
> Shoran
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group,
Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or
http://www.fpga-guru.com
Article: 24480
Subject: Viewlogic to Orcad conversion
From: Jean-Marie Bussat <bussat_NOSPAM_@cern.ch>
Date: Thu, 10 Aug 2000 19:17:36 +0200
Links: << >>  << T >>  << A >>
Hello,

I'm looking for somebody who would be so kind to translate for
me some schematics made with ViewDraw (Viewlogic suite) into
schematics readable from Orcad (I'm asking for Orcad but it
can be Protel or maybe Edif or something portable - Orcad has
an evaluation version for a conversion tool but you the
viewlogic libraries are needed and so, I'm unable to use it).

The files to convert are from the xproz project and are in the
following zip archive.

ftp://137.193.64.130/pub/xproz/xproz.zip

I would like to understand how they made their system and since
the documentation is in german (and doesn't include schematics),
I need the schematics (which are always understandable whatever
language your are speaking).

Thanks in advance for your help.

Best regards,
	Jean-Marie Bussat



P.S. Please remove _NOSPAM_ from my address to reply - Thanks
-- 
 +------------------------------------------------------------+
 | Jean-Marie Bussat - Dept. of physics, Princeton University |
 | CERN/EP - Bldg. 15-S-012 - CH-1211 GENEVA 23 - Switzerland |
 | Email: bussat_NOSPAM_@cern.ch                              |
 | Tel: (41 22) 767 32 41              Fax: (41 22) 767 32 41 |
 +------------------------------------------------------------+
Article: 24481
Subject: Re: Can i see Gate-delay and Interconnection-delay of circuit on FPGA
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 10 Aug 2000 10:26:20 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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  I'd say DO NOT DO THIS for a production design you expect
to have to build for any extended period of time. I think it is
still true that Xilinx generally does not guarantee minimum
timings for any part, only maximum delays. Over the lifetime
of a part family, die shrinks allow them to use smaller parts
(that will run faster, have shorter logic and routing delays)
in place of their original design. Relative delays can change
when they do this, and unless your circuit design is totally
immune to these changes you can run into trouble.

Asynchronous design is attractive for the speed improvements
and circuit size reductions that can result, but I don't know
of any proven, commercially available tool set to make more
than the simplest async designs bulletproof to expected
FPGA variations.

Ray Andraka wrote:
> 
> This is not something the faint of heart
> would want to do in an FPGA.  If you are
> going to do it, you'll want to
> structurally instantiate your design
> rather than synthesize it, and you'll
> want to do at least the placement by
> hand to make sure the routing doesn't
> kill you.  You may even find that you
> need to do the routing by hand as well.
> For the delays, you need to look at the
> post PAR results, as the stuff from the
> synthesizer is only an estimate based on
> the logic inferred.  Your best path for
> success will have you spending a
> considerable amount of time in the
> timing anaylzer and FPGA editor tools..
> 
> Phunjapa Ruangsinsup wrote:
> >
> > I must design asynchronous circuit on FPGA and I must know Gate-delay and
> > interconnection delay for create Complete signal check (the signal which
> > have delay longest than another in circuit). I design by RTL-VHDL code and
> > synthesis by Xilinx Foundation 2.1i, my synthesis output is VHDL and SDF
> > code. So can i use delay report from SDF code to be a Gate-delay?? and Where
> > i can see interconection-delay of each signal??
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group,
> Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or
> http://www.fpga-guru.com
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tel;work:858-320-4102
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org:Visicom;Imaging Products
adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA
version:2.1
email;internet:jsmith@visicom.com
title:Principal Engineer
x-mozilla-cpt:;30864
fn:John L. Smith
end:vcard

--------------D31F838105E9EBE39E9F2D5E--

Article: 24482
Subject: Re: ASIC SCAN TEST
From: iglasner@my-deja.com
Date: Thu, 10 Aug 2000 17:38:36 GMT
Links: << >>  << T >>  << A >>
Hi,

  Scan test basicly mean that the FF in your design are connected in
serial one after the other and that through a scan_in you enter vectors
and read them through scan_out, and of course there will be also some
sort of scan_en that will change the FF to this serial connection
instead of your logic, meaning basicly that each scan FF have a mux of
2->1 in the input.

in order to increase the speed and shorten the tester time you might
have few scan chain in parallel as well as almost always if you have
different clock domain you will have at least one scan chain for each
clock domain.

in respect to memorey they are not in the scan as you mention and they
are tested using bist. the bist algoritum should be given to you from
the vendor as it is not only simple runing 1 etc but have also to do
with the memorey architucture, which you have no idea on it as for
example 1K bit might be arrnage as 1Kx1 or 128x8 and so on and the way
it is build have effect on some of the testing.

lastly the scan insertion is useually done in late stage of the Asic
process so you might want to give a "harder" constrain on your timing
to compenstae the "future" mux you will have when the scan insertion
will take place as otherwise you might get some timing problem after
the scan insertion.

have a nice day

   Illan

In article <3992A433.545B4451@iss-dsp.com>,
  Austin Tempany <ATempany@iss-dsp.com> wrote:
>
> --------------000E2A3D41DC22DA2D3C5CDC
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> Hi,
> Could someone please explain the whole process of Scan Test with
> reference to ASIC implementation.
> Apparently during Scan Testing (if the implementation has memory) the
> memory blocks are bypassed while the remaining circuitry is Scan
Tested.
>
> Thanks in Advance.
> Austin
>
> --
> ------------------------------------------------------------
> Integrated Silicon Systems Ltd.       Tel: +44 28 90 50 4000
> 50 Malone Road                        Fax: +44 28 90 50 4001
> Belfast  BT9 5BS                      Web:   www.iss-dsp.com
>
> --------------000E2A3D41DC22DA2D3C5CDC
> Content-Type: text/html; charset=us-ascii
> Content-Transfer-Encoding: 7bit
>
> <!doctype html public "-//w3c//dtd html 4.0 transitional//en">
> <html>
> Hi,
> <br>Could someone please explain the whole process of <u>Scan Test</u>
> with reference to ASIC implementation.
> <br>Apparently during Scan Testing (if the implementation has memory)
the
> memory blocks are bypassed while the remaining circuitry is Scan
Tested.
> <p>Thanks in Advance.
> <br>Austin
> <p>--
> <br>------------------------------------------------------------
> <br>Integrated Silicon Systems
Ltd.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> Tel: +44 28 90 50 4000
> <br>50 Malone
Road&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> Fax: +44 28 90 50 4001
> <br>Belfast&nbsp; BT9
5BS&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> Web:&nbsp;&nbsp; www.iss-dsp.com
> <br>&nbsp;</html>
>
> --------------000E2A3D41DC22DA2D3C5CDC--
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24483
Subject: Further FPGA metastability questions
From: "John L. Smith" <jsmith@visicom.com>
Date: Thu, 10 Aug 2000 11:01:02 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------9280D8CF6CD8F00A8C0761D4
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  Xilinx has two (older, dated three years ago) app notes posted on
metastability. They are XAPPP077 and XAPP094. The first note,
(XAPP077, uncredited) presents some numbers for the 9500 family.
(If you read it and try to follow, it has an error, contains a
minus sign in the exponent for the MTBF equation, leading to
the wrong result of smaller MTBF for larger metastability
resolution time). The second one, by Alfke and Philofsky, presents
some numbers for some 3000, 4000, and 4000E parts (and does not
have the exponent error).

 Depending on the design of the flip-flop, a metastable event may
take different forms:
1) Delayed output transition
2) Runt pulse (starts to transit, but returns to original state)
3) Oscilation

 Finally, my questions...
 XAPP094 illustrates only the first type of metastable event,
although the test circuit they used would produce results
for each of the three modes I listed.

A) Are the FF's inside Xilinx parts designed so that delayed
 transition is the only metastable mode possible?

Most discussions I've seen on Deja seem to be of a qualitative
nature...

B) Does anyone have any characterization for newer parts they
 can share?

Crossing clock domains is unavoidable, we all want to make it
reliable.
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title:Principal Engineer
x-mozilla-cpt:;30864
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--------------9280D8CF6CD8F00A8C0761D4--

Article: 24484
Subject: Help with Xilinx
From: ramy <ramy@cim.mcgill.ca>
Date: Thu, 10 Aug 2000 11:34:39 -0700
Links: << >>  << T >>  << A >>
Hello,

I have been working with the Foundation Series to program my XC4010E-4 PG191, and I have been having many problems. Any ideas or suggestions would be greatly appreciated. 

What I need:
I need to create a triangular wave voltage signal. I implemented an 8-bit counter that counts from 0 to 255 to 0 and back to 255, etc. The output goes through a D/A converter and to an amplifier to generate at 30V peak to peak triangular wave.

Problem:
Occasionally, the bit file will program correctly, and the triangle wave will be as desired. However, when I implement other parts of the Xilinx control circuit, the new bit file does not program the chip correctly: the resulting triangle wave is not smooth, but rather a very odd shape that is more like a staircase. 

The  previous version of this project has used the XC4010 version of the chip and works correctly. However, I am currently using Foundation Series which only implements the XC4010E library. However, the results are identical when programming the XC4010 and XC4010E chips.
(note, the XC4010E chip is backwards compatible with XC4010, but differs by architectural enhancements.)

If you have any idea what might be causing this problem, ideas or solutions (anything!!) or would like me to provide more information, please e-mail me ramy@cim.mcgill.ca.

thanks,
Ramy
Article: 24485
Subject: Deterministic FPGA routing?
From: Don Frevele <dfrevele@hotmail.com>
Date: Thu, 10 Aug 2000 19:44:36 GMT
Links: << >>  << T >>  << A >>
Can the Xilinx router (PAR) be made to run deterministically (i.e.
produce the same exact output for different runs given the same input)?

I'm asking because my bosses want to make the release procedure of
hardware design similar to that used for software designs. For software
they copy the source files to a temp directory, run the build procedure
and then compare the outputs (object file) between this build and what
they are releasing.
The equivalent for hardware would be start with the VHDL code and
compare the bitsteam files. I don't that the VHDL tools would be any
problem, but I know the Xilinx PAR is not deterministic.

Long,long ago APR used a random seed, which you could feed back for
subsequent runs, but I don't see that anymore.

How about using a guide file? Would feeding the released ncd as a guide
file force PAR to produce the same route given the same input?

Any thoughts would be appreciated.
Thanks in advance for your help.


Donald Frevele
Senior Engineer, Technical Services
BAE SYSTEMS
Advanced Systems
Phone: 	631-262-8135
e-Fax: 	631-262-8011
E-mail: 	don.frevele@baesystems.com



Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24486
Subject: Re: 3-state busses on Virtex?
From: Hernan Saab <hernan@synplicity.com>
Date: Thu, 10 Aug 2000 12:45:39 -0700
Links: << >>  << T >>  << A >>

I can read this implementation is pretty much implemented as a priority
encoder (this fact confirms my guess that I sent to Peter Alfke a few
months back).

I find it hard to believe a company would even dare to Patent this feature.
Is there a very complicated detail I maybe missing about this patent?




Philip Freidin wrote:

> On Wed, 09 Aug 2000 16:09:54 +0200, Steven Sanders <sanders@imec.be> wrote:
>
> >Hello,
> >
> >I was wondering how 3-state busses are REALLY implemented in Virtex
> >devices. Is a real 3-state bus possible or is everything divided in
> >separate lines from block to block which accesses the bus?
> >Thanx in advance!
> >Steven.
>
> The best way to answer questions like this is to get the IBM patent
> server to help you. Try this:
>
>     http://204.146.135.160/cgi-bin/viewpat.cmd/US05677638__
>
> and
>
>    http://204.146.135.160/cgi-bin/viewpat.cmd/US05847580__
>
> and
>
>    http://204.146.135.160/cgi-bin/viewpat.cmd/US05939930__
>
> Philip Freidin
>
> Mindspring that acquired Earthlink that acquired Netcom has
> decided to kill off all Shell accounts, including mine.
>
> My new primary email address is    philip@fliptronics.com
>
> I'm sure the inconvenience to you will be less than it is for me.

--



Hernan Javier Saab
Western Area Applications Engineer
Email: HERNAN@synplicity.com
Direct Phone: 408-215-6139
Main Phone: 408-215-6000
Pager: 888-712-5803
FAX: 408-990-0295
Synplicity, Inc.
935 Stewart Drive
Sunnyvale, CA  94086  USA
Internet <http://www.synplicity.com >


Article: 24487
Subject: Re: Deterministic FPGA routing?
From: Greg Neff <gregneff@my-deja.com>
Date: Thu, 10 Aug 2000 20:18:20 GMT
Links: << >>  << T >>  << A >>
In article <8mv0n3$4e3$1@nnrp1.deja.com>,
  Don Frevele <dfrevele@hotmail.com> wrote:
> Can the Xilinx router (PAR) be made to run deterministically (i.e.
> produce the same exact output for different runs given the same
input)?
>
> I'm asking because my bosses want to make the release procedure of
> hardware design similar to that used for software designs. For
software
> they copy the source files to a temp directory, run the build
procedure
> and then compare the outputs (object file) between this build and what
> they are releasing.
> The equivalent for hardware would be start with the VHDL code and
> compare the bitsteam files. I don't that the VHDL tools would be any
> problem, but I know the Xilinx PAR is not deterministic.
>
> Long,long ago APR used a random seed, which you could feed back for
> subsequent runs, but I don't see that anymore.
>
> How about using a guide file? Would feeding the released ncd as a
guide
> file force PAR to produce the same route given the same input?
>
> Any thoughts would be appreciated.
> Thanks in advance for your help.
>
> Donald Frevele
> Senior Engineer, Technical Services
> BAE SYSTEMS
> Advanced Systems
> Phone: 	631-262-8135
> e-Fax: 	631-262-8011
> E-mail: 	don.frevele@baesystems.com
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>

The newer Alliance/Foundation (i.e. NeoCAD) tools do not use a random
seed like the old XACT tools.  Instead, there is a cost table, similar
to PCB autorouting tools.  If you don't use multi-pass place and route
then you will use the default cost table entry, and you should get the
same result every time.  If you use multi-pass place and route, then
you can select the starting table entry.  You should not need to use a
guide file, and the result should be deterministic.  Check with Xilinx
to be sure.

Of course, this assumes that you are using the same version and service
pack(s). Also, make sure that you are using the same speed and package
files for the target device, since these will affect the P&R algorithm.

Your build configuration should include:

1) Schematics and/or HDL source

2) Schematic part and/or HDL libraries

3) All files generated by schematic/HDL/Xilinx tools

4) Xilinx software CDs

5) Xilinx executeable service packs

6) Xilinx device speed and package files

7) Xilinx Command History (from Design Manager utilities menu, select
command line option)

--
Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24488
Subject: Re: tbuf
From: "Domagoj" <domagoj@engineer.com>
Date: Thu, 10 Aug 2000 23:05:09 +0200
Links: << >>  << T >>  << A >>
> What about the Automatic replacement of internal Tristates available in
> Synthesis tools.?

    Had no idea about that possiblity.. :)
Which tools can do that ?

regards.

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------



Article: 24489
Subject: Re: Help with Xilinx
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 10 Aug 2000 14:29:01 -0700
Links: << >>  << T >>  << A >>
If you really get a staircase, but with the correct overall period, then I assume that the least-significant bits are not brought out to your D/A. I would probe the eight(?) digital outputs and look at their activity.
If the frequency is correct, then the counter works properly. And vice versa: if the frequency is wrong, then the counter is wrong.

I would also vary the frequency, the chip temperature and Vcc up and down, to get a feel for the source of the problem.

Important:
Since this design configures correctly at least sometimes, I would be suspicious about the configuration process, the bitstream, CCLK reflections, the proper beginning of the bitstream, etc.
Monitoring  Dout is the popular way of testing this.

Peter Alfke, Xilinx Applications.

ramy wrote:

> Hello,
>
> I have been working with the Foundation Series to program my XC4010E-4 PG191, and I have been having many problems. Any ideas or suggestions would be greatly appreciated.
>
> What I need:
> I need to create a triangular wave voltage signal. I implemented an 8-bit counter that counts from 0 to 255 to 0 and back to 255, etc. The output goes through a D/A converter and to an amplifier to generate at 30V peak to peak triangular wave.
>
> Problem:
> Occasionally, the bit file will program correctly, and the triangle wave will be as desired. However, when I implement other parts of the Xilinx control circuit, the new bit file does not program the chip correctly: the resulting triangle wave is not smooth, but rather a very odd shape that is more like a staircase.
>
> The  previous version of this project has used the XC4010 version of the chip and works correctly. However, I am currently using Foundation Series which only implements the XC4010E library. However, the results are identical when programming the XC4010 and XC4010E chips.
> (note, the XC4010E chip is backwards compatible with XC4010, but differs by architectural enhancements.)
>
> If you have any idea what might be causing this problem, ideas or solutions (anything!!) or would like me to provide more information, please e-mail me ramy@cim.mcgill.ca.
>
> thanks,
> Ramy

Article: 24490
Subject: Re: Further FPGA metastability questions
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 10 Aug 2000 17:37:28 -0400
Links: << >>  << T >>  << A >>
"John L. Smith" wrote:
> 
>   Xilinx has two (older, dated three years ago) app notes posted on
> metastability. They are XAPPP077 and XAPP094. The first note,
> (XAPP077, uncredited) presents some numbers for the 9500 family.
> (If you read it and try to follow, it has an error, contains a
> minus sign in the exponent for the MTBF equation, leading to
> the wrong result of smaller MTBF for larger metastability
> resolution time). The second one, by Alfke and Philofsky, presents
> some numbers for some 3000, 4000, and 4000E parts (and does not
> have the exponent error).
> 
>  Depending on the design of the flip-flop, a metastable event may
> take different forms:
> 1) Delayed output transition
> 2) Runt pulse (starts to transit, but returns to original state)
> 3) Oscilation
> 
>  Finally, my questions...
>  XAPP094 illustrates only the first type of metastable event,
> although the test circuit they used would produce results
> for each of the three modes I listed.
> 
> A) Are the FF's inside Xilinx parts designed so that delayed
>  transition is the only metastable mode possible?
> 
> Most discussions I've seen on Deja seem to be of a qualitative
> nature...
> 
> B) Does anyone have any characterization for newer parts they
>  can share?
> 
> Crossing clock domains is unavoidable, we all want to make it
> reliable.

I expect that Peter Alfke of Xilinx will reply to your request for more
info as he seems to be a metastable expert <grin>.  But until he gets
around to it I can tell you that he has said in the past that the newer
parts are very metastability resistant. It appears that this is a
function of the gain bandwidth of the buffers used in the FFs. With each
new generation of FPGAs Xilinx improves on this figure so that the parts
are more and more resistant to metastability. 

On the other hand, IIRC, metastability is a strong function of the
resolution time (as you noted above). So as the clock speeds get faster
we lose some ground as well. But Peter has indicated in the past that
metastability is *almost* no longer a problem. I think he got a lot of
flack for that, but I know what he meant. No one would say that
metastability is *NOT* a problem regardless of how fast your parts are.
It all depends on how you use them. 



-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24491
Subject: Re: Further FPGA metastability questions
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 11 Aug 2000 03:16:22 GMT
Links: << >>  << T >>  << A >>


"John L. Smith" wrote:

>   Xilinx has two (older, dated three years ago) app notes posted on
> metastability. <snip>
>
>  Depending on the design of the flip-flop, a metastable event may
> take different forms:
> 1) Delayed output transition
> 2) Runt pulse (starts to transit, but returns to original state)
> 3) Oscilation
>
>  Finally, my questions...
>  XAPP094 illustrates only the first type of metastable event,
> although the test circuit they used would produce results
> for each of the three modes I listed.
>
> A) Are the FF's inside Xilinx parts designed so that delayed
>  transition is the only metastable mode possible?

They are just designed for high speed, no special deep insight into
metastability. My rule is: give the master latch the highest possible
gain-bandwidth in its feedback loop. The loop has so few amplifying
elements that, in my simplistic analysis, it just cannot oscillate.

>
>
> Most discussions I've seen on Deja seem to be of a qualitative
> nature...

Well, I published quantitative results, lots of numbers...

>
>
> B) Does anyone have any characterization for newer parts they
>  can share?

Unfortunately not.
Two reasons:
The flip-flops are now so good, have such a short recovery time, that it
is difficult to measure. If you read the app note you see that our
method ( documented in 1988, and copied by most other IC manufacturers)
is to transfer the contents of the flip-flop under test twice.
The early and the late transfer are then compared, and when they differ,
it is counted as a metastable delay that is longer than the first delay
( and shorter than the second). In order to reduce the required clock
frequency, I used the rising and falling edge for the two delays. Since
the measurements establish timing differences, the absolute delay does
not matter.
We then read the clock frequency that gives roughly one metastable event
per second, then increase the frequency until we see roughly 65000
metastable events per second. The rest is math.

Recently, we tried it with Virtex parts, and did not immediately get any
meaningful results, so we abandoned the tests for the time being. We
were not able to bring the measuring clock edge close enough to the
first clock. The flip-flops are just too fast in resolving
metastability. Which is good! But it makes it so damn difficult to prove
how good they are. Something akin to other reliability-related
quantitative measurements. Awfully hard to quantify the "badness" when
the devices are so good.

The second reason is that this effort has a hard time getting top
priority. And it is hard to argue that metastability measurements should
take precedence over many other activities, like preparing for the
introduction of a new device family.


> Crossing clock domains is unavoidable, we all want to make it
> reliable.

I agree.

Peter Alfke


Article: 24492
Subject: Re: 3-state busses on Virtex?
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 11 Aug 2000 03:23:24 GMT
Links: << >>  << T >>  << A >>


Hernan Saab wrote:

> I find it hard to believe a company would even dare to Patent this feature.

C'mon Hernan, patents have nothing to do with "daring".
If you have a smart idea, and you think it is novel, and you get it past the
patent examiner, you get a patent.
Doesn't mean that it always is the greatest invention ever. But it might be...

The objective here was to avoid the inherent delay of a conventional 3-state bus
driver, but achieve the same functionality.

Peter Alfke

Article: 24493
Subject: Re: Further FPGA metastability questions
From: Peter Alfke <palfke@earthlink.net>
Date: Fri, 11 Aug 2000 03:35:43 GMT
Links: << >>  << T >>  << A >>


rickman wrote:

>  It appears that this is a
> function of the gain bandwidth of the buffers used in the FFs. With each
> new generation of FPGAs Xilinx improves on this figure so that the parts
> are more and more resistant to metastability.
>
> On the other hand, IIRC, metastability is a strong function of the
> resolution time (as you noted above). So as the clock speeds get faster
> we lose some ground as well. But Peter has indicated in the past that
> metastability is *almost* no longer a problem. I think he got a lot of
> flack for that, but I know what he meant. No one would say that
> metastability is *NOT* a problem regardless of how fast your parts are.
> It all depends on how you use them.
>

Thanks, Rick. That's what I meant.
If you want to synchronize a 100 MHz signal with a 155 MHz clock, you may
still run into metastability problems.
But raw flip-flop speed has increased more than system speed. In other
words, interconnect delays are becoming more dominant, even in the ASIC
world. That's good for metastability resolution.
Slow flip-flops with very fast interconnects ( the old TTL MSI world) were
really struggling with metastability issues. When system speed is
determined predominantly by interconnects, then the flip-flop speed is so
excessive, that metastable events are easily resolved.

Peter Alfke


Article: 24494
Subject: Re: Further FPGA metastability questions
From: Phil Hays <spampostmaster@sprynet.com>
Date: Thu, 10 Aug 2000 21:28:47 -0700
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> > B) Does anyone have any characterization for newer parts they
> >  can share?
> 
> Unfortunately not.
> Two reasons:
> The flip-flops are now so good, have such a short recovery time, that it
> is difficult to measure.

Measuring metastability accurately would be nice.  But simply giving a limit:
"We didn't find any metastability events and we looked this hard" would be more
than good enough for most practical purposes.  After all, few of your customers
are going to need to push the metastability hardness to the limit.


> The second reason is that this effort has a hard time getting top
> priority.

I, as a customer of Xilinx, care about getting information on metastability. 
Crossing clock domains is something that can't be avoided.  Should I have told
the salesman when we ordered a small pile of XCV3200E's today that metastability
information is important?  Would that help?


-- 
Phil Hays
Article: 24495
Subject: PCI core needed for Xilinx
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Fri, 11 Aug 2000 04:37:09 GMT
Links: << >>  << T >>  << A >>
Hello,

I am designing a PCI target card.

I am trying to choose between a PCI interface glue chip and  a Xilinx FPGA.

I realize Xilinx sells a PCI core but it is way too pricey for a self
employed person such as myself.

Does anyone know of somesone selling a PCI interface design ?

Sincerely
Daniel DeConinck



Article: 24496
Subject: Getting into FPGAs
From: josh_eckstein@my-deja.com
Date: Fri, 11 Aug 2000 04:37:59 GMT
Links: << >>  << T >>  << A >>
Hi. Please forgive me, I am a newbie. No, wait!
Don't stop reading yet! Please come back.. Thank you.

As someone who has always enjoyed hardware design and
even moreso, writing code, it came as a complete surprise
to me that I had never heard of FPGAs until a few days ago
when I came across an article that mentioned them in the
context of device prototyping.

In short, I am interested. To that extent, I have had
a hard time finding out information about obtaining
FPGAs or any of the hardware one might use to program an FPGA,
preferably in an inexpensive manner. :) Software info seems
to be in greater abundance, though much of the software is
not under several hundred dollars. Where would I purchase
FPGAs and appropriate accessories? Where might I download
VHDL/Verilog/etc. compilers? (Alliance is free, correct?)

I know I sound stupid right now, but I don't have a
clue what I'm talking about, would like to, but can't
find anything. As my subject suggests: have pity.
You guys have a newsgroup FAQ? Can anyone push me to
an informative site so I can stop bugging you?

Thank you for whatever help you can offer!

- Joshua Eckstein
  josh_eckstein@yahoo.com


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24497
Subject: [Ad] Overstocked on Xilinx Spartan FPGA Proto Kits
From: "Tony Burch" <tony@BurchED.com.au>
Date: Fri, 11 Aug 2000 14:47:03 +1000
Links: << >>  << T >>  << A >>
Oops, Burch Electronic Designs is currently
overstocked with BED-XILINX-BASE+
FPGA Prototyping Kits.

If you order a BED-XILINX-BASE+ Kit in
August, we will throw in an extra free Download
Pod Printed Circuit Board with your order!

BED-XILINX-BASE+ Kits are US$66.00

www.BurchED.com.au

Best regards
Tony Burch
---------------
Low Cost, Easy FPGA Prototyping Kits -
Real FPGA Tools for Real World Prototypes

- Spartan XCS05 FPGA on a board
- Easy connection - FPGA pin numbers
   labelled on BOTH sides of the board
- Prototyping area - add what you want
- Canned crystal oscillator module plus
   other components included
- Configuration download pod board included
- PC parallel port interface capability
- Low cost
- Easy!



Article: 24498
Subject: what does 0.35 micron mean
From: "me" <me@rad.com>
Date: Fri, 11 Aug 2000 07:48:57 +0100
Links: << >>  << T >>  << A >>

What is 0.35 micron a measurement of ?, when FPGAs / ASICs are spec'd as
using 0.35 micron technology .



Thanks

    Jon


Article: 24499
Subject: Re: what does 0.35 micron mean
From: "disk" <personne@microsoft.com>
Date: Fri, 11 Aug 2000 08:57:16 +0200
Links: << >>  << T >>  << A >>
This is the length of the smallest transistor...




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