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Messages from 13575

Article: 13575
Subject: Re: A short digression...
From: rk <stellare@NOSPAMerols.com>
Date: Thu, 10 Dec 1998 06:55:54 -0500
Links: << >>  << T >>  << A >>
hi,

i guess viewsim (and other logic simulators) have recently been, well, trashed
a bit.  but being a board deisgner (and designing the fpgas on the boards) it's
nice to have a single simulator/environment.  perhaps i do need to get updated
a bit, do the vhdl simulator vendors supply vhdl models for the discrete
ttl-type parts that are normally on a board in their package?  available as an
option?  have to buy from third party [and have another integration problem?]?

viewsim does seem to work pretty well - and when the board is done, just push a
button and netlists come out that feed right itno the pcb designer's computer,
no muss, no fuss [unless of course the license got screwed in the update or if
the 'new' version needs the 'new' patch].  anyways, when it's all set up right,
it works perfectly.  i gave up checking the netlister's output years ago.

rk

----------------------------------------------------------------------------------

Austin Franklin wrote:

> >... By the time I needed to do a new
> > design, the tools had changed a lot. As a result, I never became more
> > than just "familiar" with the tools.
>
> I understand ;-)
>
> My choice of Viewlogic for schematics is based on my need to do board level
> designs too, and Viewlogic is a good schematic tool for that, interfaces
> with PADS very well...and I can do board level simulation very easily.
> Overall, it is a pretty complete and robust tool.  I did like the DOS
> version though....I don't believe there was a better x86 based tool
> available....and I don't know if there is today.  Yes, on Unix
> workstations, there were other better/comparable tools available...
> Viewlogic has come a long way...
>
> It's user interface could really be improved (like using the page-up/down
> keys, instead of F8 and F7, etc)...but all in all, it work pretty well.
>
> If you only do chips, and never do board level stuff, then, I am sure, your
> options are different...
>
> Austin



Article: 13576
Subject: Re: Verilog/FPGA Express Synth Problem
From: Alain <alain_raynaud@mentorg.com>
Date: Thu, 10 Dec 1998 14:51:06 +0100
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:
> 
> Rick, the example is classic textbook Verilog for synthesis of an
> async resettable register.  Synthesis tools recognise it and
> infer the appropriate flipflop(s).  The always block (=process)
> executes every time one of the "or"-ed signals in its sensitivity
> list changes.  The qualifier "posedge" restricts the sensitivity
> to only rising transitions of the qualified signal. "or" is a magic
> operator for sensitivity lists and is not the same as logical OR.

However, there is one slight discrepancy in Verilog for asynchronous SET
and RESET.

You code an always block with @(posedge reset or posedge set)

Which means that when RESET for instance becomes active (ie, switches to
1), a posedge is indeed detected and the flip-flop output is
asynchronously reset. This is correct.

But when both SET and RESET are active, say SET has priority over RESET
(so the output is 1), and then the SET signal becomes inactive.... your
output stays stuck at one, even though the only asynchronous signal is
the RESET.

That's a limitation of the Verilog RTL subset in my opinion. Not to
start a war here (please!) but the VHDL RTL style for flip-flops is much
more clean regarding that aspect. The Verilog RTL style is (IMHO) a
hack: you have to obey a specific order of nested IF conditions. Why? I
still didn't figure it out.

Do you find it normal to have a mismatch between pre and post-synthesis
simulation? I don't.

Alain.
-- 
-----------------------------------------------------------------------
 Alain RAYNAUD                                            META SYSTEMS 
 R&D Logic Design Team                                          LP 853
                                   3 Avenue du Canada - Batiment Sigma
 Tel: (33) 01 64 86 61 69             91975 Courtaboeuf Cedex - FRANCE
 E-Mail: Alain_Raynaud@mentor.com             Fax: (33) 01 64 86 61 61
-----------------------------------------------------------------------

Article: 13577
Subject: Re: A short digression...
From: z80@ds2.com (Peter)
Date: Thu, 10 Dec 1998 14:19:24 GMT
Links: << >>  << T >>  << A >>

BTW, how does current VL Office compare with the old VL4? I mean
productivity-wise. Does it support the old VL 4 simulation scripts?
(.cmd files)

I still use VL 4 for the occassional X3K or X4K FPGA job. Of course it
doesn't run in any windoze DOS box, and the only way to get 1024x768
is with an 8514-emulating video card, but it is a rock solid program
with few if any relevant bugs. I can knock together a design, with
lots of functional simulation (which really does work) in no time.

I am also reliably informed that VL4 can use the later unified
libraries, although personally I never tried it. This extends device
support to most of the later XC4k family, with my P & R tools
(XACT6.01) supporting only a little more device-wise. 

I paid some $10k for this Xilinx-only kit some years ago. And there is
a dongle crack for it too, which removes another big hassle.

I still use Orcad SDT/386 for PCB-level design - far quicker to use
than Orcad Capture.

I know that when VL Office first came out, it was bug-ridden.

>I did like the DOS
>version though....I don't believe there was a better x86 based tool
>available....and I don't know if there is today.  Yes, on Unix
>workstations, there were other better/comparable tools available... 
>Viewlogic has come a long way...


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13578
Subject: Re: A short digression...
From: Todd Kline <todd@wgate.com>
Date: Thu, 10 Dec 1998 09:28:37 -0500
Links: << >>  << T >>  << A >>
If you "need" to add VHDL for FPGA/PLD support, add Viewlogic's SpeedWave to your
design tools and keep ViewSim!  SpeedWave is the Vantage VHDL simulator.  It
integrates seamlessly with ViewDraw & ViewSim.  If you need Verilog, you can also add
VCS.

I use FPGA's for ASIC prototyping, so my methodology is full VHDL inside the chips,
however, I would never want to be forced into doing my board level sims exclusively in
VHDL.  If your simulating discreet logic, stick to gate level simulators.

Todd

rk wrote:

> hi,
>
> i guess viewsim (and other logic simulators) have recently been, well, trashed
> a bit.  but being a board deisgner (and designing the fpgas on the boards) it's
> nice to have a single simulator/environment.  perhaps i do need to get updated
> a bit, do the vhdl simulator vendors supply vhdl models for the discrete
> ttl-type parts that are normally on a board in their package?  available as an
> option?  have to buy from third party [and have another integration problem?]?

Article: 13579
Subject: Re: Verilog/FPGA Express Synth Problem
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Thu, 10 Dec 1998 09:39:36 -0500
Links: << >>  << T >>  << A >>
Thanks everyone for comments/suggestions. I did figure out the problem, and yes,
FPGA Express did generate wrong logic. Even though what I wrote is legal Verilog
(is even in textbook I have), FPGA Express would not recognize proper reset unless
everything in the else... clause was bracketed by a begin....end.

Code fragment (with fixes)....

    always @ ( posedge(reset) or posedge(mclk) )
        begin
            if (reset == 1)
                lfsr_reg <= 6'b 000001; // guarantee register doesn't
                                        //load all 0's on reset
            else              begin // THIS ADDED                if (load == 1) //
loading takes precedence over shift
                    lfsr_reg <= load_data; // enable
                else if (enable == 1)
                    lfsr_reg <= { (lfsr_reg[5] ^ lfsr_reg[0]) ,
                                lfsr_reg[5:1] }; // shift right
              end // THIS ADDED
         end


Article: 13580
Subject: Re: Verilog/FPGA Express Synth Problem
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Thu, 10 Dec 1998 14:40:54 +0000
Links: << >>  << T >>  << A >>
Alain wrote:
<snip quoted intro-to-always-for-VHDL-codist>
> However, there is one slight discrepancy in Verilog for asynchronous SET
> and RESET.

> You code an always block with @(posedge reset or posedge set)
> Which means that when RESET for instance becomes active (ie, switches to
> 1), a posedge is indeed detected and the flip-flop output is
> asynchronously reset. This is correct.
> But when both SET and RESET are active, say SET has priority over RESET
> (so the output is 1), and then the SET signal becomes inactive.... your
> output stays stuck at one, even though the only asynchronous signal is
> the RESET.
> That's a limitation of the Verilog RTL subset in my opinion. Not to
> start a war here (please!) but the VHDL RTL style for flip-flops is much
> more clean regarding that aspect. The Verilog RTL style is (IMHO) a
> hack: you have to obey a specific order of nested IF conditions. Why? I
> still didn't figure it out.

I agree, although I have never hit this problem myself because I have
always used the "synchronous thought police" approach which says that
async (re)set is strictly for use at system initialisation, so my 
designs have never used both in the same always block.

OTOH I would have hoped that the synthesis tool will notice that it 
cannot synthesise hardware that will give the same results as 
simulation; so it should grumble.  Synplify, to its shame, doesn't.

The hack, I suggest, comes from placing the "posedge" test within
the sensitivity list.  If you could use "posedge" as a genuine 
operator, like VHDL's rising_edge() or 'EVENT, it would be OK:

always @(set or reset or clk)
 if (set)
   ...
 else if (reset)
   ...
 else if (posedge clk)
   ...

Much cleaner, and it would allow for such things as fancy flipflops
that can clock on either edge. This special-case behaviour of 
posedge/negedge and the 'or' operator is one of many things about 
Verilog that strike me as being only 0.8-baked. (Maybe some Verilog 
guru will now pop up and tell me that the above example is correct 
Verilog, in which case I apologise in advance!)
 
> Do you find it normal to have a mismatch between pre and post-synthesis
> simulation? I don't.

Not only do I not find it normal, I find it offensive.  In practice,
of course, I cover myself by using only a "safe" synthesisable subset,
same as everyone else.  Thanks for alerting me to yet another
restriction on that subset.

Jonathan Bromley

Article: 13581
Subject: Magazine IEEE for FPGA ???
From: renzo.arce@st.com
Date: 10 Dec 98 14:40:57 GMT
Links: << >>  << T >>  << A >>
Hi,
some body know which IEEE magazine contains articles about FPGA
design and development.

Thank you !

Renzo Arce

Article: 13582
Subject: Re: A short digression...
From: "Austin Franklin" <dar0kroom@ix.netcom.com>
Date: 10 Dec 1998 15:53:31 GMT
Links: << >>  << T >>  << A >>
> BTW, how does current VL Office compare with the old VL4? I mean
> productivity-wise.

Pretty good for me.

> Does it support the old VL 4 simulation scripts?
> (.cmd files)

Why, yes it does ;-)

 

Article: 13583
Subject: Re: A short digression...
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 10 Dec 1998 10:54:46 -0500
Links: << >>  << T >>  << A >>
wvo7.5 seems to be pretty bug free, and they put the command line back
in.  The user interface is a little different than the old vl4, but once
you get used to it it isn't bad.  Productivity-wise, it is a little
better.  How much depends on your design habits.  You will take a
productivity hit until you get used to the user interface though.  One
nice feature is that you can have multiple pages open at once so you don't
have to push-pop push-pop to go back and forth.  The VL4 sim scripts will
run just fine, I've got several that I've used under wvo7.5.  Mine is
running under NT4.  Since the rest of my environment is NT4, there is a
big productivity boost by not having to reboot to get in or out of wvo.
Back when I used VL4, I had to reboot frequently because I had a good part
of my stuff under windows 3.1.

Peter wrote:

> BTW, how does current VL Office compare with the old VL4? I mean
> productivity-wise. Does it support the old VL 4 simulation scripts?
> (.cmd files)
>
> I still use VL 4 for the occassional X3K or X4K FPGA job. Of course it
> doesn't run in any windoze DOS box, and the only way to get 1024x768
> is with an 8514-emulating video card, but it is a rock solid program
> with few if any relevant bugs. I can knock together a design, with
> lots of functional simulation (which really does work) in no time.
>
> I am also reliably informed that VL4 can use the later unified
> libraries, although personally I never tried it. This extends device
> support to most of the later XC4k family, with my P & R tools
> (XACT6.01) supporting only a little more device-wise.
>
> I paid some $10k for this Xilinx-only kit some years ago. And there is
> a dongle crack for it too, which removes another big hassle.
>
> I still use Orcad SDT/386 for PCB-level design - far quicker to use
> than Orcad Capture.
>
> I know that when VL Office first came out, it was bug-ridden.
>
> >I did like the DOS
> >version though....I don't believe there was a better x86 based tool
> >available....and I don't know if there is today.  Yes, on Unix
> >workstations, there were other better/comparable tools available...
> >Viewlogic has come a long way...
>
> --
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13584
Subject: Re: A short digression...
From: rich katz <rich.katz@gsfc.nasa.gov>
Date: Thu, 10 Dec 1998 11:29:25 -0500
Links: << >>  << T >>  << A >>
it's a lot more stable then the intial windoze versions, where crashes and
lockups were pretty common.  it still seems to have some annoying quirks along
with breaking of previously working features.  one new feature is the symbol
wizard which makes life a bit easier for this task, and you can enter pin #'s,
labels, bubbles (for inversions), etc., etc, and you can resize the symbol w/
spacers and it'll move the stuff for you.  it would be nice if you could use
that to re-edit an already made symbol, maybe there's a way we couldn't find,
or perhaps that's in the latest version.. anyways, better than the FUB
technique.

as far as simulation, i still cut segments out of old .cmd files, paste them
into new ones, it works fine, haven't seen any problems.  we often run the
simulator from a .cmd file called from another program (pascal, of course) and
have it redirect errors (from check commands) into files, don't have to use
the gooey, and our calling program will automagically verify that there are no
errors.

rk

Ray Andraka wrote:

> wvo7.5 seems to be pretty bug free, and they put the command line back
> in.  The user interface is a little different than the old vl4, but once
> you get used to it it isn't bad.  Productivity-wise, it is a little
> better.  How much depends on your design habits.  You will take a
> productivity hit until you get used to the user interface though.  One
> nice feature is that you can have multiple pages open at once so you don't
> have to push-pop push-pop to go back and forth.  The VL4 sim scripts will
> run just fine, I've got several that I've used under wvo7.5.  Mine is
> running under NT4.  Since the rest of my environment is NT4, there is a
> big productivity boost by not having to reboot to get in or out of wvo.
> Back when I used VL4, I had to reboot frequently because I had a good part
> of my stuff under windows 3.1.
>
> Peter wrote:
>
> > BTW, how does current VL Office compare with the old VL4? I mean
> > productivity-wise. Does it support the old VL 4 simulation scripts?
> > (.cmd files)
> >
> > I still use VL 4 for the occassional X3K or X4K FPGA job. Of course it
> > doesn't run in any windoze DOS box, and the only way to get 1024x768
> > is with an 8514-emulating video card, but it is a rock solid program
> > with few if any relevant bugs. I can knock together a design, with
> > lots of functional simulation (which really does work) in no time.
> >
> > I am also reliably informed that VL4 can use the later unified
> > libraries, although personally I never tried it. This extends device
> > support to most of the later XC4k family, with my P & R tools
> > (XACT6.01) supporting only a little more device-wise.
> >
> > I paid some $10k for this Xilinx-only kit some years ago. And there is
> > a dongle crack for it too, which removes another big hassle.
> >
> > I still use Orcad SDT/386 for PCB-level design - far quicker to use
> > than Orcad Capture.
> >
> > I know that when VL Office first came out, it was bug-ridden.
> >
> > >I did like the DOS
> > >version though....I don't believe there was a better x86 based tool
> > >available....and I don't know if there is today.  Yes, on Unix
> > >workstations, there were other better/comparable tools available...
> > >Viewlogic has come a long way...
> >
> > --
> > Peter.
> >
> > Return address is invalid to help stop junk mail.
> > E-mail replies to zX80@digiYserve.com but
> > remove the X and the Y.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka



Article: 13585
Subject: Re: A short digression...
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Thu, 10 Dec 1998 10:06:00 -0700
Links: << >>  << T >>  << A >>
rk wrote in message <366FB6C9.38153E21@NOSPAMerols.com>...
>hi,
>
>i guess viewsim (and other logic simulators) have recently been, well,
trashed
>a bit.  but being a board deisgner (and designing the fpgas on the boards)
it's
>nice to have a single simulator/environment.  perhaps i do need to get
updated
>a bit, do the vhdl simulator vendors supply vhdl models for the discrete
>ttl-type parts that are normally on a board in their package?  available as
an
>option?  have to buy from third party [and have another integration
problem?]?


ModelSim does not come with TTL libraries.  I searched the 'net and found a
number of sites (see the FAQ of comp.lang.vhdl) that had VITAL models of
various things - and it was a mess!  I ended up thumbing through the
Ashenden book and found some code that did setup/hold time checks, so I
started building models.  It's all yr basic jellybean parts ('373, '374,
'245, '244, '823, etc. etc.), with setup/hold checks, minimum clock width
checks and prop delays. Delays are modelled as from clock to output,
output-enable to output, and just input to output.  It's basically the same
code for the all of the parts.

To make my life easier, I used generics for the number of gates in the chip,
so I could use one '373 (an octal part) for a sixteen-bit (or any arbitrary
width) bus if I wanted to.  The timing parameters are all generics, too; the
defaults are for FCT parts but it's simple enough to change the defaults
when instantiating the parts.

Nope, I don't model PCB trace delays or wire lengths or any of that.  Nor do
I model loading effects, tho' I'd really like to.  I'm sure VITAL does all
of that, but have you looked at those models?

I also have bus-signal models of the processors we use (would you believe -
transputers?).  The processor model reads a text-file "program" which simply
contains the value of the address and data busses and any control signals
for one instruction cycle, and the model generates the proper timing for all
of the relevant signals.  I'm working on one for a Motorola Coldfire
processor now.  I don't particularly care about modelling the ALU - I just
need the bus timing.

I even have models of A/D and D/A converters.  I defined a (bounded)
float-based type called volt and built the models.  Took about an hour each
to write the model and verify it.  A model of the digital timing is what I'm
after.  For a DAC, data gets latched or loaded into the part, and some
conversion time later the voltage output changes.  There's no attempt to
make that voltage change anything other than a step function - that's not
what I'm trying to model.

Obviously, if you don't have the time to develop your own models, you'll
have to buy/beg/borrow/steal 'em from wherever, and I realize that many
people simply don't have the time.  I think it's time well spent, tho'.

-- Andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 13586
Subject: Synthesis with Actel
From: renzo.arce@st.com
Date: 10 Dec 98 17:15:22 GMT
Links: << >>  << T >>  << A >>
Hi,
somebody know what mean the communication error during the 
synthesis with ActMap of Actel Designer Series.

ERROR:(VHDL-1769) Cannot split signal 'n15'

I am using the family Actel 3200DX for synthesis an 64-bits
multiplier.

Thank you

Renzo Arce
renzo.arce@st.com

Article: 13587
Subject: Re: HELP, Tool selection
From: z80@ds2.com (Peter)
Date: Thu, 10 Dec 1998 20:08:23 GMT
Links: << >>  << T >>  << A >>

>Also, I note that the most vehement and ill-informed complainers are the
>anonymous ones such as yourself (and e.g. the initiator of the "Will
>Xilinx survive" thread"), who are willing to put their Usenet
>reputation, but *not* their personal or professional reputation on the
>line.

You must be confusing *me* with someone else.

Note also, that for non-UK readers (which is about 95% of the net)
your signature (Direct Insight Ltd) might as well be anonymous too.
Only a small selection of UK engineers will recognise it as a vendor
of high-end EDA software.

I am not sure what you want. Everyone in usenet to register a PGP
public key with some 3rd party, and PGP-sign all their posts? Nothing
short of that will mean anything - IF you are to allow people to post
their *private* opinions at all.

>My company has declined to respond to your own past untrue criticisms
>for these reasons, 

Please produce examples if you can where something **I** said was "ill
informed" or was an "untrue criticism".

>and I know many other vendors and VARs take the same
>view of Usenet. Which is a shame.

It is a shame, but let me paraphrase what I think you are saying: only
a few vendors maintain a usenet presence, usually because they are
frightened to death of many negative responses to something they say. 

This is true; a lot of usenet posts are negative in their nature,
because people tend to complain more loudly than they praise. 

But a company which makes good products, supports them well, attends
promptly to bugs, etc, has little to fear and a huge amount to gain
from usenet presence IF that presence is done by people who are
genuinely helpful. Usually, however, firms use virtual morons for this
purpose (probably the same people they employ in Tech Support) - see
e.g. the Symantec "support" forums where the staff do little more than
post standard replies without as much as reading the questions. You
can tear your hair out trying to get a response there. But that is the
norm.

Peter Afke of Xilinx does a great job here, OTOH, but he is an
exception, not only because he posts here at all, but because he has
good technical knowledge.

I can well understand vendors staying away when they read the stick
which certain firms, e.g. Protel, Orcad, get in usenet. But those
firms frankly ASK for it, releasing buggy-as-hell products and then
charging $1k+ for an "upgrade" which sometimes contains many of the
same old bugs. For those who don't look after their customers, and
prefer to hide behind their distributors, any public forum like usenet
will always be a very rough place.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13588
Subject: Re: Array Range Legal?
From: Makarand Joshi <mjoshi@quickturn.com>
Date: Thu, 10 Dec 1998 16:34:09 -0500
Links: << >>  << T >>  << A >>
Yes Rich,
You are correct.
It is perfectly legal to do this in VHDL as well as in Verilog;
I dont see a reason why one would want to do so.

-Makarand.

Suttinan Chattong wrote:

> Hi there,
>
> I believe it is OK to do so.  I've used it once in simulation & synthesis,
> and
> it did not give any problems.
>
> Suttinan....
>
> rich katz <rich.katz@gsfc.nasa.gov> wrote in article
> <36687FA3.A8A81595@gsfc.nasa.gov>...
> > hi,
> >
> > is the following code legal vhdl, with the starting and ending index the
> > same?
> >
> >         ZData : Out Std_Logic_Vector(0 downto 0)
> >
> > it's the output of vhdl-generating software and normally is a
> > multiple-bit bus - however, the architecture permits single bit
> > outputs.  is this ok or does it need to be recoded to be a Std_Logic
> > signal.
> >
> > thanks a bunch
> >
> > rk
> >
> >



Article: 13589
Subject: Re: HELP, Tool selection
From: rich katz <rich.katz@gsfc.nasa.gov>
Date: Thu, 10 Dec 1998 16:46:19 -0500
Links: << >>  << T >>  << A >>
Peter wrote:

> Peter Afke of Xilinx does a great job here, OTOH, but he is an
> exception, not only because he posts here at all, but because he has
> good technical knowledge.

let's not forget stu, who along with good technical posts, is also
entertaining to read.

rk

Article: 13590
Subject: Re: HELP, Tool selection
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Thu, 10 Dec 1998 21:54:50 GMT
Links: << >>  << T >>  << A >>
On Tue, 8 Dec 1998 10:00:03 +0000, David Pashley <David@edasource.com>
wrote:

>In the "olden days" of digital design, we used to talk about
>hierarchichal and top-down design (now called "re-use"). At the bottom
>level of these designs would be gate-level schematics, very efficiently
>designed with the target architecture in mind. Because we would put the
>bottom-level modules in a library and re-use them either directly, or
>modified, the trick was to make them as fast and small as possible. 

The trick was also that we didn't have a 100K gate FPGA to fill and
get out in the same time as the 25K gate one we did the year before.
Hence why I advocate that designers do as much in HDL as possible to
keep independent, and then only do the things they really have to do
by hand (schematics, or structural HDL).

>Hand drawn schematics are often many times more efficient than what a
>synthesis tool can produce. Of course you can't start out on a 200,000k

<CHEAP_SHOT ON>
Many times? If you talk about FPGA Express, maybe :-)
<CHEAP_SHOT OFF>

>gate design with just a schematic editor. But a mixed approach, with
>highly efficient, schematic-drawn reusable elements alongside
>synthesized modules at the bottom level, and perhaps with a block
>schematic at the top does make sense. And this approach is more widely
>used than you may think.

Oh, I would agree. The block diagram is an improvement on a log-book
or the back of an envelope, but this is just some of what Renoir is
about.

>5 years ago, if, as an EE, you knew VHDL, then you were a prized
>specimen. If I'm right, before long, designers who can work at the gate
>level and drive schematic editors will be the rare and sought-after
>commodity.

I used to draw P and N wells and shove polygons of "active area",
metal and polysilicon around and then connect them up with little
black crosses. I haven't seen too much demand for that recently.

>The portability and productivity of HDL-based design are of undoubted
>benefit, but there is no reason to abandon the performance advantages of

Agree. The best flow is the one that gets a working product out the
door, to spec, and under budget. 

>designing with schematics, while we can do both together. Given the
>right tools, of course. ;-)

Whoa! I just have to respond to that (good natured, I'm sure) swipe.
(With apologies to all for what might appear to be an infomercial)

Without wishing to appear rude, do you know what Renoir is, and does?

I can create a top level "schematic" block diagram. I can then push
down into these blocks and create:

Another block diagram
A State machine
A Truth Table
A Flow Chart
My own HDL

I can create my own packages and libraries. I can have multiple
implementations of components defining which is to be the default
*view* used in a particular build. HDL to Graphics imports HDL files
and turns them, where possible, into graphics. Useful for working back
from old designs, or understanding customer designs quickly), or
documentation and maintenance. It's also OLE compliant, so
documentation becomes a little easier. 

With libraries, I can even directly use FPGA gate-level components,
such as from Xilinx, right down to AND2B1 and all those little CY4
elements if I need them. I can instantiate anything I like (design
re-use?) and stick designs in libraries for later. I just plonk them
on a schematic sheet, and wire them up as needed. (but they are all
VHDL or Verilog, not a proprietary netlist format)

I can even have a top level VHDL Entity that calls a Verilog previous
library core, which instantiates a VHDL Entity as a module, which
instantiates some 'gates', no problem, ad nauseum. No fighting to
co-ordinate three separate simulation kernels. All done in one kernel
- ModelSim, and all running quite happilly on a laptop. Plus many
orders of magnitude faster at functional simulation than a gate level
schematic sim (I would imagine?).

I've got Renoir source cross-probing to either Spectrum or Turbo
Writer. I can even click a transition in a state machine diagram and
go right to the code that it generated.

An important point with this HDL-centric flow is that the whole design
output is HDL text files (VHDL or Verilog). This helps to maintain
vendor independence of the design as much as possible. Not only in
terms of target technology, but also in terms of simulator, synthesis
and other downstream tools post design entry. I'm not sure I could run
a code-coverage tool on your proprietary gate-level schematic and
block diagram mixed with written VHDL and a state machine from
State-Cad, could I?

At the end of the day, you can even walk away with your whole Renoir
design (ie. all your intellectual property) as a bunch of plain text
HDL and go simulate it and synthesise it however and wherever you
like. I think that the absence of a proprietary format has some appeal
for the longevity and maintenance of old designs.

If you want to call Renoir "schematics", I guess you can, as it does
indeed involve drawing diagrams. However, keeping with HDL brings all
the benefits, plus those of a far more productive environment than
just symbols, nets and 'gates'. (IMHO)

That's it.

Cheers
Stuart

An employee of Saros Technology, The HDL Solutions Company:
Renoir
Model Technology
Exemplar Logic
TransEDA
www.saros.co.uk
(I sell these products, so paint me biased)

Article: 13591
Subject: Re: Array Range Legal?
From: rich katz <rich.katz@gsfc.nasa.gov>
Date: Thu, 10 Dec 1998 17:15:37 -0500
Links: << >>  << T >>  << A >>
Makarand Joshi wrote:

> Yes Rich,
> You are correct.
> It is perfectly legal to do this in VHDL as well as in Verilog;
> I dont see a reason why one would want to do so.
>
> -Makarand.

why?  er, why not!?!?!?!

if the output of our program is normally an array, then the s/w is simpler and
more reliable if it treats all cases the same, such as the case where the output
is reduced to a single bit (not normally done but we've used that case).
otherwise we have to change the port declarations and all of the constant
assignments in the code from " => ', making a mess of the system for the single
bit case.  i thought i explained that earlier.  as some fuzz-headed engineer
previously posted:

        > rich katz <rich.katz@gsfc.nasa.gov> wrote in article
        > <36687FA3.A8A81595@gsfc.nasa.gov>...
        > > hi,
        > >
        > > is the following code legal vhdl, with the starting and ending index
the
        > > same?
        > >
        > >         ZData : Out Std_Logic_Vector(0 downto 0)
        > >
        > > it's the output of vhdl-generating software and normally is a
        > > multiple-bit bus - however, the architecture permits single bit
        > > outputs.  is this ok or does it need to be recoded to be a Std_Logic

        > > signal.

it turns out that some synthesis software recognizes it, some barfs.  that's why
i asked, not being able to locate our copy of the lrm.

thanks for the help,

rk

===========================================================

> Suttinan Chattong wrote:
>
> > Hi there,
> >
> > I believe it is OK to do so.  I've used it once in simulation & synthesis,
> > and
> > it did not give any problems.
> >
> > Suttinan....
> >
> > rich katz <rich.katz@gsfc.nasa.gov> wrote in article
> > <36687FA3.A8A81595@gsfc.nasa.gov>...
> > > hi,
> > >
> > > is the following code legal vhdl, with the starting and ending index the
> > > same?
> > >
> > >         ZData : Out Std_Logic_Vector(0 downto 0)
> > >
> > > it's the output of vhdl-generating software and normally is a
> > > multiple-bit bus - however, the architecture permits single bit
> > > outputs.  is this ok or does it need to be recoded to be a Std_Logic
> > > signal.
> > >
> > > thanks a bunch
> > >
> > > rk
> > >
> > >



Article: 13592
Subject: CFP: Workshop On Cryptographic Hardware And Embedded Systems (CHES)
From: "Daniel V. Bailey" <bailey@wpi.edu>
Date: Thu, 10 Dec 1998 17:17:26 -0500
Links: << >>  << T >>  << A >>
    WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES)
    
                http://ece.WPI.EDU/Research/crypt/ches

                    Worcester Polytechnic Institute
                    Worcester, Massachusetts, USA
                         August 12 & 13, 1999

                         First Call for Papers

General Information

The focus of this workshop is on all aspects of cryptographic
hardware and embedded system design. The workshop will be a forum of
new results from the research community as well as from the industry.
Of special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submission from academia,
industry, and other organizations. All submitted papers will be
reviewed.

The topics of interest include but are not limited to:

   * Computer architectures for public-key cryptosystems
   * Computer architectures for secret-key cryptosystems
   * Reconfigurable computing and applications in cryptography
   * Cryptographic processors and co-processors
   * Modular and Galois field arithmetic architectures
   * Tamper resistance on the chip and board level
   * Architectures for smart cards
   * Tamper resistance for smart cards
   * Efficient algorithms for embedded processors
   * Special-purpose hardware for cryptanalysis
   * Fast network encryption
   * True and pseudo random number generators

Mailing List

If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to:  ches@ece.orst.edu


Instructions for Authors

Authors are invited to submit original papers. The preferred
submission form is by electronic mail to ches@ece.orst.edu. Papers
should be formatted in 12pt type and not exceed 12 pages (not
including the title page and the bibliography). The title page should
contain the author's name, address (including email address and an
indication of the corresponding author), an abstract, and a small
list of key words. Please submit the paper in Postscript or PDF. We
recommend that you generate the PS or PDF file using LaTeX, however,
MS Word is also acceptable. All submissions will be refereed.

Only original research contributions will be considered. Submissions
must not substantially duplicate work that any of the authors have
published elsewhere or have submitted in parallel to any other
conferences or workshops that have proceedings.

Workshop Proceedings

It is planned to publish the proceedings in Springer-Verlag's Lecture
Notes in Computer Science (LNCS) series. Notice that in order to be
included in the proceedings, the authors of an accepted paper must
guarantee to present their contribution at the workshop.

Important Dates

 Submission Deadline:          April 30th, 1999.
 Acceptance Notification:      June 15th, 1999.
 Final Version due:            July 15th, 1999.
 Workshop:                     August 12th & 13th, 1999.
 
NOTES: The CHES dates August 12 & 13 are the Thursday & Friday preceding
       CRYPTO '99 which starts on August 15.

Invited Speakers
	To be announced.

Program Chairs

All correspondence and/or questions should be directed to either of
the Program Chairs:

 Cetin Kaya Koc                       Christof Paar
 Dept. of Electrical & Computer       Dept. of Electrical & Computer
 Engineering                          Engineering
 Oregon State University              Worcester Polytechnic Institute
 Corvallis, Oregon 97331, USA         Worcester, MA 01609, USA
 Phone: +1 541 737 4853               Phone: +1 508 831 5061
 Fax: +1 541 737 1300                 Fax: +1 508 831 5491
 Email: Koc@ece.orst.edu              Email: christof@ece.wpi.edu

Program Committee

Gordon Agnew,  University of Waterloo, Canada
David Aucsmith,   Intel Corporation, USA
Ernie Brickell,  CertCo, USA
Wayne Burleson,   University of Massachusetts at Amherst, USA
Burt Kaliski,   RSA Laboratories, USA
Jean-Jacques Quisquater,   Universite Catholique de Louvain, Belgium
Christoph Ruland,   University of Siegen, Germany
Victor Shoup,   IBM Research, Switzerland
Michael Wiener,   Entrust Technologies, Canada

Location

WPI is in Worcester, the second largest city in New England. The city
is 80 km (50 miles) West of Boston and 280 km (175 miles) North-East
of New York City.

Worcester is home to a wealth of cultural treasures, many of which
are just a short distance from WPI. These include the historic
Higgins Armory Museum, which houses one of the world's largest
collections of armor; the EcoTarium (formerly New England Science
Center), one of the only museums in the country dedicated to
environmental education; and the beautifully restored Mechanics Hall,
one of America's finest concert halls. The Worcester Art Museum,
holding one of the nation's finest collections, and the
world-renowned American Antiquarian Society, with the largest
collection of items printed during the nation's colonial period, are
within two blocks of the WPI campus. Worcester is also well known for
its ten colleges, which cooperate through the Colleges of Worcester
Consortium.

Recreation areas within easy driving distance include Boston and Cape
Cod to the east, the White and Green mountains to the north, and the
Berkshires to the west.

August weather in New England is usually very pleasant with average
temperatures of 20 C (70 F).

Workshop Sponsors

This workshop has received generous support from Compaq - Atalla
Security Products, Intel, SITI. The organizers express their sincere
thanks.





Article: 13593
Subject: FPGA work at 3com
From: tonymart <tonymart@ne.mediaone.net>
Date: Thu, 10 Dec 1998 19:15:42 -0500
Links: << >>  << T >>  << A >>
FPGA designers wanted....

Anyone interested in designing and building custom FPGA emulation boards
to emulate >200K gate ASIC send you resume.
The location is Boxborough Mass.

thanks

Tony  Martuscello


Article: 13594
Subject: Re: Array Range Legal?
From: Makarand Joshi <mjoshi@quickturn.com>
Date: Thu, 10 Dec 1998 19:49:07 -0500
Links: << >>  << T >>  << A >>
I agree with your insight and would not have put forth the Q
if you were manually coding the VHDL. However, I thought
you were referring to the fact that the output was from a VHDL generation
software. Well, if so is the case,  ("technically speaking") shouldn't you
be regenerating the VHDL code again from this VHDL generation software?
Also, on another note you may want to recommend to the software company
to handle it in such a way that if the higher and lower indices are the same
(0 and 0 in your case) then they use std_logic instead of std_logic_vector (0
downto 0).
Just a thought.


rich katz wrote:

> Makarand Joshi wrote:
>
> > Yes Rich,
> > You are correct.
> > It is perfectly legal to do this in VHDL as well as in Verilog;
> > I dont see a reason why one would want to do so.
> >
> > -Makarand.
>
> why?  er, why not!?!?!?!
>
> if the output of our program is normally an array, then the s/w is simpler and
> more reliable if it treats all cases the same, such as the case where the output
> is reduced to a single bit (not normally done but we've used that case).
> otherwise we have to change the port declarations and all of the constant
> assignments in the code from " => ', making a mess of the system for the single
> bit case.  i thought i explained that earlier.  as some fuzz-headed engineer
> previously posted:
>
>         > rich katz <rich.katz@gsfc.nasa.gov> wrote in article
>         > <36687FA3.A8A81595@gsfc.nasa.gov>...
>         > > hi,
>         > >
>         > > is the following code legal vhdl, with the starting and ending index
> the
>         > > same?
>         > >
>         > >         ZData : Out Std_Logic_Vector(0 downto 0)
>         > >
>         > > it's the output of vhdl-generating software and normally is a
>         > > multiple-bit bus - however, the architecture permits single bit
>         > > outputs.  is this ok or does it need to be recoded to be a Std_Logic
>
>         > > signal.
>
> it turns out that some synthesis software recognizes it, some barfs.  that's why
> i asked, not being able to locate our copy of the lrm.
>
> thanks for the help,
>
> rk
>
> ===========================================================
>
> > Suttinan Chattong wrote:
> >
> > > Hi there,
> > >
> > > I believe it is OK to do so.  I've used it once in simulation & synthesis,
> > > and
> > > it did not give any problems.
> > >
> > > Suttinan....
> > >
> > > rich katz <rich.katz@gsfc.nasa.gov> wrote in article
> > > <36687FA3.A8A81595@gsfc.nasa.gov>...
> > > > hi,
> > > >
> > > > is the following code legal vhdl, with the starting and ending index the
> > > > same?
> > > >
> > > >         ZData : Out Std_Logic_Vector(0 downto 0)
> > > >
> > > > it's the output of vhdl-generating software and normally is a
> > > > multiple-bit bus - however, the architecture permits single bit
> > > > outputs.  is this ok or does it need to be recoded to be a Std_Logic
> > > > signal.
> > > >
> > > > thanks a bunch
> > > >
> > > > rk
> > > >
> > > >



Article: 13595
Subject: Re: Array Range Legal?
From: rk <rich.katz@gsfc.nasa.gov>
Date: Thu, 10 Dec 1998 22:04:15 -0500
Links: << >>  << T >>  << A >>
Makarand Joshi wrote:

> I agree with your insight and would not have put forth the Q
> if you were manually coding the VHDL. However, I thought
> you were referring to the fact that the output was from a VHDL generation
> software.

it is.

==============================================

>                        Well, if so is the case,  ("technically speaking") shouldn't
> you
> be regenerating the VHDL code again from this VHDL generation software?

sorry, confused here.  the idea is to take the output of the vhdl generation software
and stuff it into a vhdl synthesizer and make use of the output.  i wouldn't want to
have to write and put a post-processor on it.

===============================================

> Also, on another note you may want to recommend to the software company
> to handle it in such a way that if the higher and lower indices are the same
> (0 and 0 in your case) then they use std_logic instead of std_logic_vector (0
> downto 0).

hmmm ... i am the software "company."  originally it was coded such that upper and
lower indices could be the same.  and the response we got, which was unanimous, was
that this was legal vhdl.  on the other hand, having options for how the vhdl is coded
needlessly complicates the generation software, as the declaration, usage, and
assignments (when constants) must be done differently, depending on the case.  making
extra cases is a good way to make mistakes and makes the code harder to verify in
walk-throughs.  we found we are putting time into dealing with synthesizer problems
and not improving the "QoR" of the system, which is the goal of this thing.

well, that all sounds good, but in practice one synthesizer we use chokes and gags.
however, since it often produces superior results, we are recoding our generation s/w
based on the width of the output bus, since we can do that quicker than we can get the
synthesizer vendor to fix their code.

=================================================

> Just a thought.

rk

Article: 13596
Subject: Re: computer requirements for CAE systems
From: "Daniel Lang" <dblx@xtyrvos.caltech.edu>
Date: Thu, 10 Dec 1998 22:57:29 -0800
Links: << >>  << T >>  << A >>
Brian Drummond wrote in message <366f11ef.2778975@news.demon.co.uk>...
>On Mon, 07 Dec 1998 20:05:46 GMT, Todd Kline <todd@wgate.com> wrote:
>
>>I wanted an
>>ultra-wide/ultra-fast SCSI.  What I ended up with was the same old
>>enhanced IDE, not even ultra-IDE!  I couldn't convince my boss that disk
>>I/O performance was important.  I would be interested in hearing what
>>people recommend for disk I/O.
>
>The problem with SCSI of course is the cost hit.
>Is there any mileage in using a big cheap IDE for bulk storage, and a
>small (2 or 4GB) SCSI for workspace? What would you keep on each?
>
You may want to try enabling bus mastering (needs at least NT4.0 SP3).
See http://www.ntfaq.com/ntfaq/hardware29.html#hardware29 for more
information.

Daniel Lang  dblx@tyrvos.caltech.edu  (but remove the x)



Article: 13597
Subject: Re: HELP, Tool selection
From: z80@ds2.com (Peter)
Date: Fri, 11 Dec 1998 08:26:33 GMT
Links: << >>  << T >>  << A >>
I wonder why there appears to be *no* support for schematics?
Otherwise, it sounds very good. How much? How many users? How long in
beta before release?

>I can create a top level "schematic" block diagram. I can then push
>down into these blocks and create:
>
>Another block diagram
>A State machine
>A Truth Table
>A Flow Chart
>My own HDL


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.

Article: 13598
Subject: Need basic info on FPGA!
From: "TNT" <tim-cam@email.dk>
Date: Fri, 11 Dec 1998 10:15:56 +0100
Links: << >>  << T >>  << A >>
Hi

We are engineering sudents working on a projekt that involves basic
knowledge on FPGA.
Our main purpose is to implement by C++,  the intension though is to end up
with programming a Xilinx XC 4010 XL.
What we need at this point is an introduction to the following:

    - CLB
    - LUT
    - Macro's
    - The basic's of gate arrays

The only documentation on the subjekt we have so far is the "The practical
Xilinx designer lab book".

Thank you for any contribution what so ever.




Article: 13599
Subject: Re: Synthesis with Actel
From: nospam_ees1ht@ee.surrey.ac.uk (Hans)
Date: 11 Dec 1998 09:59:13 GMT
Links: << >>  << T >>  << A >>

Renzo,

Which version of ACTMAP are you using? The current version which is R3-1998.

Hans.


In article <367001aa.0@lps.tina.agr.st.com>, renzo.arce@st.com says...
>
>Hi,
>somebody know what mean the communication error during the 
>synthesis with ActMap of Actel Designer Series.
>
>ERROR:(VHDL-1769) Cannot split signal 'n15'
>
>I am using the family Actel 3200DX for synthesis an 64-bits
>multiplier.
>
>Thank you
>
>Renzo Arce
>renzo.arce@st.com



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