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Messages from 45925

Article: 45925
Subject: Re: EDIF netlist from XST
From: Juergen Otterbach <juergen.otterbach@t-online.de>
Date: Sun, 11 Aug 2002 15:31:38 +0200
Links: << >>  << T >>  << A >>
Dies ist eine mehrteilige Nachricht im MIME-Format.
--------------D55DDEF63C04103828511F42
Content-Type: multipart/alternative;
 boundary="------------6D2631D716B2C9C17BDF0995"


--------------6D2631D716B2C9C17BDF0995
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Content-Transfer-Encoding: 7bit

Hello,
in the past I could generate EDIF files in the ISE4.1 GUI:
Take an editor an open the *.xst file on the homedirectory of the project.
You can set the parameter as Kevin said:
-ofmt EDIF
but after closing the *.xst file you have to set write protection.
Using GUI will process alway to edif format.

Kind Regards Juergen Otterbach

Kevin Brace schrieb:

> MICHAEL ALEX wrote:
> >
> > Back in early June, Kevin Brace (I think) noted that one can generate an
> > EDIF netlist in Webpack if you run XST from a batch file.  I tried it
> > back then, and indeed it worked.  I recently upgraded my hard drive,
> > reinstalled WebPack, and have been using Webpack and ModelSIM.  However,
> > now when I try to generate an EDIF netlist using the XST command as
> > Kevin specified, I get an error message saying "XILINX environment
> > variable not set."  I didn't have this problem before, and XST still
> > generates the (groan) NGC netlist from the Webpack IDE.  There is
> > probably a simple solution, but I can't find it.  Any pointers?
> >
> > Thanks,
> > Michael
>
>         Someone else found out that, in addition to running XST from the
> command line, in case you are using ISE WebPACK 4.2, you can add the
> "-ofmt EDIF" option from ISE's GUI.
>
> http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=ad2sbv%248u0%2401%241%40news.t-online.com
>
> The only problem I found with this method is that ISE's GUI won't update
> the status of the design flow (i.e., Usually when the synthesis is done,
> an exclamation mark or a check mark appears next to "Synthesize".)
> because apparently ISE's GUI is monitoring for a .NGC file.
> I don't know how to get ISE to monitor a .EDN file instead of a .NGC
> file. (I will like to know that.)
> Anyhow, it appears, the difference between an EDIF netlist and an NGC
> encrypted netlist is only that the design gets encrypted with NGC, so
> what I usually do is that when I want an EDIF netlist, I add "-ofmt
> EDIF", and when I want ISE's design flow to work correctly, I remove
> that option.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)




Article: 45926
Subject: Re: xilinx RLOC usage
From: hamish@cloud.net.au
Date: 11 Aug 2002 13:32:54 GMT
Links: << >>  << T >>  << A >>
Nahum Barnea <nahum_barnea@yahoo.com> wrote:
> Hamish, ThankX for this great help !
> Concerning the 1'st solution, I understand the effect for RG1 and RG2,
> now I want similiar solution for RG3 and RG4 BUT I do'nt want to put any
> contraint between RG1-RG2 to RG3-RG4.
> Is it possible ?

Yes. You need to assign them to different "user sets" (U_SETs).

INST RG1 U_SET = "set1";
INST RG2 U_SET = "set1";
INST RG1 RLOC = "X0Y0";
INST RG2 RLOC = "X9Y9";

INST RG3 U_SET = "set2";
INST RG4 U_SET = "set2";
INST RG3 RLOC = "X0Y0";
INST RG4 RLOC = "X9Y9";

There are some other options for sets too which you can find in the
manuals (H_SETs and HU_SETs).

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 45927
Subject: Re: unloading a fast ADC
From: Ray Andraka <ray@andraka.com>
Date: Sun, 11 Aug 2002 18:52:37 GMT
Links: << >>  << T >>  << A >>
The converter we used was an Atmel TS8388BF, and we followed it with a
TS81102G0 1:4/8 Demux chip.  That DEMUX is nice because it also provides a DR
at the output data rate, so interfacing it to the FPGA looks like simply
interfacing 4 or 8 ADCs with a common DR at 1/4 or 1/8 the sample frequency.
It basically gives you a next-to-no-thought-required solution to getting the
high speed sampled data into the FPGA without having to push the I/O specs to
the limits.

glen herrmannsfeldt wrote:

> >John Larkin wrote:
>
> >> I'm thinking about grabbing a bunch of samples of a burst analog event
> >> that will last maybe 100 ns or so. Maxim makes an ADC, the MAX104,
> >> that samples up to 1 GSPS and outputs alternate samples on two 8-bit
> >> PECL ports.
> (snip)
> Then Ray Andraka <ray@andraka.com> writes:
>
> >The LVDS specs on some of the faster chips will handle that, but the
> >internal design just to get the data reliably onto the chip is not
> >trivial, and involves treating the data as DDR data.  VirtexII would make
> >this easier for you, but still a major PITA to pull it off.  We did a
> >similar design earlier this year with an Atmel 8 bit 1GS/sec converter
> >plus a sister chip (also Atmel)  that packed 4 samples into one 32 bit
> >word and transferred that at a much more manageble 240 MHz into a virtexE
> >over LVDS lines.  That was a lot easier than trying to run at the hairy
> >edge using interface specs that were not directly compatible.
>
> My thought would be to put some PECL latches on to get it down to
> four 8 bit values at 250MHz each.
>
> Another choice would be to gate directly into a RAM array, then later
> read it out at the desired speed.  This would be if you didn't need
> real time processing.
>
> --glen

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45928
Subject: Re: I seek a FPFA developer
From: "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org>
Date: Sun, 11 Aug 2002 15:08:54 -0400
Links: << >>  << T >>  << A >>

"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message
news:aj4gvk$2ep9$1@agate.berkeley.edu...
> In article <2002810-15296-214605@foorum.com>,
> Damien  <damien_legieda@hotmail.com> wrote:
> >
>
>> I seek a FPGA developer, serious, motivated and having spare time able to
be
>> invested in an interesting challenge.

[deleted]
>
> If you aren't gonna pay, you would be best saying what the job IS.

And could you also unload your mailbox so that it will accept more
messages?



Article: 45929
Subject: articles about FPGA based DSP design
From: "Hristo Stevic" <hristostev@yahoo.com>
Date: Sun, 11 Aug 2002 19:55:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
hello,
for a thesis chapter, i am looking for some articles, *up to date*,
about FPGA as promising platform for hardware design
The pros and the cons

how the futue looks like with it
many thanks


-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 45930
Subject: Re: articles about FPGA based DSP design
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 12 Aug 2002 08:56:39 +1200
Links: << >>  << T >>  << A >>
Hristo Stevic wrote:
> 
> hello,
> for a thesis chapter, i am looking for some articles, *up to date*,
> about FPGA as promising platform for hardware design
> The pros and the cons
> 
> how the futue looks like with it
> many thanks

Just what does 'promising platform for hardware design' mean ?

Does this mean used in the design process, but not in the final
product ? ( As in Asic design / simulation )

or, does it mean as a device that ships in final products.

 I'd go to http://www.optimagic.com/companies.html
and then get the 'party line' from each vendor, and average
over these to find a more correct industry picture..

-jg

Article: 45931
Subject: Re: EDIF netlist from XST
From: dorn@apl-landau.de (Hans-JŁrgen Dorn)
Date: Sun, 11 Aug 2002 22:15:38 GMT
Links: << >>  << T >>  << A >>
On Sun, 14 Jul 2002 23:24:44 -0500, Kevin Brace
<killspam4hotmail@killspam4kevinbraceusenet.com> wrote:

>
>The only problem I found with this method is that ISE's GUI won't update
>the status of the design flow (i.e., Usually when the synthesis is done,
>an exclamation mark or a check mark appears next to "Synthesize".)
>because apparently ISE's GUI is monitoring for a .NGC file.
>I don't know how to get ISE to monitor a .EDN file instead of a .NGC
>file. (I will like to know that.)
>Anyhow, it appears, the difference between an EDIF netlist and an NGC
>encrypted netlist is only that the design gets encrypted with NGC, so
>what I usually do is that when I want an EDIF netlist, I add "-ofmt
>EDIF", and when I want ISE's design flow to work correctly, I remove
>that option.
>
>
>
>Kevin Brace (In general, don't respond to me directly, and respond
>within the newsgroup.)


If you use the option "-ofmt ngo_edif" you get both EDIF and NGO
files, and the GUI doesn't get confused.

Regards Hans



Article: 45932
Subject: Re: articles about FPGA based DSP design
From: Ray Andraka <ray@andraka.com>
Date: Mon, 12 Aug 2002 00:02:42 GMT
Links: << >>  << T >>  << A >>
I've built a business on doing nothing but DSP in FPGAs, and if I may say
so myself business has been good.  I've got a number of papers and
articles on my website dealing with DSP designs in FPGAs.  The most
recent is a bit more than a year old.  Right now, DSP in FPGAs has seemed
to ahve gotten past the acceptance stage (people now generally accept
that DSP can be done with FPGAs, contrast that with 5 years ago when
people were practically commenting "you can do math in those things?").
Sytem level tools lower the bar enough for someone who is not DSP
hardware saavy to get into an FPGA based DSP processor, but not enough
for a practical design.  By practical design I mean on that is efficient
enough to be cost effective, and the fault is not the devices or even the
tools, but rather a lack of knowledge in hardware DSP design.

First there is relatively very little expertise in DSP hardware as
opposed to DSP software out there, since most of the DSP work in the last
quarter century has been targeted at software platforms.  The algorithms
developed in this time are generally optimized to software implementation
and map quite poorly to hardware, and frankly many of the good hardware
designers do not also have the DSP expertise needed to do the algorithmic
work needed for a smooth transition to hardware.  Unfortunately, I don't
think tools will ever fully bridge the gap.  So far, I have found it is
much easier to train a hardware designer to do signal processing than it
is to train a DSP saavy software expert to do hardware design.  The
bottom line is the transition to a hardware based DSP system is not a
trivial transition, but it is well worth the rewards if executed well.

Jim Granville wrote:

> Hristo Stevic wrote:
> >
> > hello,
> > for a thesis chapter, i am looking for some articles, *up to date*,
> > about FPGA as promising platform for hardware design
> > The pros and the cons
> >
> > how the futue looks like with it
> > many thanks
>
> Just what does 'promising platform for hardware design' mean ?
>
> Does this mean used in the design process, but not in the final
> product ? ( As in Asic design / simulation )
>
> or, does it mean as a device that ships in final products.
>
>  I'd go to http://www.optimagic.com/companies.html
> and then get the 'party line' from each vendor, and average
> over these to find a more correct industry picture..
>
> -jg

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45933
Subject: 485 core
From: "Duane Perry" <dlp_sr@yahoo.com>
Date: Sun, 11 Aug 2002 21:17:15 -0400
Links: << >>  << T >>  << A >>
Does anyone know of a serial 485 type IP?



Article: 45934
Subject: Advice regarding clock gating
From: Vikram Chandrasekhar <cvikram@ruf.rice.edu>
Date: Sun, 11 Aug 2002 21:23:17 -0500
Links: << >>  << T >>  << A >>
Hi everyone,
I am employing clock-gating on a Virtex-II FPGA using the BUFGMUX unit,
in order to turn off idle functional units, for reducing dynamic power
dissipation in my design.

However, when I use XPower (the power estimator tool offered by Xilinx) to
estimate the power dissipation, it does not report the correct activity
rate for the gated clock. Infact, the switching frequency reported by it
is the same as the global ungated clock. Does it mean that it does not
take the activity rate of a clock into account? Is there any way that I
can make Xpower understand the clock being gated??

Any help would be greatly appreciated.
Thank you
Vikram Chandrasekhar.



Article: 45935
Subject: Synthesis Verilog to ASIC
From: "Reala" <manfield.chow@scoreconcept.com>
Date: Mon, 12 Aug 2002 11:32:31 +0800
Links: << >>  << T >>  << A >>
Hi,

I wrote a verilog code. Then, I ran Modelsim to verify the design.
If I implement the design by Altera, I can use LeonardaSpectrum for
synthesis.
However, i want to implement the design by ASIC. What
information/software/library needed for this approach? Thank you.

Reala






Article: 45936
Subject: Re: 485 core
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Mon, 12 Aug 2002 06:03:37 GMT
Links: << >>  << T >>  << A >>
On Sun, 11 Aug 2002 21:17:15 -0400, "Duane Perry" <dlp_sr@yahoo.com>
wrote:

>Does anyone know of a serial 485 type IP?

'485 is actually a voltage / current / impedance level specification.

Try searching for "UART".

Allan.

Article: 45937
Subject: Re: ASIC conversion
From: kayrock66@yahoo.com (Jay)
Date: 11 Aug 2002 23:15:52 -0700
Links: << >>  << T >>  << A >>
One of the things you left out is that the FPGA vendors are claiming a
gate equivalency for the on chip ASIC-like block ram.  These rams can
be quite large and are the main contributer to the inflated "gate"
numbers.

One way to look at it is that if the design fits in an FPGA, it would
be considered a small ASIC, often pad limited (die size dictated by
I/O ring).

Regards

prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0208091212.52694a29@posting.google.com>...
> Hi,
> 
> Given below is the method I use to estimate the number of ASIC gates
> my design might use.
> 
> 1. 10000 logic elements used on EP20K1500E (Apex20KE).
> 2. 51480 LE's correspond to 1.5e+6 'FPGA' gates on EP20K1500E.
> 3. Hence each LE = 29.13 'FPGA' gates.
> 4. 10000 LE's = 291,300 'FPGA' gates.
> 5. ASIC gates = 291300/4 = 72,825 'ASIC' gates.
> 
> Is this correct ? I understand this is a rough estimate. Would the
> gurus consider this pessimistic or optimistic if low gate counts was
> the goal ? Would there be a recommendation for a more correct solution
> similar to the above approach ?
> 
> Thanks,
> Prashant

Article: 45938
Subject: Re: Power saving with Clock gating
From: John Blaine <john.blaine@xilinx.com>
Date: Mon, 12 Aug 2002 09:34:00 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------8BFD2DE634D8E9E748BDF149
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dear Vikram

XPower will look in the PCF file for the period of the clock and use this
value
to set the frequency in XPower. To workaround it you should manually set the
clock frequency by hand in XPower.

John

Vikram Chandrasekhar wrote:

> Hi everyone,
>
> I am new to this group, so I am all excited about joining this fountain og
> knowledge. I hope that a small query of mine can be answered....:)
>
> My issue is this:
>
> I am employing clock-gating on a Virtex-II FPGA using the BUFGMUX unit,
> in order to turn off idle functional units, for reducing dynamic power
> dissipation in my design.
>
> However, when I use XPower (the power estimator tool offered by Xilinx) to
> estimate the power dissipation, it does not report the correct activity
> rate for the gated clock. Infact, the switching frequency reported by it
> is the same as the global ungated clock. Does it mean that it does not
> take the activity rate of a clock into account? Is there any way that I
> can make Xpower understand the clock being gated??
>
> Any help would be greatly appreciated.
> Thank you
> Vikram Chandrasekhar.
>
> Vikram Chandrasekhar
> Graduate Student
> Electrical and Computer Engg.
> Rice University
> Ph:(713)529 9819 (R)
>    (713)348 2897 (O)
> www.ece.rice.edu/~cvikram/index.html



Article: 45939
Subject: changing width of array
From: maimuna_a@nrsa.gov.in (maimuna)
Date: 12 Aug 2002 02:45:03 -0700
Links: << >>  << T >>  << A >>
the width of the array which i have used in my program changes with some inputs.
is there any way to set the width of the array according to the inputs.
if so please tell me

Article: 45940
Subject: What does the question lie in?
From: "Yx Jiang" <yxjiang2002@sina.com>
Date: Mon, 12 Aug 2002 18:02:02 +0800
Links: << >>  << T >>  << A >>
Hi,
When I translate the design(using the sum of product example provided by
Xilinx Inc.),in the message window it informs me that

"ISE Auto-Make Log File
-----------------------

Updating: Implement Design

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1i - ngdbuild E.30
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd d:/xilinx/mysumofproduct/_ngo -nt timestamp -p
xc2v3000-bf957-5 sop_subm.edf sop_subm.ngd

Launcher: "sop_subm.ngo" is up to date.
Reading NGO file "d:/xilinx/mysumofproduct/_ngo/sop_subm.ngo" ...
Reading component libraries for design expansion...

Checking timing specifications ...

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'and_chainx' with type 'AND_CHAIN' is
   unexpanded. Symbol 'AND_CHAIN' is not supported in target 'virtex2'.
ERROR:NgdBuild:604 - logical block 'and_chainx_5' with type 'AND_CHAIN' is
   unexpanded. Symbol 'AND_CHAIN' is not supported in target 'virtex2'.
ERROR:NgdBuild:604 - logical block 'and_chainx_3' with type 'AND_CHAIN' is
   unexpanded. Symbol 'AND_CHAIN' is not supported in target 'virtex2'.
ERROR:NgdBuild:604 - logical block 'and_chainx_4' with type 'AND_CHAIN' is
   unexpanded. Symbol 'AND_CHAIN' is not supported in target 'virtex2'.

NGDBUILD Design Results Summary:
  Number of errors:     4
  Number of warnings:   0


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "sop_subm.bld"...
EXEWRAP detected a return code of '2' from program 'ngdbuild'

Done: failed with exit code: 0002."

What's wrong with the design?

Thanks,
Yx Jiang




Article: 45941
Subject: Re: What does the question lie in?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 12 Aug 2002 12:14:30 +0100
Links: << >>  << T >>  << A >>


Yx Jiang wrote:

>

<snip>

>
> What's wrong with the design?
>
> Thanks,
> Yx Jiang

You need to find out where ``AND_CHAIN'' is coming from. Its either:

(1) A `primitive' being generated by your synthesiser and output into an EDIF
file.

(2) A `black box' module of your own for which NGDBUILD cannot find an EDIF or
.nmc file.

In case #1 the reason is most likely that you are synthesising to the wrong
device, or no device at all.

If that doesn't help then post the source code for the combined mighty
intellects of the NG to examine.



Article: 45942
Subject: ModelSim takes forever
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Mon, 12 Aug 2002 16:02:53 +0200
Links: << >>  << T >>  << A >>
Hi all,

I'm trying to simulate a double handshake protocol in Verilog. My
synthesizeable code is supposed to run in a SpartanIIe, the testbench
simulates a PC's parallel port programmed in Linux.

ModelSim (which came with the WebPack) does not produce any result or error
message. It just stands there consuming CPU. The code worked when I
simulated the PC being the master. But it fail when I simulate the PC
answering the handshake.

What happens is that the synthesizeable code writes a data word, sets
"transmitting" high, waits for "pc_read" to get high, sets "transmitting"
low, waits for "pc_read" to get low, then sends a new data word. So the
below code that simulates the PC waits for "transmitting == 1", sets
"pc_read" high, waits for "transmitting == 0", sets "pc_read" low.

 initial
 begin
  #1 clk_100 = 0; clk_sd = 0; reset_local = 0; // start of reset and clocks
  #40 reset_local = 1; // done resetting
  //pc_read = 0; // pc isn't reading anything

  #1 din = 1; // generate some input data to a parallel-serial converter
  #1000 din = 0;
// more din_sd lines are generated the same way. Plenty of #1000... snipped
for convenience
 end

 always
  #5 clk_100 = ~clk_100; // 50% clock running 100MHz

 always
  #500 clk_1 = ~clk_1; // 50% clock running at 1MHz

 always
 begin
//  #13000 pc_read = ~pc_read; // this line worked just fine. It simulates
the PC being the master.
  if (transmitting == 1)
   #10 pc_read = 1;   // simulate PC's handshake when FPGA is master. This
takes forever!
  else if(transmitting == 0)
   #10 pc_read = 0;
 end

endmodule


Regards,

BÝrge




Article: 45943
Subject: Re: ModelSim takes forever
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Mon, 12 Aug 2002 16:43:00 +0200
Links: << >>  << T >>  << A >>
Found a typo. Fixed below. But doesn't make the code run any better.

BÝrge

"BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in
message news:1029160973.660093@halvan.trd.sintef.no...
> Hi all,
>
> I'm trying to simulate a double handshake protocol in Verilog. My
> synthesizeable code is supposed to run in a SpartanIIe, the testbench
> simulates a PC's parallel port programmed in Linux.
>
> ModelSim (which came with the WebPack) does not produce any result or
error
> message. It just stands there consuming CPU. The code worked when I
> simulated the PC being the master. But it fail when I simulate the PC
> answering the handshake.
>
> What happens is that the synthesizeable code writes a data word, sets
> "transmitting" high, waits for "pc_read" to get high, sets "transmitting"
> low, waits for "pc_read" to get low, then sends a new data word. So the
> below code that simulates the PC waits for "transmitting == 1", sets
> "pc_read" high, waits for "transmitting == 0", sets "pc_read" low.
>
>  initial
>  begin
>   #1 clk_100 = 0; clk_1 = 0; reset_local = 0; // start of reset and clocks
>   #40 reset_local = 1; // done resetting
>   //pc_read = 0; // pc isn't reading anything
>
>   #1 din = 1; // generate some input data to a parallel-serial converter
>   #1000 din = 0;
> // more din_sd lines are generated the same way. Plenty of #1000...
snipped
> for convenience
>  end
>
>  always
>   #5 clk_100 = ~clk_100; // 50% clock running 100MHz
>
>  always
>   #500 clk_1 = ~clk_1; // 50% clock running at 1MHz
>
>  always
>  begin
> //  #13000 pc_read = ~pc_read; // this line worked just fine. It simulates
> the PC being the master.
>   if (transmitting == 1)
>    #10 pc_read = 1;   // simulate PC's handshake when FPGA is master. This
> takes forever!
>   else if(transmitting == 0)
>    #10 pc_read = 0;
>  end
>
> endmodule
>
>
> Regards,
>
> BÝrge
>
>
>



Article: 45944
(removed)


Article: 45945
Subject: Re: Programming bits reverse engineering
From: jetmarc@hotmail.com (jetmarc)
Date: 12 Aug 2002 07:56:12 -0700
Links: << >>  << T >>  << A >>
> Given that you can place a Micro-Blaze uP in your design, you could have
> the part call home, and get its authorization to perform its function if
> and only if the customer was a valid one.

It should be fairly easy to locate the Instruction memory for the
Microblaze (probably a Block RAM).  After the program is extracted,
it can be disassembled. A crack can be developped, that disables
the call-home feature.  This crack can then be translated back
into the FPGA bitstream, so that it becomes valid code for the
Microblaze.  Desktop software demonstrates, how even sophisticated
self-encrypting protection schemes fail.

The most effective way is to split essential secrets (eg key material)
over as many different components as possible.  The cost for the
attacker goes up, and motivation goes down (especially for the casual
hacker at home - those guys who pretend to write a linux driver for
your security gadget).

As others have pointed out already:  if the attack is more expensive
than the protected information, it is not worth attacking.

Marc

Article: 45946
Subject: FPGA a promising platform for hardware design...need articles
From: hristostev@yahoo.com (hristo)
Date: 12 Aug 2002 08:15:46 -0700
Links: << >>  << T >>  << A >>
hello,
for a thesis chapter, i am looking for some articles, *up to date*,
about FPGA as promising platform for hardware design
The pros and the cons

how the futue looks like with it

Article: 45947
Subject: Reconfiguration in Xilinx FPGA
From: rxv20@po.cwru.edu (Ramakrishnan)
Date: 12 Aug 2002 08:35:14 -0700
Links: << >>  << T >>  << A >>
Hi,
   I have a few questions with regard to Xilinx 4000 series FPGA.

1. I have designed a architecture in VHDL which contains memories ,
functional units and interconnection matrices . This architecture is
basically for performing various kinds of functions like bandpass
filters, cosine and various other ones. I wanted to implement this
architecture in Xilinx FPGA and test it out. I have some questions
regarding this.

a.I have a text file generated by a C program which plugs in all the
important values to the architecture and each and every application
has a unique file on its own. Now suppose i wanted to implement few of
the applications in the FPGA board.
I wanted to know whether it would be possible to download these text
files for the applications in someway or another to the FPGA board
memory and then after the successful completion of one application,
reconfigure the FPGA to start the next application , by picking up the
second text file and then so on and so forth.
The problem i think would like in the fact that some of the
applications that i choose to implement would use fewer memories in my
VHDL architecture than others. So how would i be able to overcome this
problem.

Is it possible to do this at all and am i making any  sense in trying
to do this ?.

I would really appreciate if someone could give some insight on this.

Thanks,

Ramakrishnan.

Article: 45948
Subject: Re: ModelSim takes forever
From: vhdlcohen@aol.com (VhdlCohen)
Date: 12 Aug 2002 15:51:20 GMT
Links: << >>  << T >>  << A >>
>ModelSim (which came with the WebPack) does not produce any result or error
>message. It just stands there consuming CPU. 
I understood that ModelSim that comes with WebPack is limited in the size of
the program. If the program is too large, ModelSim has built-in stops to slow
it down. 
Nothing in life is FREE!
Ben Cohen 

Article: 45949
Subject: Re: Reconfiguration in Xilinx FPGA
From: "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org>
Date: Mon, 12 Aug 2002 12:08:19 -0400
Links: << >>  << T >>  << A >>
"Ramakrishnan" <rxv20@po.cwru.edu> wrote in message
news:15cf85fc.0208120735.1884e326@posting.google.com...
> Hi,
>    I have a few questions with regard to Xilinx 4000 series FPGA.
>
[deleted]
> The problem i think would like in the fact that some of the
> applications that i choose to implement would use fewer memories in my
> VHDL architecture than others. So how would i be able to overcome this
> problem.
>
Then why not create a file for each memory not used in all the tests, that
loads this memory with random data, and use the resulting files to load any
memory not used in the current test so that all the memories end up
loaded?





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