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Messages from 45675

Article: 45675
Subject: Re: FPGA performance matrix..
From: Ray Andraka <ray@andraka.com>
Date: Wed, 31 Jul 2002 17:39:51 GMT
Links: << >>  << T >>  << A >>
Since the FPGA is simply a vehicle to carry a digital circuit design,
there is not really a way to quantify the performance in the way you
desire.  The performance of an FFT, for example depends on tradeoffs
made in the design, and ultimately on the rate at which the design is
clocked.  One can trade area for clock cycles.  The maximum clock
frequency is also dependent on those design tradeoffs, the skill of the
designer, the place and route solution and other factors.  For example,
our 16 point FFT core is both smaller and considerably faster (240
MS/sec in virtexE-8) than the xilinx FFT core due to differences in the
design approach and the level of effort applied to optimizing it. One of
the advantages of designing custom hardware is that you can usually
increase the performance by adding more parallel paths (operations) in
the logic.  That can't be done with a sequential processor.

Autofuzz wrote:

> Hi,
> I'm curious if it's possible to quantify the performance of FPGA's..
> i.e in terms of Operations per second.
>
> What i'm really confused about is when say the FPGA is doing FFT
> computations it must do it at say X ops/sec, but while the same chip
> is doing a DCT it would do it at Y ops/sec. how can one quantify it?
> more over if one part of the fpga is doing FFT and another part is
> doing a DCT how many ops does that make it..
>
> thanks,
> Auto

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45676
Subject: logicore pci macro in virtex problem
From: "jf hasson" <jfhasson@club-internet.fr>
Date: Wed, 31 Jul 2002 19:53:12 +0200
Links: << >>  << T >>  << A >>
Hi,

I have been working on the pci macro from xilinx (v3.0) on a virtex E and I
have a little problem. My design is target only and should be able to accept
burst transfers read or write. Burst transfers, read or write, any number,
are correct (the target is a RAM inside the FPGA). Then i try to test burst
transfers in which the initiator inserts wait states in the burst (actually
IRDY goes alternatively 0 and 1 during the burst). In this case, a write
memory burst is fine but a read memory burst of what have been written is
not. For example :the initiator writes 0x11111111, 0x00000001,0x00000002,
... and i read in a burst with wait states starting after 0x00000001 :
0x11111111, 0x00000001,0x0000000X, ... There seems to be a conflict on the
AD_IO bus but the ADIO bus (the one on the user side of the macro) is not
improperly driven (no X). The X is in bit format  001x which would lead me
to a believe in a conflict on the first bit of the AD_IO bus !!! What signal
am i missing here that improperly driven gives such a behavior ? Does anyone
have a clue ? By the way a burst read of the same area without wait states
is fine.

Thanks in advance,

J.F.



Article: 45677
Subject: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
From: emanuel stiebler <emu@ecubics.com>
Date: Wed, 31 Jul 2002 18:53:40 -0600
Links: << >>  << T >>  << A >>
Even when I check "disable BUSHOLD circuitry"
it doesn't change.

And I check it with a scope. The value B"1110_1100_1110_0111" stays
on the bus, regardless of the status of rstout.

So, anything else to check ?!?!

Thanks

"M. Randelzhofer" wrote:
> 
> If the buskeepers are enabled (default), the last state is held in tristate.
> 
> MIKE
> 
> "emanuel stiebler" <emu@ecubics.com> schrieb im Newsbeitrag
> news:3D456B80.A4455AC9@ecubics.com...
> > Hi all,
> >
> > I have this very small vhdl segment, I try to put in a 95144xl cpld.
> > Using ISE4.2, XST.
> >
> > The problem I "suspect" is, that the "d" bus doesn't go tristate,
> > even when "rstout" is not active. What am I missing ?
> >
> > thanks,
> > emanuel
> >
> > P.S. "suspect" means, that some chip on the bus is blocking the bus.
> > And there are only three chips on it.
> >
> > ----------cut ------------------
> >
> > library IEEE;
> > use IEEE.std_logic_1164.all;
> >
> > entity cpld is
> > port (
> > rstout:  in STD_LOGIC;     -- enable signal
> >         d: out STD_LOGIC_VECTOR(15 downto 0); -- databus
> > );
> > end cpld;
> >
> > architecture cpld_arch of cpld is
> >
> > begin
> > d <= B"1110_1100_1110_0111" when rstout = '0' else "ZZZZZZZZZZZZZZZZ";
> > end cpld_arch;

Article: 45678
Subject: Re: tone detection...
From: jetmarc@hotmail.com (jetmarc)
Date: 31 Jul 2002 18:56:05 -0700
Links: << >>  << T >>  << A >>
> > What I have is two frequencies I want a high for 1 and a low 
> > for the other.
> 
> And what if neither is present? :-)

Good point!  The question could be interpreted as if the input signal
was guaranteed to be either freq #1 or freq #2.  In this case, a
single DPLL would suffice to produce the desired output.

If, however, the signal may be "any" input, it depends on how much of
the analog signal remains in the "TTL pulse train".  PCM?  Or 1-bit
treshold "ADC"?

A good (software) algorithm to detect single tones is the Goertzel
algorithm.  The result is an approximation of the DFT, but calculation
is done as IIR filter.  Many DTMF detection appnotes are based on it.

For hardware (VHDL) it may be better to implement two FIRs as narrow
bandpass filters (centered at one frequency each).  The output of
both can be compared to produce the result.  Hysteresis and/or feedback
from bit clock recovery can help the comparator in the decision process.

Special techniques exist for modulated data.  MSK for example is
best demodulated by auto-correlation.  But this is way DSP.

Marc

Article: 45679
Subject: Re: Name of reset net
From: spam_hater_7@email.com (Spam Hater)
Date: Thu, 01 Aug 2002 02:35:42 GMT
Links: << >>  << T >>  << A >>

It doesn't matter.

The synthesizer will find the signal that resets all the flip flops,
and assign it to the global reset line.

If you include the start-up block, you can drive the global line via
GSR.  But you can't get at the global reset directly.

Check the warning messages carefully, and you'll see the reset net
assignment in action.

IMHO, name the reset line either 'RESET' if it's active high, or
'RESET_n' if it's active low.

NB:  Use only ONE flavor of reset in your design.  Choose either
active high or active low NOW.  The Xilinx synthesizer likes that much
better.  IIRC, it likes active high -slightly- more...


On Wed, 31 Jul 2002 16:01:08 +0200, "BÝrge Strand"
<borge.strand.remove.if.not.spamming@sintef.no> wrote:

>Hi all, here's a new newbie question from me:
>
>On a Spartan IIE, what is the net name that Verilog uses for the global
>reset? I guess this signal is active low.
>
>Regards,
>
>BÝrge
>
>


Article: 45680
Subject: Re: Dual Port Block RAM
From: mrmikehicks@earthlink.net
Date: Thu, 01 Aug 2002 03:59:43 GMT
Links: << >>  << T >>  << A >>
On 30 Jul 2002 06:37:55 -0700, brimdavis@aol.com (Brian Davis) wrote:

snip..snip..
Brian, that explains why, even after I thought I had it fixed (with
Michael's solution), I had to reverse the narrow and wide buses. I am
saving 36 bit words starting at location 0 and when pulling them out
as 72 bit words, I want the 36 bit word at location 0 to be in the
'top' half of the 72 bit word. I guess this makes it a big-endian
scheme for the wide port so trying to do this with coregen would have
also been a big mystery. Here's the big-endian mapping:

            dob(7 downto 4) => bramb_data2fr(7 downto 4), 
            dob(3 downto 0) => bramb_data2fr(43 downto 40) 
vice
            dob(3 downto 0) => bramb_data2fr(7 downto 4), 
            dob(7 downto 4) => bramb_data2fr(43 downto 40) 
...
    Thanks to all
     Mike

>take a look at this old thread:
>
>http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm 010813225155.01553.00000107%40mb-ci.aol.com&rnum=7
>
>Brian


Article: 45681
Subject: Re: VirtexE : OrCAD capture part symbol
From: "Austin Franklin" <austin@dark99room.com>
Date: Thu, 1 Aug 2002 00:07:15 -0400
Links: << >>  << T >>  << A >>
This is not meant as a slight at all...but...it simply amazes me that this
EXACT same question is asked ALL the time here, and only for OrCAD....  Is
it that OrCAD users don't know how to create their own symbols???  What
gives with this?

"Jerry" <jerryl@adaptivenetworks.com> wrote in message
news:ee782d9.-1@WebX.sUN8CHnE...
> Does anyone know where I can find an ORCAD capture library symbol for a
PQ240 VirtexE part?



Article: 45682
Subject: about amplify/synplify
From: sdrg <djd@sdfjg.zlfjv>
Date: Thu, 1 Aug 2002 01:10:48 -0700
Links: << >>  << T >>  << A >>
as we know,amplify of synplicity is a physical optimization tool,and synplify is logic synthesis tool.can i directly run place&route of xilinx after it was synthesised by amplify and not synplify?

Article: 45683
Subject: Re: about amplify/synplify
From: "Daryl" <e-engineer@eastday.com>
Date: Thu, 1 Aug 2002 16:58:56 +0800
Links: << >>  << T >>  << A >>

"sdrg" <djd@sdfjg.zlfjv> wrote in message news:ee78334.-1@WebX.sUN8CHnE...
> as we know,amplify of synplicity is a physical optimization tool,and
synplify is logic synthesis tool.can i directly run place&route of xilinx
after it was synthesised by amplify and not synplify?

as I know, amplify work between synthesis and p&r. always, amplify run
together with synpify pro; after synthesize the design by synpify pro which
also estimates the timing after routing, you could analyze the HDL by
amplify software to find out the citical path, and then generate the
constraint file to p&r tools to resolve it.
so, you see, amplify is not a sole tool.
I dont know if you want to use amplify to create a hard macro where one
prefer not to employ systhesis tools. I have no experience on this.

Best Regards,

Daryl



Article: 45684
Subject: Re: Pipelined Multiplier Implemented in Slices in Virtex II
From: ed.moore@snellwilcox.com (Edward Moore)
Date: 1 Aug 2002 03:43:54 -0700
Links: << >>  << T >>  << A >>
Ben,

For Leonardo to fully pipeline the multiplier you need to add
registers on the output for every internal stage. Leonardo will move
the registers into the internal logic. This is explained in the
Leonardo Users Manual.

For a 14x10 you should need 4 registers; one for the 14 by 2 input
stages,
and three for the adder tree. 
Extra registers on the inputs will speed things up a bit too.

Make sure you set the variable 'virtex2_multipliers' to false, so
Leonardo doesn't use embedded multipliers.

Leonardo's results should run at about 180 Mhz in a V2-4, not
floorplanned.
Alternatively, you could build a smaller and faster multiplier from
primitives.

--
Ed

bmhowe@yahoo.com (Ben Howe) wrote in message news:<df26a773.0207301042.1a6ae128@posting.google.com>...
> I am trying to implement a 14x10 multiplier into slices in the Virtex
> II (not the dedicated multipliers) using LeonardoSpectrum and Xilinx
> ISE 4.1i.  I have added a register after the multiply so that
> LeonardoSpectrum will pipeline the multiplier.  But when I place &
> route, I am only getting speeds of about 70 MHz (when the LUT max
> fanout is set to 5); however, when I do a similar design for the
> Stratix (multiplier implemented in logic elements, not dsp blocks),
> the design runs over 150 MHz.
> 
> The only difference is that I am using Quartus II's MegaWizard to
> generate the multiplier instead of Leonardo.  I find it hard to
> believe that there is that much difference between the FPGAs.  Has
> anybody else had better luck with the Virtex II (either with Synplify
> or Leonardo)?
> 
> Thanks,
> Ben Howe

Article: 45685
Subject: ICAP component in Virtex-II
From: stein.kjolstad@visitech.no (=?ISO-8859-1?Q?Stein_Kj=F8lstad?=)
Date: 1 Aug 2002 04:04:26 -0700
Links: << >>  << T >>  << A >>
Hi,

has anyone tried out the ICAP component in Virtex-II in a partial
reconfigurable application? The component is not well documented in
the Xilinx documentation. I would like any tips using the ICAP.

Thanks

Stein K

Article: 45686
Subject: Re: Pipelined Multiplier Implemented in Slices in Virtex II
From: Ray Andraka <ray@andraka.com>
Date: Thu, 01 Aug 2002 12:04:02 GMT
Links: << >>  << T >>  << A >>
It sounds like Leo is producing the correct construction then.  Floorplanning will get it to just about
200 MHz in the -4.  Unfortunately, that's about all you'll get out of the carry chain logic in V-2.  If
the numbers offered for Stratix turn out to be true, I think it may be faster than the V-2 for arithmetic.

> Ben,
>
> For Leonardo to fully pipeline the multiplier you need to add
> registers on the output for every internal stage. Leonardo will move
> the registers into the internal logic. This is explained in the
> Leonardo Users Manual.
>
> For a 14x10 you should need 4 registers; one for the 14 by 2 input
> stages,
> and three for the adder tree.
> Extra registers on the inputs will speed things up a bit too.
>
> Make sure you set the variable 'virtex2_multipliers' to false, so
> Leonardo doesn't use embedded multipliers.
>
> Leonardo's results should run at about 180 Mhz in a V2-4, not
> floorplanned.
> Alternatively, you could build a smaller and faster multiplier from
> primitives.
>
> --
> Ed
>
> bmhowe@yahoo.com (Ben Howe) wrote in message news:<df26a773.0207301042.1a6ae128@posting.google.com>...
> > I am trying to implement a 14x10 multiplier into slices in the Virtex
> > II (not the dedicated multipliers) using LeonardoSpectrum and Xilinx
> > ISE 4.1i.  I have added a register after the multiply so that
> > LeonardoSpectrum will pipeline the multiplier.  But when I place &
> > route, I am only getting speeds of about 70 MHz (when the LUT max
> > fanout is set to 5); however, when I do a similar design for the
> > Stratix (multiplier implemented in logic elements, not dsp blocks),
> > the design runs over 150 MHz.
> >
> > The only difference is that I am using Quartus II's MegaWizard to
> > generate the multiplier instead of Leonardo.  I find it hard to
> > believe that there is that much difference between the FPGAs.  Has
> > anybody else had better luck with the Virtex II (either with Synplify
> > or Leonardo)?
> >
> > Thanks,
> > Ben Howe

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 45687
Subject: Re: VirtexE : OrCAD capture part symbol
From: Greg Deuerling <egads@fnal.gov>
Date: Thu, 1 Aug 2002 07:58:16 -0500
Links: << >>  << T >>  << A >>
In article <ukhcvlspieo1e4@corp.supernews.com>, austin@dark99room.com says...
> This is not meant as a slight at all...but...it simply amazes me that this
> EXACT same question is asked ALL the time here, and only for OrCAD....  Is
> it that OrCAD users don't know how to create their own symbols???  What
> gives with this?

I always wander this myself.  I'm an OrCAD user, but I always make my
own symbols.  I made a 896 pin VertexII symbol in less than two hours
just a few months ago.  Its not that hard.  It takes some time and
some thought, but you get what you want.  I've also come to distrust
any symbol I get from someone else, I've been burned too many times
by trusting that the symbol/footprint is correct...

In short, take the time, do it your self !!!

-- 
                                                                     gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
=          Greg Deuerling, Fermi National Accelerator Laboratory          =
= P.O.Box 500 MS368  Batavia, IL 60510  (630)840-4629, FAX  (630)840-5406 =
=                  Electronic Systems Engineering Group                   =
=            Work: egads@fnal.gov       Personal: gad@elnet.com           =
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=

Article: 45688
Subject: Re: Pipelined Multiplier Implemented in Slices in Virtex II
From: "Wolfgang Loewer" <wolfgang.loewer@elca.de>
Date: Thu, 1 Aug 2002 15:37:10 +0200
Links: << >>  << T >>  << A >>
Ben,

a 14x10 LPM multiplier with 4 pipeline stages, registers on the
inputs/outputs and implemented with logic elements (not DSP block) in a
Stratix -5 devices runs at 358 MHz. This is a push button result, without
timing constraints or floorplanning. I think it is not uncommon that
instantiating optimized library functions can give better performance than
functions, inferred from RTL code.

Regards
Wolfgang
http://www.elca.de

"Ben Howe" <bmhowe@yahoo.com> schrieb im Newsbeitrag
news:df26a773.0207301042.1a6ae128@posting.google.com...
> I am trying to implement a 14x10 multiplier into slices in the Virtex
> II (not the dedicated multipliers) using LeonardoSpectrum and Xilinx
> ISE 4.1i.  I have added a register after the multiply so that
> LeonardoSpectrum will pipeline the multiplier.  But when I place &
> route, I am only getting speeds of about 70 MHz (when the LUT max
> fanout is set to 5); however, when I do a similar design for the
> Stratix (multiplier implemented in logic elements, not dsp blocks),
> the design runs over 150 MHz.
>
> The only difference is that I am using Quartus II's MegaWizard to
> generate the multiplier instead of Leonardo.  I find it hard to
> believe that there is that much difference between the FPGAs.  Has
> anybody else had better luck with the Virtex II (either with Synplify
> or Leonardo)?
>
> Thanks,
> Ben Howe



Article: 45689
Subject: Re: timing got worse?
From: hamish@cloud.net.au
Date: 01 Aug 2002 14:13:37 GMT
Links: << >>  << T >>  << A >>
Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote:
> On Mon, 29 Jul 2002 08:46:25 GMT, William Lenihan
> <lenihan3we@earthlink.net> wrote:
>>Is there some trick or switch to make 4.1i get at least as good,
>>preferably better, timing than 3.1i?
> 
> Yes, upgrade to 4.2i.

Also, if you weren't tracking service packs and speed file updates on
3.x, some of the slow down is a fact of life and may require significant
design changes, manual placement etc to work around.


Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 45690
Subject: Re: Who can compare the synthesis tools for me ?
From: kayrock66@yahoo.com (Jay)
Date: 1 Aug 2002 08:32:52 -0700
Links: << >>  << T >>  << A >>
If you know that eventually your design is going to be an ASIC, you
might consider just using the Synopsys option and save untangling the
last minute differences between the tools.  Also, if your company
already owns Synopsys Design Compiler for asic design, you can use
this along with the Xilinx technology libraries and do sythesis albiet
with non optimal circuit speeds and area.

Regards

Daryl <caoqh@engineer.com.cn> wrote in message news:<3d45ff34@shknews01>...
> Synopsys FPGA Compiler II
> Synplicity SynplifyPro
> Leonardo

Article: 45691
Subject: Safe design speed
From: "Peter Baltazarovic" <baltazarovic@ncode.sk>
Date: Thu, 1 Aug 2002 18:27:52 +0200
Links: << >>  << T >>  << A >>
Hello to everybody,

    I would like to know that if I want my design to be run at say 100 MHz,
for what speed should it be synthesized to be safe, stable and workung? I
mean 1%, 2% above 100 MHz?

Thanx for answer.

Peter



Article: 45692
Subject: FPGA needed
From: "Rafael Antunes Nobrega" <rafael@cbpf.br>
Date: Thu, 1 Aug 2002 19:14:43 +0200
Links: << >>  << T >>  << A >>
Hi,
I am at cern right now, working in a LHCb project and I had a problem with
my FPGA. It is not working properly.
I am waiting for new ones but it will take some time to arrive. If someone
can help me lending me one would be nice. I would raplace it as soon as the
FPGAs asked arrive. (main info XILINX CX4010 PC84)
Regards

--
Rafael
=====================================
Rafael Antunes Nobrega
Brazilian Center for Research in Physics (CBPF)
phone (at cern): 767 5874
E-mails:  rafael@cbpf.br
              rafael.nobrega@cern.ch
=====================================




Article: 45693
Subject: Xilinx ISE 4.2: UCF file name
From: Jee <Jee@hotmail.com>
Date: Thu, 01 Aug 2002 12:30:17 -0600
Links: << >>  << T >>  << A >>
Hi,
    I am using Xilinx ISE 4.2, I just found that it seemed that I have
to name the UCF file same as my top level entity name. Forexample, if my
top level entity is mysys, then ISE only look for mysys.ucf, and I can
not find where to tell ISE my UCF file name.
    IS this restriction true?

Thanks,



Article: 45694
Subject: Re: Xilinx ISE 4.2: UCF file name
From: Alan Raphael <alraphael@yahoo.com>
Date: Thu, 01 Aug 2002 15:00:01 -0400
Links: << >>  << T >>  << A >>
I use the same software and do not have the restriction you are talking 
about (my .ucf does have a different name).  Just make sure you specify 
it on the "properties" menu for Implement Design under the Translate 
Properties tab.  There is a property name Implementation User 
Constraints File that you can enter or search for the value of.  I 
assume if you leave it blank, it will look for a .ucf with the same name 
as your top level entity.

Jee wrote:

> Hi,
>     I am using Xilinx ISE 4.2, I just found that it seemed that I have
> to name the UCF file same as my top level entity name. Forexample, if my
> top level entity is mysys, then ISE only look for mysys.ucf, and I can
> not find where to tell ISE my UCF file name.
>     IS this restriction true?
> 
> Thanks,
> 
> 
> 


Article: 45695
Subject: Re: Safe design speed
From: "Kevin Neilson" <kevin-neilson@removethistextattbi.com>
Date: Thu, 01 Aug 2002 19:03:11 GMT
Links: << >>  << T >>  << A >>
100MHz.

Worst-case margins are already built into the timing models.

"Peter Baltazarovic" <baltazarovic@ncode.sk> wrote in message
news:aibni6$i3j$1@virtual.nextra.sk...
> Hello to everybody,
>
>     I would like to know that if I want my design to be run at say 100
MHz,
> for what speed should it be synthesized to be safe, stable and workung? I
> mean 1%, 2% above 100 MHz?
>
> Thanx for answer.
>
> Peter
>
>



Article: 45696
(removed)


Article: 45697
Subject: Looking for VHDL clock generator with jitter control ?
From: yanick_viens@hotmail.com (Yanick)
Date: 1 Aug 2002 12:19:22 -0700
Links: << >>  << T >>  << A >>
Hi,

I am looking for VHDL code that generates a clock output with jitter.
I need to be able to constraint the jitter throughout the frequency
spectrum.

Regards,

Yanick

Article: 45698
Subject: Pricing on Virtex 2 pro XC2VP4?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Thu, 1 Aug 2002 19:21:49 +0000 (UTC)
Links: << >>  << T >>  << A >>
Does anyone know what the ballpark prices for the XC2VP4 part is today
in small (~10) and large (~25,000) quantity?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 45699
Subject: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
From: "M. Randelzhofer" <mrandelzhofer@uumail.de>
Date: Thu, 1 Aug 2002 22:43:26 +0200
Links: << >>  << T >>  << A >>
First check in the fitterreport (projectname.rpt) if the related outputs
have a .TRST productterm like
"signal>".TRST = /signaloe

If there is none, your synthesistool doesn't understand you.

If there is one, and you disable it, maybe there is an error in the new
xilinx-sw. Please use the latest version, since the no buskeeper option is
only implemented in the last versions.

You can check the buskeepers with a 1 kohm resistor to Gnd or 3v3. The pins
(with output enable disabled) should follow the applied levels.

In the 95xx maindatasheet is a description of the buskeeper function. Only
buskeepers or pullup resistors are possible on these pld outputs. You should
ask Xilinx, if real National Semiconductor invented tristate function is
availlable.

MIKE







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