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excluding the net going into the carry since that is subject to routing:
VIrtex2-4:
Topcyf 0.769
Tbyp 0.106 * (N-2/2)
Tciny 1.446
net (fanout=1) 0.001
Tdyck 0.370
for a 16 bit carry chain, that is 3.328 ns plus the routing from the previous flip-flop
VirtexE-7:
Topcyf 0.839
Tbyp 0.133 * (N-2)/2
Tcckx 1.138
for 16 bits, that is 2.908 ns plus routing into the carry chain,
The routing delays into the carry chain are dependent on fanout, layout and routing solution. Both appear to be
in the same ballpark at about 1.5ns for a flip-flop in an adjacent CLB. If anything, the virtexE-7 is slightlye
faster here too based on a sample of a few worst case paths in a small sample of designs.
It looks like the main culprit is the excess delay getting off the carry chain.
Rick Filipkiewicz wrote:
> Ray,
>
> Do you have any quantitative idea of the in-the-fabric multiplier slow-down caused by the slower V-2 carry
> chain logic ? i.e. if it were as fast as the V-E what speed would you get ? [I think the V-2 -4 speed grade is
> supposed to be ~equivalent to the V-E -7].
>
> I strikes me that the problem may be the move in the V-2 to "fully buffered" routing which IIRC was designed
> so that the ``push the big green button'' merchants could get reasonable results without all that messing
> about with Floorplanning and RPMs.
>
> IMHO Xilinx really should do something about this otherwise they're in danger of losing one of their major
> historic advantages over Brand-A parts.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45801
Hello,
I'm starting to learn Verilog and I've faced a problem that I would be so
happy if anyone can help me.
I've difficulty translating this part of the code (from my older VHDL
designs) to verilog. The difficulty arises when I want to mix signed and
unsigned signals in a single expression:
Regards
Arash
--- from som old real-world code...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity rain is
port (
i : in unsigned(13 downto 0);
o : out unsigned(14 downto 0);
clock : in std_logic
);
end entity;
architecture one of rain is
type word_array is array(8 downto 1) of signed(17 downto 0);
signal z : word_array;
begin
process(clock)
variable ii : signed(17 downto 0);
variable oo : signed(17 downto 0);
begin
if rising_edge(clock) then
--FIR filter section
ii := signed("0000" & i);
z(8) <= - ii;
z(7) <= z(8) - ii;
z(6) <= z(7) - ii;
z(5) <= z(6) + ii;
z(4) <= z(5) + (ii sll 2);
z(3) <= z(4) + ii;
z(2) <= z(3) - ii;
z(1) <= z(2) - ii;
oo := z(1) - ii;
--Rectifier sectoin
if oo(17) = '1' then
o <= (others => '0');
else
o <= unsigned(oo(16 downto 2));
end if;
end if;
end process;
end one;
Article: 45802
Hi,
I am trying to reprogram the cpld on the xsv (300) board so as to
include a control signal from the parallel port to the FPGA. I am
trying to use the control bit c2 from the parallel port for this
purpose. But whatever i try, this control bit cannot be detected
beyond the cpld. For those of you who have seen the program for
generation of "dwnldpar.svf", this is the only line of code i added to
the existing code:
V_c <= ppc(2); -- had defined V_c as an o/p earlier.
I assigned V_c to port 30 (to be connected to port 169 of the fpga).
I cannot figure out how to proceed beyond this.
If this is not possible, is it possible to do handshaking in spite of
using all the 8 data lines for data transfer???
{ would i be right in assuming that the line c2 from the parallel port
to the cpld corresponds to the bit2 of the control register from the
pc side? }
Thanx in advance for the help!!
Shibu
Article: 45803
DLL minimum input clock is 25MHz, so his 20 MHz clock is too low to reliably
use the DLL.
Manfred Kraus wrote:
> > The burst clock frequencies are nominally 20 MHz, and the available
> > 'official' clock is 20 MHz, so there are no obvious resynchronization
> > tricks available.
>
> Why dont you produce a higher system clock "SYSCLK" out of your official
> clock ?
> The SPARTAN-II CLKDLL can do it.
> Then you could sample the 20 input clocks and input data using "SYSCLK".
> If you detect a rising input clock, you store the sampled data.
> This works only if the data is valid +/- Periodlength(SYSCLOCK) relative
> to the data's clock.
>
> -Manfred
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45804--------------CD07D2AF1EFEA6B3B82F81C1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit John, Times are tough. Xilinx did not have layoffs (oops, not pc), or have a 'RIF' as all other silicon companies did. We tightened our belts, stuck to what we do best, and continued to execute. Recently, we realized we have an opportunity to hire the absolute best engineers that had to be let go by their companies who were unable to weather the downturn. The terms and conditions are ours to make: since no one else is hiring (for ASIC, ASSP, or FPGA), it matters little if we do not offer relocation as a benefit. We have many other benefits that are more important. It is up to the candidate to decide what the trade-offs are, and if they make sense for them. As for Peter, and myself, no one ever offered us a relocation bonus. In the "old days" (and Peter is such a distinguished gentleman I would not offer to state when that was) for me, I was told that if I wanted the job, I could show up and interview for it. I know, we walked uphill in the snow to and from school, but hey, if you have never experienced tough times, you have nothing to provide you with a reference. As for discrimination, that is unfair and scurrilous to suggest: we hire the best, end of statement. I have engineers in their 60's working for me. I have engineers in their 20's working for me. I don't care how old they are, and neither do any other managers here. Peter worked in Sweden after he graduated from college in Germany. Austin John Jakson wrote: > I saw that Xilinx was hiring for VLSI guys with some substantial > experience, not just Verilog coders, but transistor level, HSpice, > layout, the works etc. > > I just happen to fit the bill and being an FPGA nut as well, but I am > out of state & MA based. > > As I was just about to expect a pre screen call, I was told that I > would not be interviewed unless I waived the benefit of a relocation > package as the budget is really tight. Of course I was working with a > head hunter so it must be even more really tight. > > I was somewhat dumbstruck, flabbergasted, and somewhat pissed off. > > This would seem to be a blatant form of either age or distance related > discrimination as I believe that many older engineers will have left > the valley. But Si valley is where the action is as any job search > will show so I was willing to go back even if the cost of living was > much much higher than MA, and salary likely much lower and now > apparently I have to buy the job. > > Is this true Peter, Austin, is it common that relocation is gone in > the valley. > > I am sure that Peter didn't just walk from Denmark? to SJ to start > work for what I thought was a remarkable company. > > John Jakson --------------CD07D2AF1EFEA6B3B82F81C1 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit John, Times are tough. Xilinx did not have layoffs (oops, not pc), or have a 'RIF' as all other silicon companies did. We tightened our belts, stuck to what we do best, and continued to execute. Recently, we realized we have an opportunity to hire the absolute best engineers that had to be let go by their companies who were unable to weather the downturn. The terms and conditions are ours to make: since no one else is hiring (for ASIC, ASSP, or FPGA), it matters little if we do not offer relocation as a benefit. We have many other benefits that are more important. It is up to the candidate to decide what the trade-offs are, and if they make sense for them. <br> <br> As for Peter, and myself, no one ever offered us a relocation bonus. In the "old days" (and Peter is such a distinguished gentleman I would not offer to state when that was) for me, I was told that if I wanted the job, I could show up and interview for it. I know, we walked uphill in the snow to and from school, but hey, if you have never experienced tough times, you have nothing to provide you with a reference. As for discrimination, that is unfair and scurrilous to suggest: <b>we hire the best</b>, end of statement. I have engineers in their 60's working for me. I have engineers in their 20's working for me. I don't care how old they are, and neither do any other managers here. Peter worked in Sweden after he graduated from college in Germany. Austin John Jakson wrote: <blockquote TYPE=CITE>I saw that Xilinx was hiring for VLSI guys with some substantial <br>experience, not just Verilog coders, but transistor level, HSpice, <br>layout, the works etc. I just happen to fit the bill and being an FPGA nut as well, but I am <br>out of state & MA based. As I was just about to expect a pre screen call, I was told that I <br>would not be interviewed unless I waived the benefit of a relocation <br>package as the budget is really tight. Of course I was working with a <br>head hunter so it must be even more really tight. I was somewhat dumbstruck, flabbergasted, and somewhat pissed off. This would seem to be a blatant form of either age or distance related <br>discrimination as I believe that many older engineers will have left <br>the valley. But Si valley is where the action is as any job search <br>will show so I was willing to go back even if the cost of living was <br>much much higher than MA, and salary likely much lower and now <br>apparently I have to buy the job. Is this true Peter, Austin, is it common that relocation is gone in <br>the valley. I am sure that Peter didn't just walk from Denmark? to SJ to start <br>work for what I thought was a remarkable company. John Jakson</blockquote> </html> --------------CD07D2AF1EFEA6B3B82F81C1--Article: 45805
Hi, I have one more question. In my architecture, the values of the signals change for every time step , so the text file which i was talking about would contain signals for every step . If i had to synthesize according to you, will the synthesizer be able to get a ROM so that it would have different signals for different time steps in accordance with the text file. Thanks, Ram. rxv20@po.cwru.edu (Ramakrishnan) wrote in message news:<15cf85fc.0208051905.1c936afd@posting.google.com>... > Hi, > I got your idea, but i was wondering whether it would be possible > to view the data of the memories in my architecture , without > explictly making them write on the display. > > Thanks, > > Ram. > > "Holger Kleinegraeber" <nul@nul.com> wrote in message news:<aili21$14q134$1@ID-69700.news.dfncis.de>... > > "Ramakrishnan" wrote > > > > > that , " how would i be able to download or include the > > > text file somehow in my program > > > > Which program? It's a hardware description. > > You can define a constant in your package. An array of integer which holds > > your values, or a std_logic_vector which holds your data in the form of > > zeros and ones. > > Then the syntheziser extracts a rom, which holds your data. > > > > Greetings, > > HolgerArticle: 45806
Everything I have heard indicates that jobs are fairly hard to come by in
silicon valley too. It is certainly an employer's market right now. If
you don't like the terms, then bag the interview and move on. With the
downturn, employers are in a position to pick and choose to get the best
talent at the best prices. The fact of the matter is that a relocation
package costs money, so it is a consideration in the hiring decision.
BTW, Peter was in silicon valley long before he went to Xilinx.
John Jakson wrote:
> I saw that Xilinx was hiring for VLSI guys with some substantial
> experience, not just Verilog coders, but transistor level, HSpice,
> layout, the works etc.
>
> I just happen to fit the bill and being an FPGA nut as well, but I am
> out of state & MA based.
>
> As I was just about to expect a pre screen call, I was told that I
> would not be interviewed unless I waived the benefit of a relocation
> package as the budget is really tight. Of course I was working with a
> head hunter so it must be even more really tight.
>
> I was somewhat dumbstruck, flabbergasted, and somewhat pissed off.
>
> This would seem to be a blatant form of either age or distance related
> discrimination as I believe that many older engineers will have left
> the valley. But Si valley is where the action is as any job search
> will show so I was willing to go back even if the cost of living was
> much much higher than MA, and salary likely much lower and now
> apparently I have to buy the job.
>
> Is this true Peter, Austin, is it common that relocation is gone in
> the valley.
>
> I am sure that Peter didn't just walk from Denmark? to SJ to start
> work for what I thought was a remarkable company.
>
> John Jakson
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45807Hi, Yes, I do get a lot of glitching between clock and signals do not change exactly at the clock transitions either. Thanks a lot for all the help. bye, Prashant "Xanatos" <fpsbb98@yahoo.com> wrote in message news:<61x39.282087$WJf1.50680@news01.bloor.is.net.cable.rogers.com>... > Yup, it is what you thought (a gate level sim). > > As for your "Quartus" way, I assume the sdo file comes into play > automatically. You should be able to tell by looking at the transitions in > the waveform - If they do not all change on clock edges (and you see lots of > glitches between clocks), then the sdo file has been used during the Quartus > sim. > > Cheers, > Xanatos > > "Prashant" <prashantj@usa.net> wrote in message > news:ea62e09.0208050712.17e721d5@posting.google.com... > > Hi, > > I have been simulating the gate level netlists the modelsim way, just > > as you suggest. But I wanted to confirm if the Quartus approach was > > what I thought. > > > > Also, I understand that with modelsim you should use the .sdo file. > > But is this file taken into consideration when working the Quartus way > > ? > > > > Thanks, > > Prashant > > > > > > "Xanatos" <fpsbb98@yahoo.com> wrote in message > news:<S6k39.278432$WJf1.96674@news01.bloor.is.net.cable.rogers.com>... > > > Yes. > > > > > > You can (in the EDA Tools section) set up a simulator specific output > > > simulation file, which is a gate level netlist as well. I've used that > quite > > > a bit (with Modelsim -> creates a vo file and sdo timing file), and > seems to > > > work fine. > > > > > > Cheers, > > > Xanatos > > > > > > "Prashant" <prashantj@usa.net> wrote in message > > > news:ea62e09.0208041608.7e947420@posting.google.com... > > > > Hi, > > > > If I followed the Quartus II flow of compiling a design (includes > > > > synthesis, fitting of the circuit in an FPGA device and timing > > > > analysis) and then simulate the design in Quartus using its own > > > > simulator, would that be considered equal to gate level simulation ? > > > > > > > > Thanks, > > > > PrashantArticle: 45808
"Ramakrishnan" schrieb:
> Hi,
> I have one more question. In my architecture, the values of the
> signals change for every time step , so the text file which i was
> talking about would contain signals for every step .
>
> If i had to synthesize according to you, will the synthesizer be able
> to get a ROM so that it would have different signals for different
> time steps in accordance with the text file.
I see no problem for the syntheziser dealing with the following two
dimensional array:
package ROM is
type which_time_array is array ( 0 to 63) of integer;
type which_signal_array is array (0 to 15) of which_time_array;
constant ROM : which_signal_array;
end package;
package body ROM is
constant rom(0)(0) : integer : 6;
constant rom(0)(1) : integer : 43;
...
end package body rom;
Now you can access your values:
actual_value <= rom(actual_time)(which_signal);
or (I'm not sure)
actual_value <= ROM(which_signal)(actual_time);
I haven't testet it, but I believe it would work.
HTH,
Holger
Article: 45809It's the "Law of Supply and Demand". The current supply of FPGA experts exceeds the demand in the Silicon Valley. (Ask me how I know...) You are "geographically undesireable". Sorry, it's not any form of discrimination. On 6 Aug 2002 04:35:51 -0700, johnjakson@earthlink.net (John Jakson) wrote: >I saw that Xilinx was hiring for VLSI guys with some substantial >experience, not just Verilog coders, but transistor level, HSpice, >layout, the works etc. > >I just happen to fit the bill and being an FPGA nut as well, but I am >out of state & MA based. > >As I was just about to expect a pre screen call, I was told that I >would not be interviewed unless I waived the benefit of a relocation >package as the budget is really tight. Of course I was working with a >head hunter so it must be even more really tight. > >I was somewhat dumbstruck, flabbergasted, and somewhat pissed off. > >This would seem to be a blatant form of either age or distance related >discrimination as I believe that many older engineers will have left >the valley. But Si valley is where the action is as any job search >will show so I was willing to go back even if the cost of living was >much much higher than MA, and salary likely much lower and now >apparently I have to buy the job. > >Is this true Peter, Austin, is it common that relocation is gone in >the valley. > >I am sure that Peter didn't just walk from Denmark? to SJ to start >work for what I thought was a remarkable company. > >John JaksonArticle: 45810
XILINX has given limited 3.3v suppport. Some text from them is included below. Doen't give you a warm feeling however. Yes, limited support for 3.3V I/O is available in Virtex-II Pro devices. (3.3V I/O is available on Banks 0, 1, 2, and 3 only.) For more information, please see the Virtex-II Pro Handbook under Single-Ended Select I/O Resources -> 3.3V I/O Support: http://support.xilinx.com/publications/products/v2pro/handbook/index.htm Additionally, ONLY LVDCI_33 I/O standards may be used in Virtex-II Pro to drive or receive 3.3V I/Os. To access these, set the IOSTANDARD attribute to "LVDCI_33". (Please see the Virtex-II Pro Handbook -> Single Ended Select I/O Resources for more information.) The DC and Switching Characteristics table (page 1, table 1) describes the limitations and implies the absolute overshoot and undershoot of 300 mV: http://support.xilinx.com/publications/products/v2pro/ds_pdf/ds083-3.pdf NOTE: 1. LVDCI_33 inputs are exactly the same as LVCMOS33 inputs. No VRN/VRP is required if the bank is used for LVDCI input only. (Please see (Xilinx Answer 14128) for more information.) To match the impedance of the transmission line, add a source resistor near the drivers for LVCMOS and LVTTL devices on the board that are driving FPGA LVDCI inputs. 2. If LVDCI outputs are used, the VRN/VRP must be connected to appropriate resistors that match the impedance of the transmission line. 3. For more information on DCI, please see Chapter 2 of the Virtex-II Pro Handbook, "Digital Controlled Impedance (DCI)": http://support.xilinx.com/publications/products/v2pro/handbook/index.htm 4. The LVTTL I/O standard may interface with Virtex-II I/O, provided the undershoot/overshoot and the VIH/VOH specifications are met. 5. JTAG pins are 3.3V-tolerant, even though VCCAUX (VCC powering JTAG pins) is 2.5V. Solution 2: The supported PCI I/O standards are: PCI33_3 PCI66_3 For further information on the PCI interface, please see the following Xilinx application notes: (Xilinx XAPP646) "Connecting Virtex-II Devices to a 3.3V/5V PCI Bus" (Xilinx XAPP653) "Virtex-II Pro 3.3V PCI Reference Design" Both application notes must be used with the supported PCI I/O standard (PCI33_3 or PCI66_3). ----- Original Message ----- From: "Laurent Gauch" <laurent.gauch@amontec.com> Newsgroups: comp.arch.fpga Sent: Tuesday, July 30, 2002 8:37 AM Subject: VIRTEX-II pro -> LVTTL 3.3 > Hi all, > > Are the Virtex-II pro IOs LVTTL 3.3V tolerant or not? > > Laurent > "Laurent Gauch" <laurent.gauch@amontec.com> wrote in message news:3D468888.8000607@amontec.com... > Hi all, > > Are the Virtex-II pro IOs LVTTL 3.3V tolerant or not? > > Laurent >Article: 45811
I am interested in hearing what type of connectors and cabling people are using on thier boards for the differential high speed serial standards available with the new Virtex 2. I saw some interesting D connectors which 3M had produced for differential line. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com PMB 327 8630-M Guilford Road richard@associatedpro.com Columbia, Maryland 21046 Phone: 410-510-1274 or 301-498-9402 Fax: 410-510-1274 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 45812
Some customer's have been complaining about not being able to target old FPGA chips (400 sereis etc) with the newer software. Does anyone have any information on this. Has XILINX offered a synthesis and routing solution that is still available for the 4000, and 5000 series chips. I haven't actually verified their concerns and was wondering if anyone has encountered the same problems. -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com PMB 327 8630-M Guilford Road richard@associatedpro.com Columbia, Maryland 21046 Phone: 410-510-1274 or 301-498-9402 Fax: 410-510-1274 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 45813
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D4FE14B.D56334C2@xilinx.com>... > John, > > Times are tough. Xilinx did not have layoffs (oops, not pc), or have a > 'RIF' as all other silicon companies did. We tightened our belts, stuck > to what we do best, and continued to execute. > > Recently, we realized we have an opportunity to hire the absolute best > engineers that had to be let go by their companies who were unable to > weather the downturn. > > The terms and conditions are ours to make: since no one else is hiring > (for ASIC, ASSP, or FPGA), it matters little if we do not offer relocation > as a benefit. We have many other benefits that are more important. It is > up to the candidate to decide what the trade-offs are, and if they make > sense for them. > > > > As for Peter, and myself, no one ever offered us a relocation bonus. In > the "old days" (and Peter is such a distinguished gentleman I would not > offer to state when that was) for me, I was told that if I wanted the job, > I could show up and interview for it. > > I know, we walked uphill in the snow to and from school, but hey, if you > have never experienced tough times, you have nothing to provide you with a > reference. > > As for discrimination, that is unfair and scurrilous to suggest: we hire > the best, end of statement. I have engineers in their 60's working for > me. I have engineers in their 20's working for me. I don't care how old > they are, and neither do any other managers here. > > Peter worked in Sweden after he graduated from college in Germany. > > Austin > Hi Austin Thanks for your response, I apologize for implying anything untoward. I very glad to hear that more senior engineers are working hard at Xilinx. Anyway I was really unaware that reloc packages were so severely limited by the industry at large today, as it has always been my fortune to have been offered this in prior times for out of state changes even when I think the economy was far worse 84 etc. I will bear this in mind next time I talk to folks. Perhaps the head hunter should have been warned too, and I couldn't find this info on your job site or on any of the positions in B & W. RegardsArticle: 45815
Shibu wrote:
> Hi,
> I am trying to reprogram the cpld on the xsv (300) board so as to
> include a control signal from the parallel port to the FPGA. I am
> trying to use the control bit c2 from the parallel port for this
> purpose. But whatever i try, this control bit cannot be detected
> beyond the cpld. For those of you who have seen the program for
> generation of "dwnldpar.svf", this is the only line of code i added to
> the existing code:
>
> V_c <= ppc(2); -- had defined V_c as an o/p earlier.
> I assigned V_c to port 30 (to be connected to port 169 of the fpga).
> I cannot figure out how to proceed beyond this.
> If this is not possible, is it possible to do handshaking in spite of
> using all the 8 data lines for data transfer???
>
> { would i be right in assuming that the line c2 from the parallel port
> to the cpld corresponds to the bit2 of the control register from the
> pc side? }
>
> Thanx in advance for the help!!
> Shibu
This question is a bit too specific to XSV Boards for comp.arch.fpga. You
might get better response by subscribing to the XS Board users group and
ask there. That said, here are some questions:
1) Are you sure the P&R actually placed your input and output on the
appropriate pins (check the CPLD .RPT file).
2) C2 should be controlled by bit 2 of the parallel port control
register. Have you toggled that bit and actually monitored the control
pin on the parallel port to see if you have changed it?
3) As a check, have you tried toggling bit 0 or bit 1 of the control
register and monitoring the cclk and /program pins of the FPGA to see if
they change? (dwnldpar.vhd should already be doing this.)
3) What version of XSTOOLS are you using?
4) Are you sure the CPLD is being reprogrammed? (Make sure the shunt is
on jumper J23 and on pins 1-2 of jumpers J29,J30,J31.)
--
|| Dr. Dave Van den Bout XESS Corp. (919) 303-2883 ||
|| devb@xess.com 2501-B Ten-Ten Road (800) 549-9377 ||
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Article: 45816"Mike Rosing" <rosing@neurophys.wisc.edu> schrieb im Newsbeitrag news:3D4A67D5.60006@neurophys.wisc.edu... > I finally got some VHDL to compile, but the synthesis uses CLB latches > instead of lut's. What I'm trying to do is hook 16 lut's together to > create a 16x16 bit matrix, and I want to eventually read out 1 row, > or 1 diagonal using the address lines to grab 1 bit from each lut. > (and this is in a Virtex-2 fpga). The easiest way to this goal. Instanciate distributed RAM, use a simple address mux to toggle between normal and "diagonal" address access and you are done. All other attemts to write a VHDL that will recognized by the compiler is just academical playaround. > memory access. I've been assuming I'd need to use primitives > to do this, but reading some threads and the help docs indicates > that's not the prefered way to do things. What is the right way Why not? You can only achieve good performance/density when you use the special features of the target IC. -- Regards FalkArticle: 45817
"Richard Schwarz" <Rick@associatedpro.com> schrieb im Newsbeitrag news:PGT39.8633$u7.690584@news.direcpc.com... > Some customer's have been complaining about not being able to target old > FPGA chips (400 sereis etc) with the newer software. Does anyone have any > information on this. Has XILINX offered a synthesis and routing solution > that is still available for the 4000, and 5000 series chips. I haven't > actually verified their concerns and was wondering if anyone has encountered > the same problems. Hmm, AFAIK the 4K is only supported by using FPGA-EXPRESS. But Iam not sure about the 4K series, I just know that Spartan(XL) is supported. But for this old stuff, Iam afraid they have to stick to the old Foundation software. -- Regard FalkArticle: 45818
According to the Xilinx website, for XC4000 series, the only
design flow currently supported is EDIF.
Since ISE 4.2 no longer comes with Synopsys FPGA Compiler II, and XST
doesn't support XC4000 series, the ISE 4.2 user will have to buy a
separate third party synthesis tool.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 45819Hi. Is there a way to define a variable / parameter in the xilinx ucf file ? I want to P&R to several design parameters. My clock frequency determine also my I/O setup requirement etc.. Thus I am looking for a way to easily switch from one ucf to another by changing 1 parameter at most. Is it possible ? ThankX, NAHUM.Article: 45820
See the Xilinx Virtex 2 handbook section "Using Look-Up Tables as Shift Registers (SRLUTs) at http://www.xilinx.com/products/virtex/handbook/ug002_ch2_srlut.pdf for some additional help.Article: 45821
Hello! I'm working on a PCI to local bus bridge (using the Xilinx IP). I need some recommendations on "best practices" (esp. if Verilog specific). Everything dealing with the PCI "side" is nicely synchronous to the PCI clock. However, there is no local bus clock. Every peripheral on the local bus is a slave to chip select, output enable, and write enable signals. A Xilinx reference bridge essentially synchronizes the local bus to the PCI clock. I could probably do this, except the PCI spec says the clock can be anywhere from 0-33Mhz, which means there are conditions at which my design would simply stop working. In addition, there would seem to be race conditions (i.e. my write_enable must be 30ns in order to guarantee catching one positive clock edge, but if it's slightly longer for some reason, I could potentially catch two) I can't use the Xilinx CORE asynchronous FIFO (it apparently requires several "do nothing" clock cycles in order to move data around. Since I have no "do nothing" clock cycles, this doesn't work). I'm currently doing things like: assign register_decode = CHIP_SELECT & (ADDR == REGISTER); assign register_write = register_decode & WRITE_ENABLE; assign register_read = register_decode & OUTPUT_ENABLE; always @(posedge register_write) ... The problem is, combinatorial clocks give the compiler a headache. In addition, I'm running into a timing problem (even in behavioral simulation with no delays) where the bus lines get there after the register_write edge. As a result, the above construct latches bad data. Augh! Help! What is the best method for arbitrating between a synchronous clock and asynchronous signals?Article: 45822
I put my original CUPL disk away for safekeeping and now it is really safe - from me, even. I have the Tutorial, PAL search and the 4.2 upgrade disks (4 of them - this is DOS based CUPL), but I can't run the upgrade without the serial number from my original. I can't seem to find DOS-based CUPL or any way around the S/N. Anyone know a fix, or a source for CUPL 4.2? My old 286 has my programmer on it (takes an ISA slot) and an old, old 540mb drive. I really, really don't want to go to Windows for CUPL - must I? Thanks for the help - BobArticle: 45823
Bob Woolley wrote: > > I put my original CUPL disk away for safekeeping and now it is really safe - > from me, even. I have the Tutorial, PAL search and the 4.2 upgrade disks (4 > of them - this is DOS based CUPL), but I can't run the upgrade without the > serial number from my original. I can't seem to find DOS-based CUPL or any > way around the S/N. > > Anyone know a fix, or a source for CUPL 4.2? My old 286 has my programmer on > it (takes an ISA slot) and an old, old 540mb drive. I really, really don't > want to go to Windows for CUPL - must I? > > Thanks for the help - Bob What devices do you need to target ? -jgArticle: 45824
Hello, I am not very familiar with fpgas, however, I wish to learn about using them to integrate with pc applications. I was wondering if there are any suggestions as to where to find source examples or at least explanations on integrating a programmed fpga to communicate with a pc and how to send it commands, retrieve data, etc. Would also appreciate any feedback on the cost of a good quality fpga at low volume(0-50). Thanks for reading. Newbie.
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