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Messages from 46850

Article: 46850
Subject: How to make Altera UPX board self bootable?
From: enliteneer@mindless.com (eric)
Date: 9 Sep 2002 22:35:52 -0700
Links: << >>  << T >>  << A >>
Im trying to make the Altera UPX board standalone, such
that I dont need to byteblast down the code to the FPGA everytime
I turn the power on.

Ive looked through the user manual, but I cant seem to find anything
that addresses this.  Specifically, Im just looking for things like:
what eeprom chip I need (presumably it goes in the EPC 
dip socket) and how to program that chip (.sof file)? Can I program
the chip on the UPX board itself, or do I need an external programmer?

Does the VHDL code have to change in any way if booting up from rom
instead of downloading?

Any suggestions are much appreciated!

Article: 46851
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 10 Sep 2002 17:53:06 +1200
Links: << >>  << T >>  << A >>
al wrote:
> 
> Does any one know of a 555 schematic or vhdl for xilinx or other clock
> circuit ?
> 
> Trying to minimise external components.There is very little space
> left on the board I'm using.
> Only got enough space for 2 8pin dil dipswitches ,4 leds, 7 transistors, 7
> resistors
> and 1 seven segment display.
> Need a clock
> 
> Max clock needed is 1MHz
> 
> I am a beginner, still using schematics.
> 
> All help greatly appreciated.
> 
> Alex

 555 is too large - look at the Single gate devices, ~74HC1G14 in SOT23.
Farnell have those. A single R and Single C, and you're done..

Or use a xtal module, 
or a 74HC1GU04 + XTAL + HC1G14 to square-up
           ^-- the U matters, == unbuffered

-jg

Article: 46852
Subject: Re: How to make Altera UPX board self bootable?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Tue, 10 Sep 2002 06:01:27 +0000 (UTC)
Links: << >>  << T >>  << A >>


"eric" <enliteneer@mindless.com> wrote in message
news:2b8a3423.0209092135.515a08ed@posting.google.com...
> Im trying to make the Altera UPX board standalone, such
> that I dont need to byteblast down the code to the FPGA everytime
> I turn the power on.
>
> Ive looked through the user manual, but I cant seem to find anything
> that addresses this.  Specifically, Im just looking for things like:
> what eeprom chip I need (presumably it goes in the EPC
> dip socket) and how to program that chip (.sof file)? Can I program
> the chip on the UPX board itself, or do I need an external programmer?

You can program the EPC chips with a ByteBlaster. I made a little adapter up
using a scrap of prototyping board with a socket for the chip.


>
> Does the VHDL code have to change in any way if booting up from rom
> instead of downloading?

I don't think so.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 46853
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Tue, 10 Sep 2002 06:05:11 +0000 (UTC)
Links: << >>  << T >>  << A >>

"al" <alxx.@..ihug..com..au> wrote in message
news:aljsht$pr$1@lust.ihug.co.nz...
> Does any one know of a 555 schematic or vhdl for xilinx or other clock
> circuit ?
>
> Trying to minimise external components.There is very little space
> left on the board I'm using.
> Only got enough space for 2 8pin dil dipswitches ,4 leds, 7 transistors, 7
> resistors
> and 1 seven segment display.
> Need a clock
>
> Max clock needed is 1MHz

Some of the Xilinx FPGAs (I know the Spartan has one) have a built-in
oscillator (used for configuration) that you can use. It's probably as
stable as a 555 or similar.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 46854
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: "al" <alxx.@..ihug..com..au>
Date: Tue, 10 Sep 2002 17:03:51 +1000
Links: << >>  << T >>  << A >>

"Leon Heller" <leon_heller@hotmail.com> wrote in message
news:alk22n$jja$1@helle.btinternet.com...
>
> "al" <alxx.@..ihug..com..au> wrote in message
> news:aljsht$pr$1@lust.ihug.co.nz...
> > Does any one know of a 555 schematic or vhdl for xilinx or other clock
> > circuit ?
> >
> > Trying to minimise external components.There is very little space
> > left on the board I'm using.
> > Only got enough space for 2 8pin dil dipswitches ,4 leds, 7 transistors,
7
> > resistors
> > and 1 seven segment display.
> > Need a clock
> >
> > Max clock needed is 1MHz
>
> Some of the Xilinx FPGAs (I know the Spartan has one) have a built-in
> oscillator (used for configuration) that you can use. It's probably as
> stable as a 555 or similar.
>
> Leon

Sorry should have said I'm using a 9572xl cpld. XC9572XL PC44

Also been suggested that I could use an input output  loop (positive
feedback loop)
input buffer + inv + output buffer + cap to  gnd + input buffer + inv +
output buffer.
Doing this would leave me with all pins to the cpld used.

Actual clock frequency isn't critical.Anything from 1 KHz to 1 MHz would be
acceptable.

The development board I'm using has a pic 16F628 on it
but I haven't got any spare pins(for linking on the board) to connect to it
for this project

For a photo of the board see www.alxx.net/1.jpeg   or
http://www.geocities.com/alxx9672/1.jpg
what appears in the pic as unused is full with a connector(simmbus right
angled 30 pin female) and
2 ic sockets(1 7 pin, 1 8 pin,  and the rest with socket strip pins).
Also that area is connected in colums and rows  1 by 3 pins.

I was trying to get everything on the board.
But would like to fit the finished design on a 2inch by 2 inch board
including power circuit.

With this design also going to add a seven seg led to see
what state the state machine is in for debugging.


Thank you.

Alex



Article: 46855
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: "Johann Glaser" <Johann.Glaser@gmx.at>
Date: Tue, 10 Sep 2002 09:56:43 +0200
Links: << >>  << T >>  << A >>
Hi!

> I was trying to get everything on the board. But would like to fit the
> finished design on a 2inch by 2 inch board including power circuit.

Perhaps you can replace the resistors, diodes and caps by SMD components.
They are very easy to solder by hand (and much faster). And they save a
huge amount of place. Another idea is to use the bottom of the PCB. With
SMD this is no problem.

Probably the 74' ICs can be replaced within the CPLD. At least you can use
SMD packages. There are SO packages (quite small) but TSSOP is even
smaller (but trickier to solder, if you do it by hand).

But all my ideas only work if you design your own PCB. Don't know if you
will do that. Despite that, they will work for factory production as well
as for hobbyists.

Bye
  Hansi

Article: 46856
Subject: Re: XCR3384XL availability
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 10 Sep 2002 09:27:50 +0100
Links: << >>  << T >>  << A >>


rickman wrote:

>
>
> Well, I can't argue with the facts!!!

Scientific/Engineering training can be a real PITA sometimes since most of
the rest of the world seems to manage that quite happily [cf. Stratix
!!500%!! performance increase in another thread].

Arguing with facts gives a pretty good definition of politics [or marketing].


Article: 46857
Subject: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
From: "Gregory C. Read" <readgc@xxxhotmail.com>
Date: Tue, 10 Sep 2002 10:43:28 GMT
Links: << >>  << T >>  << A >>
I have no trouble making my own symbols in OrCAD. I find it very straight
forward. I'd be happy to do it for others (for a fee of course).

--
Greg
readgc@xxxhotmail.com
(Remove the 'xxx' to send Email)


"Austin Franklin" <austin@da98rkroom.com> wrote in message
news:uno10te4kjhga5@corp.supernews.com...
>
> "BasePointer" <mfide@softhome.net> wrote in message
> news:ee78d89.-1@WebX.sUN8CHnE...
> > Hi,
> > I look for Orcad 9.2 Capture(Schematic) Library for
> XCS10XL-PC84(SpartanXL) and XC18V256PC20 PROM.
> >
> > Thanks
>
> I've said this before, and it isn't meant insultingly at all...but WHY is
it
> OrCAD users are the ones who are the only ones who ask for symbols?  I've
> never seen a ViewDraw user, or any other schematic capture package user
ask
> in this group for symbols.  S'up wit dat?  Most everyone, other than
> apparently OrCAD users, simply make the symbols.
>
> Austin
>
>
>



Article: 46858
Subject: Re: How to make Altera UPX board self bootable?
From: hardwire <nospam@nomail.com>
Date: Tue, 10 Sep 2002 03:48:25 -0700
Links: << >>  << T >>  << A >>
UPx board contians socket for 8-pin DIP package, means EPC1441PC8 or EPC1PC8 boot PROM. Both, EPC1448 and EPC1 are EPROM based. You are reqired to program the PROMs by using an appropriate external programmer. U cannot use Byteblaster, Masterblaster etc.

Article: 46859
Subject: Re: minimalist FPGA system
From: Silvio Lauckner <silvio.lauckner@inf-technik.tu-ilmenau.de>
Date: Tue, 10 Sep 2002 13:07:57 +0200
Links: << >>  << T >>  << A >>

--------------C60DE99D24C8DDAB6E53733D
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I just built up my own development board a couple years ago.
Have a look at:  www.inf-technik.tu-ilmenau.de/~lauckner/misc.html

Silvio






Article: 46860
Subject: PowerTheatre for FPGAs?
From: "Ulises Hernandez" <ulises@britain.agilent.com>
Date: Tue, 10 Sep 2002 12:25:37 +0100
Links: << >>  << T >>  << A >>
Hello,

I had a look to the Sequence product - PowerTheatre
(http://www.sequencedesign.com/2_solutions/2b_power_theater.html), Power
Analysis...for SoC. I tried the tool and it seems that you specify your RTL,
the technology using SoC libraries (like 1.0v 0.13u technology) and the VCD
(if you want to).  The tool looks good and you get individual results for
each RTL block, it includes a Power Reduction Wizard...
I was wondering if there are any FPGA libraries (Xilinx principally) you can
use with this tool, or a similar tool for FPGAs (Xilinx principally), I know
about XPower but seeing this PoweerTheater thing XPower doesn't look as
good, I can't tell about the results anyway.

Thank you for your help.

--
Ulises Hernandez
ECS Technology Limited
ulisesh@ecs-tech.com



Article: 46861
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Tue, 10 Sep 2002 11:37:33 +0000 (UTC)
Links: << >>  << T >>  << A >>

"al" <alxx.@..ihug..com..au> wrote in message
news:alk5hb$8bb$1@lust.ihug.co.nz...
>
> >
> > Some of the Xilinx FPGAs (I know the Spartan has one) have a built-in
> > oscillator (used for configuration) that you can use. It's probably as
> > stable as a 555 or similar.
> >
> > Leon
>
> Sorry should have said I'm using a 9572xl cpld. XC9572XL PC44
>
> Also been suggested that I could use an input output  loop (positive
> feedback loop)
> input buffer + inv + output buffer + cap to  gnd + input buffer + inv +
> output buffer.
> Doing this would leave me with all pins to the cpld used.

Yes, that will work. Peter Afke of Xilinx posted a msg about this some time
ago (try looking for it with Google groups). I tried his suggestion with an
Altera Flex FPGA and it worked OK.

Leon
--
Leon Heller, G1HSM
leon_heller@hotmail.com
http://www.geocities.com/leon_heller



Article: 46862
Subject: Re: Polyphase filtering...
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 10 Sep 2002 15:02:26 +0200
Links: << >>  << T >>  << A >>
Hi,

Thanks for the response... do you by any chance have any good references I
could have a look at... particularly using signals in quadrature and the
associated complex FFT after the filters...

Thanks

Adrian


> That is exactly what polyphase filtering is good for.  You can get by
> with less hardware.  But make sure you are not going to suffer from the
> rolloff at your filter edge.  The cutoff is not absolute and should be
> slightly below the decimated Nyquist rate to allow the transistion band
> to remove all artifacts before you reach the decimated Nyquist rate.
> The decimated Nyquist rate should be in the stop band rather than at the
> cutoff, or at least 1/2 way though the transistion band (which results
> in the same amount of "junk" but will make it slightly harder to further
> filter).
>
> _______
>        \ ____ cutoff (-6dB)
>         \
>          \
>           \   Transistion band
>            + ---  Put Nyquist rate no lower than here
>             \
>              \
>               \  Stop band
>                \________________
>
> Result after midtransistion band frequency folding
> The transition band above the Nyquist rate is folded into the
> same freqs as the transition band below the Nyquist rate
> _______
>        \
>         \
>          \
>           \
>            >
>           /
>          /
>         /
> _______/
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX



Article: 46863
Subject: Xilinx Parallell Cable IV and Wine
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Tue, 10 Sep 2002 13:26:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hallo,

has anybody used a Xilinx Parallell Cable IV with the Xilinx supplied
software with Wine?

There are success reports for the Type III cable, but the Type IV cable
seems to use IEEE1284 feature, which probably require a driver which probably
will make Wine stumble...

But the type III cable ( with published schematics versus propriatary
hardware for the type IV cable) is not specified for the 1.8 Volt signaling
used on the JTAG port of the coolrunner II...

Any ideas welcome
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 46864
Subject: Re: Xilinx Parallell Cable IV and Wine
From: Martin <>
Date: Tue, 10 Sep 2002 07:04:49 -0700
Links: << >>  << T >>  << A >>
Hi Uwe,

I can't comment on Wine and the Parallel Cable IV but I tried the Parallel Cable IIIfar outside its spec on a Coolrunner or Coolrunner-II board a couple of weeks ago. I started of at the normal supply voltage and went down gradually to about 1.5 Volts and it still worked.
As said this is not an official statement but it's definatly worth a try. Do you have the cable or do you have any placement students to build it? Just give it a try if it'll work with your configuration.

Martin

Article: 46865
Subject: Re: XCR3384XL availability
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Sep 2002 10:19:35 -0400
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> >  Just looking at the May 2002 info, of AT40K05AL, I see
> > - 7V ABS MAX pin rating
> ...
> > looks PC/104 friendly ? ... they are not 'new', but for 5V you need
> > 'old' :)
> 
> I'm not familiar with the fine print of PC/104.  I seem to remember
> that the hard problem for PCI is an 11 V spike.  That happens when
> a driver goes from low to high and the bus is unloaded and the
> reflection bounces off the other end and comes back so you get
> back the classic twice as much as you sent.  If you FCC is 5.5,
> then you get back 11.  (Even if your driver doesn't jump
> up to 5.5V output in order to provoke a horrible reflection, the one
> on the chip next to you might do it.)
> 
> Do PC/104 systems have the same problem?  If not, how do they
> avoid it?

The drivers on the ISA-PC/104 busses have much more relaxed timing and
so drive with much less strength.  The driver spec for PC/104 is 4 mA. 
So the reflections are not as prevalent.  Also, there is no backplane
unless a card is plugged in.  Notice that your worse case condition was
an unloaded bus.  There is no such thing in PC/104.  But then again,
back when PC/104 was put together, SI issues were dealt with when they
happened, not in advance.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 46866
Subject: Re: Polyphase filtering...
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Sep 2002 10:24:29 -0400
Links: << >>  << T >>  << A >>
No sorry.  Most of my references are walking around.  John Treichler has
written a book or two.  You can search a bit on the web.  But I have not
read it, but I can't imagine it is not good.  It also helps to work with
a bunch of other guy (or gals) who are learning the stuff too.  I
learned a lot from our group discussions.  


Noddy wrote:
> 
> Hi,
> 
> Thanks for the response... do you by any chance have any good references I
> could have a look at... particularly using signals in quadrature and the
> associated complex FFT after the filters...
> 
> Thanks
> 
> Adrian
> 
> > That is exactly what polyphase filtering is good for.  You can get by
> > with less hardware.  But make sure you are not going to suffer from the
> > rolloff at your filter edge.  The cutoff is not absolute and should be
> > slightly below the decimated Nyquist rate to allow the transistion band
> > to remove all artifacts before you reach the decimated Nyquist rate.
> > The decimated Nyquist rate should be in the stop band rather than at the
> > cutoff, or at least 1/2 way though the transistion band (which results
> > in the same amount of "junk" but will make it slightly harder to further
> > filter).
> >
> > _______
> >        \ ____ cutoff (-6dB)
> >         \
> >          \
> >           \   Transistion band
> >            + ---  Put Nyquist rate no lower than here
> >             \
> >              \
> >               \  Stop band
> >                \________________
> >
> > Result after midtransistion band frequency folding
> > The transition band above the Nyquist rate is folded into the
> > same freqs as the transition band below the Nyquist rate
> > _______
> >        \
> >         \
> >          \
> >           \
> >            >
> >           /
> >          /
> >         /
> > _______/
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design      URL http://www.arius.com
> > 4 King Ave                               301-682-7772 Voice
> > Frederick, MD 21701-3110                 301-682-7666 FAX

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 46867
Subject: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
From: Peter Wallace <pcw@mesanet.com>
Date: Tue, 10 Sep 2002 08:07:04 -0700
Links: << >>  << T >>  << A >>
Leon Heller wrote:
> "al" <alxx.@..ihug..com..au> wrote in message
> news:alk5hb$8bb$1@lust.ihug.co.nz...
> 
>>>Some of the Xilinx FPGAs (I know the Spartan has one) have a built-in
>>>oscillator (used for configuration) that you can use. It's probably as
>>>stable as a 555 or similar.
>>>
>>>Leon
>>
>>Sorry should have said I'm using a 9572xl cpld. XC9572XL PC44
>>
>>Also been suggested that I could use an input output  loop (positive
>>feedback loop)
>>input buffer + inv + output buffer + cap to  gnd + input buffer + inv +
>>output buffer.
>>Doing this would leave me with all pins to the cpld used.
> 
> 
> Yes, that will work. Peter Afke of Xilinx posted a msg about this some time
> ago (try looking for it with Google groups). I tried his suggestion with an
> Altera Flex FPGA and it worked OK.
> 
> Leon
> --
> Leon Heller, G1HSM
> leon_heller@hotmail.com
> http://www.geocities.com/leon_heller
> 
> 
	You can also make a ring oscillator in the CPLD and divide the clock 
frequency down internally. That way you dont waste any I/O pins (but you 
will need free cells for the ring oscillator and divider) I have done 
this in a 9572. You do have to convince the compiler not to minimize 
your ring oscilalator away (some Xilinx app note says how...)


Article: 46868
Subject: Re: XCR3384XL availability
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 10 Sep 2002 12:10:39 -0400
Links: << >>  << T >>  << A >>
Mikeandmax wrote:
> 
> OR - just perhaps evaluate Lattice ispMACH4384 - it is available in 1.8, 2.5
> and 3.3v versions - is also an extremely low current technology - Lattice went
> to an all CMOS gate structure in this family - no sense amplifiers to gobble up
> current.
> 
> oops, affiliation and all that stuff -
> 
> Michael Thomas
> LSC SFAE
> for the latest info on Lattice products - http://www.latticesemi.com

Mike,

I read up on the Mach4384V and it seems it is 5 volt tolerant if you use
the LVCMOS IO type and don't use more than 64 pins this way.  I need TTL
input/outputs (5 volt compatible) and I need about 90 of them.  Any
solution other than to use two chips?  

I am also finding rather high list pricing.  What is a reasonable
expectation for pricing on the LC4256V-10F256BC and LC4384V-10F256C?  I
can ask the distis, but I usually get list price unless I do a real song
and dance and I just need a realistic budgetary number.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 46869
Subject: Modelsim-Altera gate level simulation
From: prashantj@usa.net (Prashant)
Date: 10 Sep 2002 09:25:54 -0700
Links: << >>  << T >>  << A >>
Hi,

I have synthesized a 150K gate design using Quartus 2. I used the
modelsim version provided with Altera to simulate the RTL for my
design. Now I'm trying to simulate the gate level netlist for the
design. The simulation takes a long time compared to RTL and I figured
that was due to a lot of factors including not having the complete
version for Modelsim.

The gate level simulation results did not match the RTL simulation. So
I wanted to check some internal signals to figure out what was going
wrong and where. Here's the problem :

I can view the signals of my testbench in modelsim. If I try to view
the internal signals in the gate level netlist, Modelsim tries to load
all the internal signals, which is in thousands. Basically, this
loading has been running for hours and I'm not sure if it will ever
get loaded.

My question : 

Is there a way to load a specific internal signal instead of all of
them in Modelsim ?

How do people using Modelsim for gate level simulations troubleshoot
their gate level designs ?

I can't see how I would troubleshoot my gate level sim without
checking the internal signals.

Any ideas ?

Thanks,
Prashant

Article: 46870
Subject: Re: C/C++ to Verilog/VHDL ?!
From: Pierre-Olivier Laprise <plapri@tesserae.McRCIM.McGill.EDU>
Date: Tue, 10 Sep 2002 16:46:05 GMT
Links: << >>  << T >>  << A >>
  If your algorithm is that big, perhaps, it isn't suited to FPGA
implementation?  You have to realize that although FPGAs have gotten
quite large, the routing overhead means that they can't run at clock
speeds that are as high as specialized CPUs.  This means that for
algorithms that are rather sequential in nature, it is still much more
advantageous to use a uP.  You have to be sure that the hardware will be
replacing sufficient instructions to make it worthwile.  If you use it
as a co-processor, you also have to take into account communication
latencies between your processing elements.  And all this supposes that
your final design will even fit on an FPGA, which is never a guarantee.

Pierre-Olivier

Frank Andreas de Groot <nospam@nospam.com> wrote:
> You are right but my problem is twofold, first I don't know VHDL, I bought a
> book about digital design and VHDL and it's pretty straightforward, but the
> main thing is, my "algorithm" is huge in hardware, I couldn't easily make
> that within a year... If I would specify it in C, it would be several nested
> loops with lots of pattern recognition and very complex decisions. No way I
> will ever get that to work in VHDL. And I need to tweak it all the time,
> radically change it maybe, and I can start all over again in VHDL...
> We are talking about a newbie here, trying to put some major artificial
> intelligence into a FPGA...

> My idea was to code in C/Java, get a slow but working FPGA fast to play
> with, slowly learn VHDL at the same time, and replace more and more of my
> C/Java by handcoded VHDL. Comparable to coding a quick prototype, a proof of
> concept in Visual Basic, and then refining routine by routine, after which
> you hand-optimize it in assembly...

> In 1 week I'll get the board and I'm very anxious to get started...
> I'll sure try to code some Verilog or VHDL myself. I *need* the end result
> to be as fast as possible. It might even be that there is no gain at all
> when using a high-level procedural language converter...

> Frank


> "John Jakson" <johnjakson@earthlink.net> wrote in message
> news:38111bbc.0209090832.50335d7a@posting.google.com...
>>
>> Instead of beating on C/C++/Java/.. to create HDL logic, you really
>> could do a better job the other way around.




Article: 46871
Subject: Re: Xilinx Parallell Cable IV and Wine
From: Troy Schultz <tschultz@canada.com>
Date: Tue, 10 Sep 2002 16:52:34 GMT
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> Hallo,
> 
> has anybody used a Xilinx Parallell Cable IV with the Xilinx supplied
> software with Wine?
> 
> There are success reports for the Type III cable, but the Type IV cable
> seems to use IEEE1284 feature, which probably require a driver which probably
> will make Wine stumble...
> 
> But the type III cable ( with published schematics versus propriatary
> hardware for the type IV cable) is not specified for the 1.8 Volt signaling
> used on the JTAG port of the coolrunner II...
> 
> Any ideas welcome

I don't normally use wine, but the Cable IV works fine with VMware under 
Linux running Win98 as a guest OS.

- Troy



Article: 46872
Subject: Re: XCR3384XL availability
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 10 Sep 2002 09:53:02 -0700
Links: << >>  << T >>  << A >>


rickman wrote:

>
> I read up on the Mach4384V and it seems it is 5 volt tolerant if you use
> the LVCMOS IO type and don't use more than 64 pins this way.

> I need TTL
> input/outputs (5 volt compatible) and I need about 90 of them.  Any
> solution other than to use two chips?

The most likely problem area is the "5-V tolerance". The manufacturer does not want
you to apply 5.5 V to the inputs, since this might, in the long run, overstress the
dielectric.
A series resistor is no help, since there is no current...
So ask yourself: Does the "TTL" driver really drive 5.5 V or even 5 V?
Bipolar TTL stays one (or two) diode drop(s) below Vcc, which might be safe, but I
would add a bleeding resistor to ground to be sure.( 10 to 100 kilohm). True CMOS
does drive to the Vcc rail.

For the IC manufacturer, 5-V tolerance is an awful requirement, leading to all sorts
of ugly compromises between chip size (cost), speed, and reliability. And 3.3-V
tolerance is heading the same way.
There is a price you pay for all the great capabilities of the newest parts. If it
doesn't fit, use the old-fashiond parts.

And BTW, idle current (quiescent current) is also going up, since transistors are
not completely cut off at the low supply voltages ( 1.5 V and below). One nanoamp
times hundred million transistors becomes real current  :-)

Peter Alfke, Xilinx Applications


Article: 46873
Subject: Re: OrCAD 9.2 Capture Part Library For SpartanXL&18VXX
From: strut911@hotmail.com (strut911)
Date: 10 Sep 2002 10:00:05 -0700
Links: << >>  << T >>  << A >>
Although it may sound lazy, I can understand the desire to look for an
Orcad part. If you draw your own part, then you run the risk of making
an error in the pinout. This may seem trivial for a low pincount part,
but with BGAs having pins that are in the 1000 range, it is a pain in
the ass to check each pin to make sure it is correctly named and the
pin number is correct. Since OrCad is a very popular schematic capture
tool, that is why it seems like OrCad users are always asking for
parts. I have noticed that Viewdraw, although it is also a nice tool,
does not have the market penetration that OrCad Capture does. Since
there are many OrCad users, then the parts can usually be
interchangeable between those users.
   Unfortunately, there is no online movement to create a repository
of known-good parts that people can draw from. I wish that OrCad would
push for something like this because it would definitely set their
tool apart from the rest. They have attempted to do something like
this with their online CIS database, but I am not sure what happened
to that. Anyhow, just wanted to put in my 2 cents. Would be nice if
there were some kind of design exchange repository where people could
put their symbols.
chris

Article: 46874
Subject: Re: atmel CPLD documentation
From: Troy Schultz <tschultz@canada.com>
Date: Tue, 10 Sep 2002 17:00:05 GMT
Links: << >>  << T >>  << A >>
George Eccles wrote:
> I am considering using an Atmel ATF15xx series CPLD.  This would be my
> first PLD of any sort, and I'm a little bit floundering.  For
> instance, the part data sheet says that outputs can be configured for
> "open-collector" (open drain?) operation; but, I don't find any
> mention of that in the  "Programmer's Reference Guide".
> 
> Is there other documentation on these parts?  Or, is there a better
> way to learn this stuff?
> 
> Thanks,
> George
> 
> 
> -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
> http://www.newsfeeds.com - The #1 Newsgroup Service in the World!
> -----==  Over 80,000 Newsgroups - 16 Different Servers! =-----

Last spring I started out with the Atmel ATF15xxx series, mostly due to 
their logic doubling feature.  I ran into a large number of problems 
with their software.

Finally after wasting many hours I switched over to the Xilinx XC95 
series parts.  I used thier free webpack software and had a working 
prototype done within 3 days including PCB changes.  The free webpack 
can handle the entire line of Xilinx CPLDs.

The Atmel parts are probably OK, but I have no intention of ever looking 
at them again because of their software issues.

In the end the Xilinx part also came in cheaper too.

All I want to say is make sure you do your homework first, and take a 
look at what is available for both the hardware and supporting software.

- Troy




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