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Messages from 47600

Article: 47600
Subject: Re: Dual Port RAM
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Mon, 30 Sep 2002 18:38:21 +0100
Links: << >>  << T >>  << A >>


Muzaffer Kal wrote:

> On Fri, 27 Sep 2002 18:15:14 +0000 (UTC),
> nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote:
>
> >In article <91710219.0209270400.3af5b3ca@posting.google.com>,
> >Nagaraj <nagaraj_c_s@yahoo.com> wrote:
> >>Hello,
> >>   Thanx for the reply.
> >>   I require around 48K bits of memory. An XCV50E/XC2V40 should do the
> >>job. Thats fine.
> >>   Now regarding your question about using memory in the existing
> >>FPGA. I have my core logic plus the memory in the existing FPGA. In
> >>the final product, the core logic will be converted to ASIC. But I am
> >>not sure about the memory. Because as I understand it is difficult to
> >>implement memory in ASIC of my required size (not digital ASIC) in
> >>terms of process as well as cost, compared to external chip. First of
> >>all, is this true? If so, I have to have another FPGA to implement
> >>memory, as you told.
> >
> >Why would an ASIC have trouble with memory?  Just about every ASIC
> >process would have to have various memory blocks in the library which
> >you could use, otherwise you would go completely crazy.
>
> Actually you get what's called a memory compiler which generates
> various types and sizes of memory just as the FPGA tools do (genmem in
> A or coregen in X).
>
> Here is an example: http://www.artisan.com/products/memory/
>
> This and other memory compilers from library vendors generate a
> simulation model and the physical design of the memories (in GDS2 and
> LEF format) so that you can instantiate them in your RTL and do P&R
> with a tool like SE.
>

Now all we need is to get the ASIC synth tool to infer memory from the HDL and invoke the
memory compiler to produce the right memories ....



Article: 47601
Subject: Diving in for the first time
From: jlcooke@engsoc.carleton.ca (Jean-Luc Cooke)
Date: 30 Sep 2002 11:39:42 -0700
Links: << >>  << T >>  << A >>
Goodday all,

I'm looking for some help with a personal project I'm starting.  I'd
like to know of any comparisons between vendors and products.  Pricing
is important, but performance (clock speed and logic element count)
are more important.

The computationally intensive math function I'm looking to implement
in hardware consists of ANDs ORs XORs NOTs and (important!) a 32bit
ADDITION.

The math function has 128bits of input, and 128bits of output.  It is
cryptographic in nature.  Intermetiate 128bit values though the
function need to be latched so I can have 64 computations on the go at
once.  Thismeans flip-flops.

Ideally this implementation would have 16,32,64,1024 parallel
implementations on the same FPGA/whatever.

What are recomended FPGA products and vendors.  Anyone here with
expirience with large/fast FPGA designs?  The thoughput produced by
this dvice will be about:

outputRate = 2^32 / (clockRate * parallelizum)

And I will need to give each of the parallel instances a 128bit START
value.

I'm a system + computer engineering graduate who has done Verilog
before (rusty!) but only ran my designs in FPGA _once_. 
Advice/guidence from you experts is appriciated.

JLC

Article: 47602
Subject: correction
From: jlcooke@engsoc.carleton.ca (Jean-Luc Cooke)
Date: 30 Sep 2002 11:42:36 -0700
Links: << >>  << T >>  << A >>
In my previous post I stated:

outputRate = 2^32 / (clockRate * parallelizum)


It will be infact:

outputRate = (clockRate * parallelizum) / 2^32

So Serial communications may not be sufficant.  Discussion on
circumventing I/O blockage from the parallel implementations is very
much welcome.

JLC

Article: 47603
Subject: Simulating mixed Verilog and VHDL files
From: Tinoosh Mohsenin <tinoosh@ece.rice.edu>
Date: Mon, 30 Sep 2002 13:57:49 -0500
Links: << >>  << T >>  << A >>
Hi,
I'm using mixed Verilog and VHDL files to implement on FPGA ,I was
wondering how I can use Project Navigator in ISE Xilinx 4.2 to simulate
these files and also synthesized them.Because it seems that it can not
read a project with mixed files.
Right now the only soultion I got is: to synthesize the project in
Synplicity and generate the .edif file which is readable by Project
Navigator and then place and route in Project Navigator .
Please let me know if there is a way to simulate and synthesize these
files in the same project,
Thanks,
Tinoosh


Article: 47604
Subject: FFT in FPGA?
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Mon, 30 Sep 2002 15:32:48 -0400
Links: << >>  << T >>  << A >>
Hi,
    A grad student working for me is proposing using an FPGA to do some
signal processing.  The algorythm will compute a cross-corelation between
two 16 bit signals.  The algorythm requires 2 2048pt FFT's and a 2048pt
inverse FFT.  What kind of size FPGA and/or what kind of speed can one
expect using a hardware based design (i.e. FPGA based design)?  I suspect
that the virtex2 is the only chip to seriously condsider.  What size chip
should one be considering?  We need to compute the cross-corelation 300
times per second.  If it is substantially easier ("do-able") we could
perhaps get by with 1024 point data records.  What we are trying to do is
find the time delay between the first and second echos of a 220KHz
ultrasonic ping.

Thanks,
Theron Hicks



Article: 47605
Subject: Re: FFT in FPGA?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 30 Sep 2002 19:58:27 GMT
Links: << >>  << T >>  << A >>
One of the original XCV1000's has sufficient memory, and several times the
number of CLBs needed to do it at 100MHz.  In fact, we've got a design going
into space that uses an XCV1000 to do 4K complex FFT's and IFFTs for complex
convolution for a radar pre-processor (exactly what you are doing, only at a
much higher rate, and another that does 1/3 overlapped continuous 4K block
floating point FFTs on a 100MS/sec data stream (that uses a pair of
XCV1000's, more memory would have gotten it into one part).
 In any event, on-chip memory is often the limiting factor.  Virtex has less
memory than virtexE which has less than virtexII.  We have a paper design for
a 1024 point FFT for an XC2V40.  It is quite a bit slower because it has a
smaller kernel and therefore needs to do more passes...it would probably
still meet your needs though.  Also, since your data is apparently not
complex, you can use the double size real only conversion to get a 2K
real-only FFT out of a 1K complex core.


Theron Hicks wrote:

> Hi,
>     A grad student working for me is proposing using an FPGA to do some
> signal processing.  The algorythm will compute a cross-corelation between
> two 16 bit signals.  The algorythm requires 2 2048pt FFT's and a 2048pt
> inverse FFT.  What kind of size FPGA and/or what kind of speed can one
> expect using a hardware based design (i.e. FPGA based design)?  I suspect
> that the virtex2 is the only chip to seriously condsider.  What size chip
> should one be considering?  We need to compute the cross-corelation 300
> times per second.  If it is substantially easier ("do-able") we could
> perhaps get by with 1024 point data records.  What we are trying to do is
> find the time delay between the first and second echos of a 220KHz
> ultrasonic ping.
>
> Thanks,
> Theron Hicks

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47606
Subject: Re: design multiplier
From: Ray Andraka <ray@andraka.com>
Date: Mon, 30 Sep 2002 20:04:06 GMT
Links: << >>  << T >>  << A >>
This is true if you are trying to multiply signals.  However, I believe his post was
asking about multiplying clocks, in which case he needs either a PLL or DLL to do
it.  The speeds you mentioned are dependent on number of bits as well as signal
loading, routing and placment.  You can substantially improve the numbers with some
floorplanning (the virtexE number looks quite low, and the virtexII number is
slightly higher than what can be had consistently with a 16 bit carry chain).

Farhad Abdolian wrote:

> The easiet way to do it, is to shift your signal 1 bit to the ledt and then  add
> it to the signal, it gives you 2+1=3 and it can easily be implemented inside a
> FPGA at 100 MHz, a hardware multiplier is good if you want to multiply larger
> values, but in your case, it is easier to make a simple multiplier yourself.
> Leonardo reporter 122 MHz for Spartan II and , 120.1 MHz for Virtex, 130.1 MHz
> on Virtex E and 206.0 MHz on a virtex 2.
>
> For Altera, Acex 1k gave  69.2 MHz, 185.0 MHz for Apex 20C and 192.3 MHz on a
> Apeck 20K.
>
> The actual maximum frequency you can run, is normaly very different than these
> values, and highly dependent on your system, number of bits etc.
>
>

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47607
Subject: Re: design multiplier
From: Farhad Abdolian <farhad_abdolian@removethis_first_hotmail.com>
Date: Mon, 30 Sep 2002 20:47:13 GMT
Links: << >>  << T >>  << A >>
Hi Ray,
I know, I got if after I received the other message (my SMTP is very slow in
getting new messages sometimes).

I completely agree with the facts you mention here, it was a quick test that I
did long time ago when one of our analog engineers wanted to design a digital
AGC running at 200 MHz with a lot of logic and 3-18 bits busses, I just cleaned
up that test and did this to show how it is, but as you mentioned, it was not
about multiplying values, but a single signal, and I think the other answer was
much better than mine :)

/Farahd
Ray Andraka <ray@andraka.com> wrote:

>This is true if you are trying to multiply signals.  However, I believe his post was
>asking about multiplying clocks, in which case he needs either a PLL or DLL to do
>it.  The speeds you mentioned are dependent on number of bits as well as signal
>loading, routing and placment.  You can substantially improve the numbers with some
>floorplanning (the virtexE number looks quite low, and the virtexII number is
>slightly higher than what can be had consistently with a 16 bit carry chain).
>
>Farhad Abdolian wrote:
>
>> The easiet way to do it, is to shift your signal 1 bit to the ledt and then  add
>> it to the signal, it gives you 2+1=3 and it can easily be implemented inside a
>> FPGA at 100 MHz, a hardware multiplier is good if you want to multiply larger
>> values, but in your case, it is easier to make a simple multiplier yourself.
>> Leonardo reporter 122 MHz for Spartan II and , 120.1 MHz for Virtex, 130.1 MHz
>> on Virtex E and 206.0 MHz on a virtex 2.
>>
>> For Altera, Acex 1k gave  69.2 MHz, 185.0 MHz for Apex 20C and 192.3 MHz on a
>> Apeck 20K.
>>
>> The actual maximum frequency you can run, is normaly very different than these
>> values, and highly dependent on your system, number of bits etc.
>>
>>


Article: 47608
Subject: Re: ... milk for free, Opencores?
From: "MikeJ" <mikejNO SPAM@freeuk.com>
Date: Mon, 30 Sep 2002 23:13:14 +0100
Links: << >>  << T >>  << A >>
Well said Rudolf !

"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message
news:d44097f5.0209282141.7c5b9355@posting.google.com...
> I am one of the contributors to OpenCores.
>
> The goal here is to create a large and mature IP library that can
> be used by commercial users. The hope is that we will get cheaper
> and/or better quality hardware faster that we might otherwise. I
> have worked for several commercial companies where the "next
> generation" product was delayed by 1-2 years to "milk" the previous
> product and extend it's live.That kind of strategies make me as
> an engineer and consumer very angry.
>
> Another item that disturbs me is the artificially blown up "R&D"
> budgets at some companies. These R&D budgets are financed from the
> hardware sale. Some of those R&D departments are a joke ! Companies
> like IBM seem to have R&D departments that every couple of months
> come up with something new and cool they have developed. 80% of
> other companies with huge R&D devisions, just burn the money without
> producing anything.
>
> How do we make money ? As somebody already mentioned, providing
> the IP core is just a small part of the job. You will find IP cores that
> are quite decent designs and work of professionals and you will also
> find projects that have not been completed in the last few years.
> To take an IP core from it's source form and put it in to an ASIC is
> a lot of work. My company is trying to adopt the model that seems to
> work for software companies (like RedHet for example): Get the core
> for free, but please buy support if you are going to use it. And no, I
> will not *force* a commercial client to buy support or pay me.
>
> In the past OpenCores has been supported in one way or another by
> many different sponsors. There is even a sponsors page up. One
> company (Flextronics Semiconductor of Israel) even payed some
> of us to develop a few cores that they wanted for one of their projects.
> I think that was very nice of them. They got what they needed, the
> community got something for free, and the developers where able to
> pay their bills ! The best thing about the deal with Flextronics was
> that the cores that where developed in that deal, where very mature
> and complete implementations. They where complete with all test
> benches, documentation and where synthesized and tried in silicon.
> What else could one dream of ?
>
> Why didn't you guys CC this to the oOpenCores mailing list ?!
>
> Best Regards,
> rudi (Will write IP cores for food ;*)
>
> ----------------------------------------------
> www.asics.ws - Solutions for your ASIC needs -
>
>
>
> Colin Marquardt <c.marquardt@alcatel.de> wrote in message
news:<k8z7khq6tj7.fsf@alcatel.de>...
> > hmurray@suespammers.org (Hal Murray) writes:
> >
> > >>While I'm a big "information needs to be free" kind of guy, it seems
> > >>kind of strange to me that the primary contributers are individuals,
> > >>and the main beneficiaries (financially) are business entities.
> > >>Aren't these kinds of projects usually handled under a "use limited to
> > >>not for profit" arrangement?  Kind of like shareware WS-FTP, if you're
> > >>using it at school go ahead, but if you're making money using it, you
> > >>shell out your $30. Otherwise all that we've accomplished is reducing
> > >>corporate NRE at engineers' expense.
> > >
> > > I'm not sure Opencores is over the hump yet.  For small things
> > > it's as easy/cheap to reinvent the solution as it is to integrate
> > > some external package into your project.  For large complicated
> > > cores/packages it really helps to have lots of users helping to find
> > > (and fix) all the bugs.
> >
> > As was already hinted either here or some other EDA newsgroup some while
> > ago, a big electronics company headquartered in Singapore is/was
employing
> > people to contribute to opencores.org.  If details can be made public, I
> > would like to know about them.
> >
> > Cheers,
> >   Colin



Article: 47609
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: Dali <dadicool@ifrance.com>
Date: Mon, 30 Sep 2002 23:57:19 +0000
Links: << >>  << T >>  << A >>
It doesn't work that way. In order to take advantage of the clock tree 
brovided by the BUFG primitive you need to use an IBUFG instead of an 
IBUF. So a normal IO pins does not do the job.

For further details, look at the Xilinx Handbook.

Dali

Ho Wong wrote:
> Hello. I'm using a pin to drive a process but the thing is that it's already
> been soldered onto a normal IO pin. I've been trawling through past posts
> and newsgroups and I still haven't found a answer yet. I'm just a beginner
> to fpgas so i'm not very familiar with the low level logics. I tried doing
> PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has
> illegal connection  Would it be possible to short my normal IO to one of the
> dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
> Webpack.
> 
> 



Article: 47610
Subject: Re: design multiplier
From: D Lee <dennislwm@hotmail.you>
Date: 30 Sep 2002 23:59:56 GMT
Links: << >>  << T >>  << A >>
Thank you all for your replies.

It seems that I need a PLL or DLL to do this. I know
a PLL is a phase-locked loop, but what is a DLL?

Thanks again.

Dennis

Article: 47611
Subject: Re: design multiplier
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Oct 2002 00:12:51 GMT
Links: << >>  << T >>  << A >>
A delay lock loop.  It is an all digital analog to a PLL
that uses a variable delay line.  The xilinx FPGAs use these
because they are all digital and not as fussy with power
supply conditioning.  They do have their own set of
idiosyncracies, the most bothersome is that unlike a PLL
they add jitter.

D Lee wrote:

> Thank you all for your replies.
>
> It seems that I need a PLL or DLL to do this. I know
> a PLL is a phase-locked loop, but what is a DLL?
>
> Thanks again.
>
> Dennis

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin
Franklin, 1759



Article: 47612
Subject: Re: design multiplier
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 30 Sep 2002 17:33:51 -0700
Links: << >>  << T >>  << A >>
A DLL is a Delay-Locked Loop. It uses chains of cascaded buffers, and is
totally digital ( good, because that makes it rather insensitive to
supply-voltage variations), but a DLL does not reduce the incoming
jitter, which a PLL can, at least theoretically. In practice there is a
residual jitter that is extremely hard to reduce.

On paper, PLLs have  advantages. In reality the more robust DLL beats a
PLL in most respects.

See the Virtex data sheets for a DLL, and the Virtex-II data sheets for
the Digital Clock Manager, which is a DLL+ with many additional
features.
It can generate delays in programmable steps of 40 ps (i.e. you can
achieve any one of 256 possible delays within a 100 MHz clock period).
That has very interesting possibilities in interface design and also in
testing...
I have struggled with analog PLLs in my prior life, I prefer digital
DLLs now, far less headache...

Peter Alfke, Xilinx Applications
================================
D Lee wrote:

> Thank you all for your replies.
>
> It seems that I need a PLL or DLL to do this. I know
> a PLL is a phase-locked loop, but what is a DLL?
>
> Thanks again.
>
> Dennis


Article: 47613
Subject: Re: FFT in FPGA?
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Mon, 30 Sep 2002 21:37:50 -0400
Links: << >>  << T >>  << A >>
Ray,
I had hope that you would respond but I didn't want to put you on the spot.  I
really appreciate the input.  Now I can get my boss to go for some funding with
confidence (on my part) that this is really do-able.

Thanks

Ray Andraka wrote:

> One of the original XCV1000's has sufficient memory, and several times the
> number of CLBs needed to do it at 100MHz.  In fact, we've got a design going
> into space that uses an XCV1000 to do 4K complex FFT's and IFFTs for complex
> convolution for a radar pre-processor (exactly what you are doing, only at a
> much higher rate, and another that does 1/3 overlapped continuous 4K block
> floating point FFTs on a 100MS/sec data stream (that uses a pair of
> XCV1000's, more memory would have gotten it into one part).
>  In any event, on-chip memory is often the limiting factor.  Virtex has less
> memory than virtexE which has less than virtexII.  We have a paper design for
> a 1024 point FFT for an XC2V40.  It is quite a bit slower because it has a
> smaller kernel and therefore needs to do more passes...it would probably
> still meet your needs though.  Also, since your data is apparently not
> complex, you can use the double size real only conversion to get a 2K
> real-only FFT out of a 1K complex core.
>
> Theron Hicks wrote:
>
> > Hi,
> >     A grad student working for me is proposing using an FPGA to do some
> > signal processing.  The algorythm will compute a cross-corelation between
> > two 16 bit signals.  The algorythm requires 2 2048pt FFT's and a 2048pt
> > inverse FFT.  What kind of size FPGA and/or what kind of speed can one
> > expect using a hardware based design (i.e. FPGA based design)?  I suspect
> > that the virtex2 is the only chip to seriously condsider.  What size chip
> > should one be considering?  We need to compute the cross-corelation 300
> > times per second.  If it is substantially easier ("do-able") we could
> > perhaps get by with 1024 point data records.  What we are trying to do is
> > find the time delay between the first and second echos of a 220KHz
> > ultrasonic ping.
> >
> > Thanks,
> > Theron Hicks
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759


Article: 47614
Subject: Configuration:Startup
From: Cisa <jjyy@hotmail.com>
Date: Mon, 30 Sep 2002 18:45:12 -0700
Links: << >>  << T >>  << A >>
I have configured a virtex-e device,
and DONE goes high,INIT also goes high .That indicates that configuration has finished,but the device can't start to work.
I suspect the virtex-e does not finish the STARTUP sequence.
Is it necessary to instantiate a STARTUP_VIRTEX module in my verilog design for STARTUP sequence?

Article: 47615
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: Dali <dadicool@ifrance.com>
Date: Tue, 01 Oct 2002 01:50:25 +0000
Links: << >>  << T >>  << A >>
How fast is your clock?

If you can ignore signal integrity issues, I would say, put a wire from 
the actual pin and the pin the package that is connected to an IBUFG.

The problem about general purpose IOs and routing is that the P&R tool 
does not guarantee any skew limits on the clock if you're not using a 
Global Buffer. I have seen 5 to 6ns skew on a VirtexE part when I used 
general purpose routing for a clock.

Dali

Ho Wong wrote:
> So is there a way at all to clock this process without having to use the
> bufg? And is it possible to short the two pins together? (current non-global
> to a global one)
> "Dali" <dadicool@ifrance.com> wrote in message
> news:3D98E4DF.3010100@ifrance.com...
> 
>>It doesn't work that way. In order to take advantage of the clock tree
>>brovided by the BUFG primitive you need to use an IBUFG instead of an
>>IBUF. So a normal IO pins does not do the job.
>>
>>For further details, look at the Xilinx Handbook.
>>
>>Dali
>>
>>Ho Wong wrote:
>>
>>>Hello. I'm using a pin to drive a process but the thing is that it's
>>
> already
> 
>>>been soldered onto a normal IO pin. I've been trawling through past
>>
> posts
> 
>>>and newsgroups and I still haven't found a answer yet. I'm just a
>>
> beginner
> 
>>>to fpgas so i'm not very familiar with the low level logics. I tried
>>
> doing
> 
>>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN
>>
> has
> 
>>>illegal connection  Would it be possible to short my normal IO to one of
>>
> the
> 
>>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
>>>Webpack.
>>>
>>>
>>
>>
> 
> 



Article: 47616
Subject: Search help about architecture of STARTUP?
From: Cisa <jjyy@hotmail.com>
Date: Mon, 30 Sep 2002 19:14:03 -0700
Links: << >>  << T >>  << A >>
I instantiate a STARTUP_VIRTEX template in my verilog design,and use the input signal GSR to reset my FFs.When I view my routed design in FPGA Editor of ISE,I can see the input signals of STARTUP,but I can't see the output signal of STARTUP to reset my FFs.
Is it a right implementation result?
Can you give me a detailed explanation of architecture about STARTUP module in virtex?And what is the right method to instantiate a STARTUP_VIRTEX in unimsims library?

Article: 47617
Subject: Re: Search help about architecture of STARTUP?
From: Spam Hater <spam_hater_7@email.com>
Date: Tue, 01 Oct 2002 04:18:18 GMT
Links: << >>  << T >>  << A >>

You can't "see" the output of the startup module.

It uses dedicated routing resources, which are not displayed by the
route editor.

Try it out; it's probably working.

SH7

On Mon, 30 Sep 2002 19:14:03 -0700, Cisa <jjyy@hotmail.com> wrote:

>I instantiate a STARTUP_VIRTEX template in my verilog design,and use the input signal GSR to reset my FFs.When I view my routed design in FPGA Editor of ISE,I can see the input signals of STARTUP,but I can't see the output signal of STARTUP to reset my FFs.
>Is it a right implementation result?
>Can you give me a detailed explanation of architecture about STARTUP module in virtex?And what is the right method to instantiate a STARTUP_VIRTEX in unimsims library?


Article: 47618
Subject: TCP/IP in FPGA
From: "geeko" <jibin@ushustech.com>
Date: Tue, 1 Oct 2002 10:24:41 +0530
Links: << >>  << T >>  << A >>
What are the chances of implementing a TCP/IP stack using VHDL anybody do
anything similar.Can the Spartan FPGA be used to hold the design



Article: 47619
(removed)


Article: 47620
(removed)


Article: 47621
Subject: DFT , Design For Test HELPPPPP
From: "Djohn" <deepucjohn@yahoo.com>
Date: Tue, 1 Oct 2002 11:41:22 +0530
Links: << >>  << T >>  << A >>
Hi all,
  I am now designing a Uart chip for study purposes. Now I am almost over
with my design and VHDL Coding .  I would like to integrate the DFT strategy
in the chip .

1)what are the different methods by which i can implement "Design for Test "
strategy in my chip.

2) I have a fair good knowledge of JTAG . So If I integrate a JTAG circuitry
in the chip (the tap controller , data registers  and instruction
registers), will it become  DFT compatible?

3) What exactly is BIST ? How is it implemented ? Any online  tutorials or
good links ...

4) What is ATPG ? how is it implemented? Any online  tutorials .......

5)Any other DFT strategies other than these.????

6) A comparison between these strategies? any links also welcome

thanks
Djohn






Article: 47622
Subject: Re: TCP/IP in FPGA
From: Janusz Raniszewski <rniski@man.koszalin.pl>
Date: Tue, 01 Oct 2002 08:39:15 +0200
Links: << >>  << T >>  << A >>
> What are the chances of implementing a TCP/IP stack using VHDL anybody do
> anything similar.Can the Spartan FPGA be used to hold the design

Hello,
It is simple. You may implement some microcontroller core and ,,,,,, :-)
JanuszR


Article: 47623
Subject: Rounting of non-global IO pad to a GCLKIOB site.
From: "Ho Wong" <s354411@student.uq.edu.au>
Date: Tue, 1 Oct 2002 16:41:51 +1000
Links: << >>  << T >>  << A >>
Hello. I'm using a pin to drive a process but the thing is that it's already
been soldered onto a normal IO pin. I've been trawling through past posts
and newsgroups and I still haven't found a answer yet. I'm just a beginner
to fpgas so i'm not very familiar with the low level logics. I tried doing
PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has
illegal connection  Would it be possible to short my normal IO to one of the
dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
Webpack.



Article: 47624
Subject: Anyone knows of a example FPGA design which reads and writes a SmartMedia card?
From: "Karl" <Far@East.Design>
Date: Tue, 1 Oct 2002 15:23:14 +0800
Links: << >>  << T >>  << A >>
Anyone knows of a example FPGA design which reads and writes a SmartMedia
card?
What are the stuff I need to read on the net, my design is simple, I want to
read the .wav
files from a SM card and feed this data into a speaker. My board will have a
15K gate
vertex chip and a PWM digital to analog converter and amplifier, plus a
fixture which
connect up the SM card (stripped from a broken SM reader).







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